PR target/16350
* config.gcc: For arm*b-* define TARGET_BIG_ENDIAN_DEFAULT.
* config/arm/linux-elf.h (TARGET_ENDIAN_DEFAULT): Define based on TARGET_BIG_ENDIAN_DEFAULT.
Use for MULTILIB_DEFAULTS.
(TARGET_DEFAULT): Set according to TARGET_ENDIAN_DEFAULT.
(LINUX_TARGET_LINK_SPEC): Pass -mlittle-endian on to the assembler.
* config/arm/linux-eabi.h (TARGET_LINKER_EMULATION): Set according to TARGET_BIG_ENDIAN_DEFAULT.
(SUBTARGET_EXTRA_LINK_SPEC): Likewise.
* gcc/config/arm/bpabi.h (TARGET_DEFAULT_MASK): Set according to TARGET_BIG_ENDIAN_DEFAULT.
From-SVN: r129999
* config.gcc: For a FreeBSD target, parse the value of ${target}
to determine the value of FBSD_MAJOR, instead of adding an
explicit check for every possible FreeBSD major version.
From-SVN: r129590
2007-10-18 David S. Miller <davem@davemloft.net>
Add Niagara-2 support.
* doc/invoke.texi: Document -m{cpu,tune}=niagara2.
* config.gcc: Add niagara2 to cpu and tune lists for sparc.
* config/sparc/sparc.md (sparc_cpu_attr): Add niagara2.
(include): Add inclusion of niagara2.md
* config/sparc/sparc.c (niagara2_costs): New.
(sparc_override_options): Add niagara2 entry to cpu_default[]
and cpu_table[]. Set align_functions to 32 on Niagara2. Use
niagara2_costs when PROCESSOR_NIAGARA2. Handle Niagara2 for
PARAM_SIMULTANEOUS_PREFETCHES and PARAM_L1_CACHE_LINE_SIZE.
(sparc_initialize_trampoline): Handle niagara2 like niagara.
(sparc64_initialize_trampoline): Likewise.
(sparc_use_sched_lookahead): Likewise.
(sparc_issue_rate): Likewise.
* config/sparc/sol2-bi.h: Handle TARGET_CPU_niagara2 and
mcpu=niagara2
* config/sparc/sparc.h (TARGET_CPU_niagara2): Define.
({CPP,ASM}_CPU64_DEFAULT_SPEC): Set appropriately for
TARGET_CPU_niagara2.
(PROCESSOR_NIAGARA2): New.
(REGISTER_MOVE_COST): Handle PROCESSOR_NIAGARA2.
(BRANCH_COST): Likewise.
* config/sparc/linux64.h: Handle TARGET_CPU_niagara2.
* config/sparc/sol2.h: Likewise.
* config/sparc/niagara2.md: New file.
From-SVN: r129472
2007-09-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
* config.gcc (powerpc*-*-*): --with-cpu=cell is a 64bit CPU.
Allow --with-tune=cell and --with-cpu=cell.
From-SVN: r128721
gcc/
2007-09-14 Nigel Stephens <nigel@mips.com>
* config.gcc (mips*-*-linux*): Recognise mipsisa32r2 and set
MIPS_ISA_DEFAULT appropriately. Don't make soft-float the default
for mipsisa32-*-linux*.
From-SVN: r128498
* configure.ac (mips*-sde-elf*): New stanza. Add target-libiberty
to $skipdirs and only disable gprof for newlib. Use the normal
mips*-elf* handling in other respects.
* configure: Regnerate.
gcc/
2007-xx-xx Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
Thiemo Seufer <ths@mips.com>
Richard Sandiford <richard@codesourcery.com>
* config.gcc (mips*-sde-elf*): Add support for the SDE C libraries.
* configure.ac: Add a mipssde threading type.
* configure: Regenerate.
* config/mips/sdemtk.h: New file.
* config/mips/t-sdemtk: Likewise.
* config/mips/sdemtk.opt: Likewise.
* gthr-mipssde.h: Likewise.
* config/mips/sde.h (FUNCTION_PROFILER): Move to config/mips/sdemtk.h.
* config/mips/mips.h (MIPS_SAVE_REG_FOR_PROFILING_P): New macro.
(MIPS_ICACHE_SYNC): New macro, split from ...
* config/mips/mips.md (clear_cache): ...here.
* config/mips/mips.c (mips_save_reg_p): Check
MIPS_SAVE_REG_FOR_PROFILING_P on profiled functions.
(build_mips16_function_stub): Use targetm.strip_name_encoding.
(build_mips16_call_stub): Likewise.
libstdc++-v3/
2007-xx-xx Thiemo Seufer <ths@mips.com>
* crossconfig.m4 (mips*-sde-elf*): New stanza.
* configure: Regenerate.
From-SVN: r128495
* gcc/config/i386/cpuid.h: New file.
* gcc/config/i386/driver-i386.c: Include cpuid.h.
(describe_cache): Shrink size and line strings to 100 bytes.
(detect_caches_amd): Return "" for unsupported max_ext_level.
Use __cpuid function.
(detect_caches_intel): Return "" for unsupported max_level.
Use __cpuid function.
(host_detect_local_cpu): Change feature flag variables to
unsigned int. Initialize only extended feature flag variables.
Use __get_cpuid_max to determine max supported cpuid level.
Use __cpuid function to determine supported features. Fix
calculation of family id. Remove is_amd and check signature
directly. Check for Geode signature. Handle family 4 id.
[PROCESSOR_GENERIC32]: New default for unknown family id. Move
cpu discovery code to other part of the function.
[PROCESSOR_PENTIUM, PROCESSOR_K6, PROCESSOR_ATHLON]: Do not tune
for sub-architecture.
[PROCESSOR_PENTIUMPRO]: Simplify cpu discovery code.
[PROCESSOR_K8]: Add k8-sse3 architecture.
[PROCESSOR_GENERIC64]: Remove.
* gcc/config/i386/x-i386 (driver-i386.o): Depend on cpuid.h.
* gcc/config/i386/crtfastmath.c: Include cpuid.h. Use __get_cpuid
to check for SSE and FXSAVE support.
* gcc/config/i386/t-crtfm (crtfastmath.o): Depend on cpuid.h.
Add -minline-all-stringops.
* gcc/config.gcc (i[34567]86-*-*): Add cpuid.h to extra_headers.
(x86_64-*-*): Ditto.
testsuite/ChangeLog:
* gcc.dg/i386-cpuid.h: Remove.
* gcc.target/i386/mmx-check.h: Include cpuid.h. Use __get_cpuid.
* gcc.target/i386/sse-check.h: Ditto.
* gcc.target/i386/sse2-check.h: Ditto.
* gcc.target/i386/sse3-check.h: Ditto.
* gcc.target/i386/ssse3-check.h: Ditto.
* gcc.target/i386/sse4_1-check.h: Ditto.
* gcc.target/i386/sse4_2-check.h: Ditto.
* gcc.target/i386/sse4a-check.h: Ditto.
* gcc.dg/torture/pr16104-1.c: Ditto.
* gcc.target/i386/mmx-4.c: Do not use NOINLINE.
* gcc.target/i386/sse-6.c: Ditto.
* gcc.target/i386/sse-7.c: Ditto.
* g++.dg/other/i386-1.C: Include cpuid.h.
(main): New function. Use __get_cpuid to check target fetaures.
libgomp/ChangeLog:
* testsuite/libgomp.c/atomic-1.c: Include cpuid.h for i386 targets.
(main): Use __get_cpuid to get i386 target fetaures.
* testsuite/libgomp.c/atomic-2.c: Include cpuid.h for x86_64 targets.
(main): Use __get_cpuid to get x86_64 target fetaures.
From-SVN: r128141
2007-09-04 Andrew Pinski <andrew_pinski@playstation.sony.com>
* config.gcc (powerpc*-*-*): Install
spu2vmx.h, vec_types.h, and si2vmx.h headers.
* config/rs6000/spu2vmx.h: New header.
* config/rs6000/si2vmx.h: New header.
* config/rs6000/vec_types.h: New header.
2007-09-04 Andrew Pinski <andrew_pinski@playstation.sony.com>
* g++.dg/other/spu2vmx-1.C: New test.
From-SVN: r128118
* config.gcc: Delete stanza for arm-semi-aof and
armel-semi-aof targets.
* config/arm/arm-protos.h
* config/arm/arm.c
* config/arm/arm.h: Delete all #ifdef AOF_ASSEMBLER blocks;
make all #ifndef AOF_ASSEMBLER blocks unconditional. Also
delete aof_pic_label and remove mention of AOF in comments.
* config/arm/arm.md: Delete patterns used only for AOF assembly.
* config/arm/aof.h
* config/arm/semiaof.h
* config/arm/t-semi: Delete file.
From-SVN: r128052
gcc/
* Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi.
* config.gcc (arm*-*-*): Add arm_neon.h to extra headers.
(with_fpu): Allow --with-fpu=neon.
* config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
* config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
* config/arm/arm-modes.def (EI, OI, CI, XI): New modes.
* config/arm/arm-protos.h (neon_immediate_valid_for_move)
(neon_immediate_valid_for_logic, neon_output_logic_immediate)
(neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret)
(neon_emit_pair_result_insn, neon_disambiguate_copy)
(neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad)
(output_move_neon): Add prototypes.
* config/arm/arm.c (FL_NEON): New flag for NEON processor capability.
(all_fpus): Add FPUTYPE_NEON.
(fp_model_for_fpu): Add NEON field.
(arm_return_in_memory): Return vectors <= 16 bytes in ARM registers.
(arm_arg_partial_bytes): Allow NEON vectors to be passed partially
in registers.
(arm_legitimate_address_p): Don't support fancy addressing for NEON
structure moves.
(thumb2_legitimate_address_p): Likewise.
(neon_valid_immediate): Recognize and prepare constants suitable for
NEON instructions.
(neon_immediate_valid_for_move): New function. Recognize and prepare
immediates for NEON move instructions.
(neon_immediate_valid_for_logic): New function. Recognize and
prepare immediates for NEON logic instructions.
(neon_output_logic_immediate): New function. Create asm string
suitable for outputting immediate logic instructions.
(neon_pairwise_reduce): New function. Implement reduction using
pairwise operations.
(neon_expand_vector_init): New function. Expand a (possibly
non-constant) vector initialization.
(neon_vector_mem_operand): New function. Memory operands supported
for quad-word loads/stores to/from ARM or NEON registers. Don't
allow base+offset addressing for core regs.
(neon_struct_mem_operand): New function. Valid mems for NEON
structure moves.
(coproc_secondary_reload_class): Enable NEON registers to be loaded
from neon_vector_mem_operand addresses without a secondary register.
(add_minipool_forward_ref): Handle >8-byte minipool entries.
(add_minipool_backward_ref): Likewise.
(dump_minipool): Likewise.
(push_minipool_fix): Likewise.
(output_move_quad): New function. Output quad-word moves, loads and
stores using ARM registers.
(output_move_vfp): Add support for vectors in VFP (NEON) D
registers.
(output_move_neon): Output a NEON load/store to/from a quadword
register.
(arm_print_operand): Implement new codes:
- 'c' for unadorned integers (without a # sign).
- 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian
mode.
- 'e', 'f' for the low and high D parts of a NEON Q register.
- 'q' outputs a NEON Q register.
- 'h' outputs ranges of D registers for VLDM/VSTM etc.
- 'T' prints NEON opcode features from a coded bitmask.
- 'F' is similar to T, but signed/unsigned codes both print as
'i'.
- 't' is similar to T, but 'u' is printed instead of 'p'.
- 'O' prints 'r' if NEON instruction should perform rounding (as
specified by bitmask), else prints nothing.
- '#' is a punctuation character to stop operand numbers from
running together with following digits in the assembler
strings for instructions (when using mode attributes).
(arm_assemble_integer): Handle extra NEON vector modes. Permute
constant vectors in big-endian mode, where necessary.
(arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers.
Handle EI, OI, CI, XI modes.
(ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3)
(ashrv2si3): Rename IWMMXT2_BUILTINs to...
(ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt)
(lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names.
(neon_builtin_type_bits): Add enumeration, one bit for each vector
type.
(v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP)
(v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros
to turn v8qi, etc. into bits defined above.
(neon_itype): New enumeration. Classifications of NEON builtins.
(neon_builtin_datum): Define struct. Contains information about
a single builtin (with multiple modes).
(CF): Define helper macro for...
(VAR1...VAR10): Define builtins with a type, name and 1-10 different
modes.
(neon_builtin_data): New array. Define information about builtins
for use during initialization/expansion.
(arm_init_neon_builtins): New function.
(arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is
true.
(neon_builtin_compare): New function.
(locate_neon_builtin_icode): New function. Find an insn code for a
builtin given a function code for that builtin. Also return type of
builtin (NEON_BINOP, NEON_UNOP etc.).
(builtin_arg): New enumeration. Types of arguments for builtins.
(arm_expand_neon_args): New function. Expand a generic NEON builtin.
Takes a variable argument list of builtin_arg types, terminated by
NEON_ARG_STOP.
(arm_expand_neon_builtin): New function. Expand a NEON builtin.
(neon_reinterpret): New function. Expand NEON reinterpret intrinsic.
(neon_emit_pair_result_insn): New function. Support returning pairs
of vectors via a pointer.
(neon_disambiguate_copy): New function. Set up operands for a
multi-word copy such that registers do not get clobbered.
(arm_expand_builtin): Call arm_expand_neon_builtin if fcode >=
ARM_BUILTIN_NEON_BASE.
(arm_file_start): Set float-abi attribute for NEON.
(arm_vector_mode_supported_p): Enable NEON vector modes.
(arm_mangle_map_entry): New.
(arm_mangle_map): New.
(arm_mangle_vector_type): New.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__
when appropriate.
(TARGET_NEON): New macro. Target supports NEON.
(fputype): Add FPUTYPE_NEON.
(UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used
for vectorization based on command-line arg.
(NEON_REGNO_OK_FOR_NREGS): Define.
(VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE)
(VALID_NEON_STRUCT_MODE): Define.
(PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation.
(arm_builtins): Add ARM_BUILTIN_NEON_BASE.
* config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec.
(consttable_16): Add pattern for outputting 16-byte minipool
entries.
(movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in
vec-common.md).
(vec-common.md, neon.md): Include md files.
* config/arm/arm.opt (mvectorize-with-neon-quad): Add option.
* config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define.
(memory_constraint "Ut", "Un", "Us"): Define.
* config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros.
(MMX_char): New mode attribute.
(addv8qi3, addv4hi3, addv2si3): Remove. Replace with...
(*add<mode>3_iwmmxt): New insn pattern.
(subv8qi3, subv4hi3, subv2si3): Remove. Replace with...
(*sub<mode>3_iwmmxt): New insn pattern.
(mulv4hi3): Rename to...
(*mulv4hi3_iwmmxt): This.
(smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3)
(umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3)
(uminv4hi3, uminv2si3): Remove. Replace with...
(*smax<mode>3_iwmmxt, *umax<mode>3_iwmmxt, *smin<mode>3_iwmmxt)
(*umin<mode>3_iwmmxt): These.
(ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with...
(ashr<mode>3_iwmmxt): This new pattern.
(lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with...
(lshr<mode>3_iwmmxt): This new pattern.
(ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with...
(ashl<mode>3_iwmmxt): This new pattern.
* config/arm/neon-docgen.ml: New file. Generate documentation for
intrinsics.
* config/arm/neon-gen.ml: New file. Generate arm_neon.h header.
* config/arm/arm_neon.h: New (autogenerated).
* config/arm/neon-testgen.ml: New file. Generate NEON tests
automatically.
* config/arm/neon.md: New file. Define NEON instructions.
* config/arm/neon.ml: New file. Abstract description of NEON
instructions, used to generate arm_neon.h header, documentation and tests.
* config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md.
* vec-common.md: New file. Shared parts for iWMMXt and NEON vector
support.
* doc/extend.texi (ARM Built-in Functions): Rename and remove
extraneous comma.
(ARM NEON Intrinsics): New subsection.
* doc/arm-neon-intrinsics.texi: New (autogenerated).
gcc/testsuite/
* gcc.dg/vect/vect.exp: Check is-effective-target arm_neon_hw.
* gcc.dg/vect/tree-vect.h: Check for NEON SIMD support.
* lib/gcc-dg.exp (cleanup-saved-temps): Fix comment.
* lib/target-supports.exp (check_effective_target_arm_neon_ok)
(check_effective_target_arm_neon_hw): New.
* gcc.target/arm/neon/neon.exp: New file.
* gcc.target/arm/neon/polytypes.c: New file.
* gcc.target/arm/neon/v*.c (1870 files): New (autogenerated).
Co-Authored-By: Joseph Myers <joseph@codesourcery.com>
Co-Authored-By: Mark Shinwell <shinwell@codesourcery.com>
Co-Authored-By: Paul Brook <paul@codesourcery.com>
From-SVN: r126911
2007-07-13 Sa Liu <saliu@de.ibm.com>
* config.gcc: Add options for arch and tune on SPU.
* config/spu/predicates.md: Add constant operands 0 and 1.
* config/spu/spu-builtins.def: Add builtins for double precision
floating point comparison: si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt,
si_dftsv, spu_cmpeq_13, spu_cmpabseq_1, spu_cmpgt_13, spu_cmpabsgt_1,
spu_testsv.
* config/spu/spu-c.c: Define __SPU_EDP__ when builtins invoked with
a CELLEDP target.
* config/spu/spu-protos.h: Add new function prototypes.
* config/spu/spu.c (spu_override_options): Check options -march and
-mtune.
(spu_comp_icode): Add comparison code for DFmode and vector mode.
(spu_emit_branch_or_set): Use the new code for DFmode and vector
mode comparison.
(spu_const_from_int): New. Create a vector constant from 4 ints.
(get_vec_cmp_insn): New. Get insn index of vector compare instruction.
(spu_emit_vector_compare): New. Emit vector compare.
(spu_emit_vector_cond_expr): New. Emit vector conditional expression.
* config/spu/spu.h: Add options -march and -mtune. Define processor
types PROCESSOR_CELL and PROCESSOR_CELLEDP. Define macro
CANONICALIZE_COMPARISON.
* config/spu/spu.md: Add new insns for double precision compare
and double precision vector compare. Add vcond and smax/smin patterns
to enable DFmode vector conditional expression.
* config/spu/spu.opt: Add options -march and -mtune.
* config/spu/spu_internals.h: Add builtins for CELLEDP target:
si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt, si_dftsv. Add builtin for
both CELL and CELLEDP targets: spu_testsv.
* config/spu/spu_intrinsics.h: Add flag mnemonics for test special
values.
testsuite/
* gcc.dg/vect/fast-math-vect-reduc-7.c: Switch on test
for V2DFmode vector conditional expression.
* gcc.target/spu/dfcmeq.c: New. Test combination of abs
and dfceq patterns.
* gcc.target/spu/dfcmgt.c: New. Test combination of abs
and dfcgt patterns.
* gcc.target/spu/intrinsics-2.c: New. Test intrinsics for
V2DFmode comparison and test special values.
* lib/target-supports.exp: Switch on test for V2DFmode
vector conditional expression.
From-SVN: r126626
* config.gcc (mipsisa32-*-elf*, mipsisa32el-*-elf*)
(mipsisa32r2-*-elf*, mipsisa32r2el-*-elf*)
(mipsisa64-*-elf*, mipsisa64el-*-elf*): Combine top-level
stanzas. Use the first part of the triplet to set MIPS_ISA_DEFAULT.
Remove redundant setting of MASK_FLOAT64 and MASK_64BIT for the
64-bit targets. Add support for *-elfoabi*.
* config/mips/t-isa3264 (MULTILIB_OPTIONS, MULTILIB_DIRNAMES): Use
different settings if $(tm_defines) does not select the EABI.
(MULTILIB_EXCLUSIONS): Define in those circumstances.
* config/mips/mips.h (MIPS_ISA_LEVEL_OPTION_SPEC): New macro.
(MIPS_ARCH_OPTION_SPEC): Likewise.
(MIPS_ISA_LEVEL_SPEC): Likewise.
(OPTION_DEFAULT_SPECS): Use MIPS_ARCH_OPTION_SPEC.
* config/mips/elfoabi.h: New file.
From-SVN: r126195
2007-06-15 Eric Christopher <echristo@apple.com>
* config.gcc (i?86-*-darwin*): Add t-crtfm and t-crtpc.
(x86_64-*-darwin*): Ditto.
* config/i386/darwin.h (CRTEND_SPEC): New. Add support
for above.
From-SVN: r125754
gcc/
* config.gcc (arm-wrs-vxworks): Remove dbxelf.h from tm_file.
Add vx-common.h. Include vxworks.h between vx-common.h and
arm/vxworks.h.
* config/vx-common.h (DWARF2_UNWIND_INFO): Undefine before
redefining.
* config/vxworks.h (TARGET_ASM_CONSTRUCTOR): Likewise.
(TARGET_ASM_DESTRUCTOR): Likewise.
* config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Check arm_arch_xscale
instead of arm_is_xscale. Use VXWORKS_OS_CPP_BUILTINS.
(OVERRIDE_OPTIONS, SUBTARGET_CPP_SPEC): Define.
(CC1_SPEC): Add -tstrongarm. Line up backslashes.
(VXWORKS_ENDIAN_SPEC): Define.
(ASM_SPEC): Add VXWORKS_ENDIAN_SPEC.
(LIB_SPEC, STARTFILE_SPEC, ENDFILE_SPEC): Redefine to their
VXWORKS_* equivalents.
(LINK_SPEC): Likewise, but add VXWORKS_ENDIAN_SPEC.
(ASM_FILE_START): Delete.
(TARGET_VERSION): Reformat.
(FPUTYPE_DEFAULT, FUNCTION_PROFILER): Define.
(DEFAULT_STRUCTURE_SIZE_BOUNDARY): Define.
* config/arm/t-vxworks (LIB1ASMSRC, LIB1ASMFUNCS): Define.
(FPBIT, DPBIT): Define.
(fp-bit.c, dp-bit.c): New rules.
(MULTILIB_OPTIONS): Add strongarm, -mrtp and -mrtp/-fPIC multilibs.
(MULTILIB_MATCHES, MULTILIB_EXCEPTIONS): Define.
* config/arm/arm-protos.h (arm_emit_call_insn): Declare.
* config/arm/arm.h: Include vxworks-dummy.h.
* config/arm/arm.c (arm_elf_asm_constructor, arm_elf_asm_destructor):
Mark with ATTRIBUTE_UNUSED.
(arm_override_options): Do not allow VxWorks RTP PIC to be used
for Thumb. Force r9 to be the PIC register for VxWorks RTPs and
make it incompatible with -msingle-pic-base.
(arm_function_ok_for_sibcall): Return false for calls that might
go through a VxWorks PIC PLT entry.
(require_pic_register): New function, split out from...
(legitimize_pic_address): ...here. Do not use GOTOFF accesses
for VxWorks RTPs.
(arm_load_pic_register): Handle the VxWorks RTP initialization
sequence. Use pic_reg as a shorthand for cfun->machine->pic_reg.
(arm_emit_call_insn): New function.
(arm_assemble_integer): Do not use GOTOFF accesses for VxWorks RTP.
* config/arm/arm.md (UNSPEC_PIC_OFFSET): New unspec number.
(pic_offset_arm): New pattern.
(call, call_value): Use arm_emit_call_insn.
(call_internal, call_value_internal): New expanders.
* config/arm/lib1funcs.asm (__PLT__): Define to empty for
VxWorks unless __PIC__.
From-SVN: r125196
2007-05-25 Eric Christopher <echristo@apple.com>
* config.gcc: Add i386/t-fprules-softfp64 and soft-fp/t-softfp
to x86-darwin configurations.
* config/i386/t-darwin: Add softfp support.
* config/i386/t-darwin64: Ditto.
* config/i386/sfp-machine.h: If mach then don't use
aliasing, emit a stub to call.
From-SVN: r125085
gcc/
* config.gcc (sparc-wrs-vxworks): New target.
* config/sparc/vxworks.h, config/sparc/t-vxworks: New files.
* config/sparc/sparc-protos.h (sparc_emit_call_insn): Declare.
* config/sparc/sparc.h: Include vxworks-dummy.h.
(PRINT_OPERAND_ADDRESS): Extend SYMBOL_REF handling to
include LABEL_REFs too.
* config/sparc/sparc.c (sparc_expand_move): Don't assume that
_GLOBAL_OFFSET_TABLE_ - label_ref is a link-time constant on
VxWorks.
(legitimize_pic_address): Handle LABEL_REFs like SYMBOL_REFs
on VxWorks.
(load_pic_register): Use gen_vxworks_load_got for VxWorks.
(sparc_emit_call_insn): New function.
(sparc_function_ok_for_sibcall): Restrict sibcalls to locally-binding
functions when generating VxWorks PIC.
* config/sparc/sparc.md (vxworks_load_got): New pattern.
(call, call_value): Use sparc_emit_call_insn instead of
emit_call_insn.
libgcc/
* config.host (sparc-wrs-vxworks): New target.
From-SVN: r124595
gcc/
* config.gcc (*-*-vxworks*): Don't add to tm_files in this stanza.
(arm-wrs-vxworks, mips-wrs-vxworks, powerpc-wrs-vxworks)
(powerpc-wrs-vxworksae): Use ${tm_file}.
(i[4567]86-wrs-vxworks, i[4567]86-wrs-vxworksae): Add svr4.h
after elfos.h. Remove i386/sysv4.h and add i386/vx-common.h.
* config/i386/vx-common.h: New file.
From-SVN: r123744
2007-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.opt ("mhard-float", "msoft-float"): Bit value
inverted and documentation adjusted.
("mhard-dfp", "msoft-dfp"): New options.
* config/s390/s390.c (s390_handle_arch_option): New architecture
switch: z9-ec.
(override_options): Sanity checks for the new options added.
* config.gcc: New architecture switch: z9-ec.
* config/s390/s390.h (processor_flags): PF_DFP added.
(TARGET_CPU_DFP, TARGET_DFP): Macro definitions added.
(TARGET_DEFAULT): Due to the s390.opt changes hard float is enabled
when the bit is NOT set so remove it from the defaults.
From-SVN: r123055
