8sa1-binutils-gdb/gas/testsuite/gas/ia64/dv-imply.d
Jim Wilson 139368c9f3 Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again.
gas/ChangeLog
	* config/tc-ia64.c (dv_sem): Add "stop".
	(specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now.
	(specify_resource, case IA64_RS_PRr): New for regs 16 to 62.
	(specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to
	match above.
	(mark_resources): Check IA64_RS_PRr.
gas/testsuite/ChangeLog
	* gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62.
	* gas/ia64/dv-waw-err.s: Likewise.
	* gas/ia64/dv-imply.d: Regenerate.
	* gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d,
	gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l,
	gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise.
include/opcode/ChangeLog
	* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
opcodes/ChangeLog
	* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
	* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
	(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
	* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
	* ia64-asmtab.c: Regnerate.
2000-09-22 19:43:50 +00:00

46 lines
2.0 KiB
Makefile

# as: -xexplicit
# objdump: -d
# name ia64 dv-mutex
.*: +file format .*
Disassembly of section \.text:
0000000000000000 <L-0xc0>:
0: 3c 20 08 00 00 21 \[MFB\] \(p01\) mov r4=2
6: 00 00 00 02 00 01 nop\.f 0x0
c: c0 00 00 40 \(p02\) br\.cond\.sptk\.few c0 <L>
10: 1d 20 1c 00 00 21 \[MFB\] mov r4=7
16: 00 00 00 02 00 00 nop\.f 0x0
1c: 00 00 20 00 rfi;;
20: 1c 20 08 00 00 21 \[MFB\] mov r4=2
26: 00 00 00 02 00 01 nop\.f 0x0
2c: a0 00 00 40 \(p02\) br\.cond\.sptk\.few c0 <L>
30: 3d 20 1c 00 00 21 \[MFB\] \(p01\) mov r4=7
36: 00 00 00 02 00 00 nop\.f 0x0
3c: 00 00 20 00 rfi;;
40: 6a 08 06 04 02 78 \[MMI\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2;;
46: 40 10 00 00 42 00 \(p01\) mov r4=2
4c: 00 00 04 00 nop\.i 0x0
50: 76 00 1c 00 00 10 \[BBB\] \(p03\) br\.cond\.sptk\.few c0 <L>
56: 00 00 00 00 10 00 nop\.b 0x0
5c: 00 00 00 20 nop\.b 0x0
60: 1d 20 1c 00 00 21 \[MFB\] mov r4=7
66: 00 00 00 02 00 00 nop\.f 0x0
6c: 00 00 20 00 rfi;;
70: 62 08 06 04 02 38 \[MII\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2
76: 30 28 18 88 e8 80 cmp\.eq\.or p3,p4=r5,r6;;
7c: 20 00 00 84 \(p01\) mov r4=2
80: 76 00 10 00 00 10 \[BBB\] \(p03\) br\.cond\.sptk\.few c0 <L>
86: 00 00 00 00 10 00 nop\.b 0x0
8c: 00 00 00 20 nop\.b 0x0
90: 1d 20 1c 00 00 21 \[MFB\] mov r4=7
96: 00 00 00 02 00 00 nop\.f 0x0
9c: 00 00 20 00 rfi;;
a0: 10 08 16 0c 42 70 \[MIB\] cmp\.ne\.and p1,p2=r5,r6
a6: 40 10 00 00 c2 01 \(p01\) mov r4=2
ac: 20 00 00 40 \(p03\) br\.cond\.sptk\.few c0 <L>
b0: 1d 20 1c 00 00 21 \[MFB\] mov r4=7
b6: 00 00 00 02 00 00 nop\.f 0x0
bc: 00 00 20 00 rfi;;