* m32r-sim.h (GET_H_SM): New macro.

(UART params): Update to msa2000.
	* devices.c (device_io_read_buffer): Update to msa2000.
	* m32r.c (m32rb_h_cr_get,m32rb_h_cr_set): Handle bbpc,bbpsw.
	(m32rb_h_psw_get,m32rb_h_psw_set): New functions.
	* arch.c,arch.h,cpu.c,cpu.h,sem-switch.c,sem.c: Regenerate.
	* m32rx.c (m32rx_h_cr_get,m32rx_h_cr_set): Handle bbpc,bbpsw.
	(m32rx_h_psw_get,m32rx_h_psw_set): New functions.
	* cpux.c,cpux.h,readx.c,semx.c: Regenerate.
PR 15938.

sim/m32r/devices.c

@@ -0,0 +1,108 @@
+/* m32r device support
+   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sim-main.h"
+
+#ifdef HAVE_DV_SOCKSER
+#include "dv-sockser.h"
+#endif
+
+/* Handling the MSPR register is done by creating a device in the core
+   mapping that winds up here.  */
+
+device m32r_devices;
+
+int
+device_io_read_buffer (device *me, void *source, int space,
+		       address_word addr, unsigned nr_bytes,
+		       SIM_CPU *cpu, sim_cia cia)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    return nr_bytes;
+
+#ifdef HAVE_DV_SOCKSER
+  if (addr == UART_INCHAR_ADDR)
+    {
+      int c = dv_sockser_read (sd);
+      if (c == -1)
+	return 0;
+      *(char *) source = c;
+      return 1;
+    }
+  if (addr == UART_STATUS_ADDR)
+    {
+      int status = dv_sockser_status (sd);
+      unsigned char *p = source;
+      p[0] = 0;
+      p[1] = (((status & DV_SOCKSER_INPUT_EMPTY)
+#ifdef UART_INPUT_READY0
+	       ? UART_INPUT_READY : 0)
+#else
+	       ? 0 : UART_INPUT_READY)
+#endif
+	      + ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0));
+      return 2;
+    }
+#endif
+
+  return nr_bytes;
+}
+
+int
+device_io_write_buffer (device *me, const void *source, int space,
+			address_word addr, unsigned nr_bytes,
+			SIM_CPU *cpu, sim_cia cia)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+#if WITH_SCACHE
+  /* MSPR support is deprecated but is kept in for upward compatibility
+     with existing overlay support.  */
+  if (addr == MSPR_ADDR)
+    {
+      if ((*(const char *) source & MSPR_PURGE) != 0)
+	scache_flush (sd);
+      return nr_bytes;
+    }
+  if (addr == MCCR_ADDR)
+    {
+      if ((*(const char *) source & MCCR_CP) != 0)
+	scache_flush (sd);
+      return nr_bytes;
+    }
+#endif
+
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    return nr_bytes;
+
+#if HAVE_DV_SOCKSER
+  if (addr == UART_OUTCHAR_ADDR)
+    {
+      int rc = dv_sockser_write (sd, *(char *) source);
+      return rc == 1;
+    }
+#endif
+
+  return nr_bytes;
+}
+
+void device_error () {}

sim/m32r/readx.c

@@ -716,10 +716,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
   EXTRACT_FMT_RTE_CODE
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (h_bsm_0) = CPU (h_bsm);
+      OPRND (h_cr_6) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 6));
-      OPRND (h_bie_0) = CPU (h_bie);
+      OPRND (h_cr_14) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 14));
-      OPRND (h_bcond_0) = CPU (h_bcond);
+      OPRND (h_bpsw_0) = CPU (h_bpsw);
-      OPRND (h_bpc_0) = CPU (h_bpc);
+      OPRND (h_bbpsw_0) = CPU (h_bbpsw);
 #undef OPRND
     }
     BREAK (read);
@@ -852,7 +852,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
   EXTRACT_FMT_TRAP_CODE
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (h_cr_0) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 0));
+      OPRND (h_cr_6) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 6));
+      OPRND (h_bpsw_0) = CPU (h_bpsw);
+      OPRND (h_psw_0) = m32rx_h_psw_get (current_cpu);
       OPRND (pc) = CPU (h_pc);
       OPRND (uimm4) = f_uimm4;
 #undef OPRND

sim/m32r/semx.c

@@ -3047,26 +3047,26 @@ SEM_FN_NAME (m32rx,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
 
 do {
   {
-    UBI opval = OPRND (h_bsm_0);
+    USI opval = ANDSI (OPRND (h_cr_6), -4);
-    CPU (h_sm) = opval;
-    TRACE_RESULT (current_cpu, "sm-0", 'x', opval);
-  }
-  {
-    UBI opval = OPRND (h_bie_0);
-    CPU (h_ie) = opval;
-    TRACE_RESULT (current_cpu, "ie-0", 'x', opval);
-  }
-  {
-    UBI opval = OPRND (h_bcond_0);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
-  }
-  {
-    USI opval = ANDSI (OPRND (h_bpc_0), -4);
     BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
     taken_p = 1;
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
+  {
+    USI opval = OPRND (h_cr_14);
+    m32rx_h_cr_set (current_cpu, ((HOSTUINT) 6), opval);
+    TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
+  }
+  {
+    UQI opval = OPRND (h_bpsw_0);
+    m32rx_h_psw_set (current_cpu, opval);
+    TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
+  }
+  {
+    UQI opval = OPRND (h_bbpsw_0);
+    CPU (h_bpsw) = opval;
+    TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
+  }
 } while (0);
 
   PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
@@ -3842,15 +3842,30 @@ SEM_FN_NAME (m32rx,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex
   EXTRACT_FMT_TRAP_CODE
 
 do {
+  {
+    USI opval = OPRND (h_cr_6);
+    m32rx_h_cr_set (current_cpu, ((HOSTUINT) 14), opval);
+    TRACE_RESULT (current_cpu, "cr-14", 'x', opval);
+  }
   {
     USI opval = ADDSI (OPRND (pc), 4);
     m32rx_h_cr_set (current_cpu, ((HOSTUINT) 6), opval);
     TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
   }
   {
-    USI opval = ANDSI (SLLSI (OPRND (h_cr_0), 8), 65408);
+    UQI opval = OPRND (h_bpsw_0);
-    m32rx_h_cr_set (current_cpu, ((HOSTUINT) 0), opval);
+    CPU (h_bbpsw) = opval;
-    TRACE_RESULT (current_cpu, "cr-0", 'x', opval);
+    TRACE_RESULT (current_cpu, "bbpsw-0", 'x', opval);
+  }
+  {
+    UQI opval = OPRND (h_psw_0);
+    CPU (h_bpsw) = opval;
+    TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
+  }
+  {
+    UQI opval = ANDQI (OPRND (h_psw_0), 128);
+    m32rx_h_psw_set (current_cpu, opval);
+    TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
   }
   {
     SI opval = m32r_trap (current_cpu, OPRND (pc), OPRND (uimm4));