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Fix compile time warnings

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This commit is contained in:
Nick Clifton 2001-09-20 15:28:25 +00:00
parent 16a419ba01
commit fc05c67f12
23 changed files with 1346 additions and 1220 deletions
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25
opcodes/ChangeLog
View File

@ -1,3 +1,28 @@
2001-09-20 Nick Clifton <nickc@cambridge.redhat.com>
* fr30-opc.c: Fix compile time warning messages.
* i370-opc.c: Fix compile time warning messages.
* i960-dis.c: Fix compile time warning messages.
* m32r-asm.c: Fix compile time warning messages.
* m32r-desc.c: Fix compile time warning messages.
* m32r-dis.c: Fix compile time warning messages.
* m32r-ibld.c: Fix compile time warning messages.
* m32r-opc.c: Fix compile time warning messages.
* m32r-opinst.c: Fix compile time warning messages.
* ns32k-dis.c: Fix compile time warning messages.
* openrisc-asm.c: Fix compile time warning messages.
* openrisc-desc.c: Fix compile time warning messages.
* openrisc-dis.c: Fix compile time warning messages.
* openrisc-ibld.c: Fix compile time warning messages.
* openrisc-opc.c: Fix compile time warning messages.
* pdp11-dis.c: Fix compile time warning messages.
* tic54x-dis.c: Fix compile time warning messages.
* v850-opc.c: Fix compile time warning messages.
* vax-dis.c: Fix compile time warning messages.
* w65-opc.h: Fix compile time warning messages.
* z8k-opc.h: Fix compile time warning messages.
* z8kgen.c: Fix compile time warning messages.
2001-09-19 Nick Clifton <nickc@cambridge.redhat.com> 2001-09-19 Nick Clifton <nickc@cambridge.redhat.com>
* arm-dis.c: Fix compile time warning messages. * arm-dis.c: Fix compile time warning messages.

13
opcodes/fr30-opc.c
View File

@ -33,10 +33,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* The hash functions are recorded here to help keep assembler code out of /* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */ the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *)); static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Instruction formats. */ /* Instruction formats. */
@ -1284,7 +1285,7 @@ static const CGEN_OPCODE fr30_cgen_macro_insn_opcode_table[] =
static int static int
asm_hash_insn_p (insn) asm_hash_insn_p (insn)
const CGEN_INSN *insn; const CGEN_INSN *insn ATTRIBUTE_UNUSED;
{ {
return CGEN_ASM_HASH_P (insn); return CGEN_ASM_HASH_P (insn);
} }
@ -1335,7 +1336,7 @@ asm_hash_insn (mnem)
static unsigned int static unsigned int
dis_hash_insn (buf, value) dis_hash_insn (buf, value)
const char * buf; const char * buf;
CGEN_INSN_INT value; CGEN_INSN_INT value ATTRIBUTE_UNUSED;
{ {
return CGEN_DIS_HASH (buf, value); return CGEN_DIS_HASH (buf, value);
} }

798
opcodes/i370-opc.c
View File

@ -1,5 +1,5 @@
/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list /* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list
Copyright 1994, 1999, 2000 Free Software Foundation, Inc. Copyright 1994, 1999, 2000, 2001 Free Software Foundation, Inc.
PowerPC version written by Ian Lance Taylor, Cygnus Support PowerPC version written by Ian Lance Taylor, Cygnus Support
Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999 Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999
@ -199,7 +199,7 @@ const struct i370_operand i370_operands[] =
#define S_D2_MASK (0xfff) #define S_D2_MASK (0xfff)
{ 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" }, { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" },
/* The L length field in an SS form instruction. */ /* The L length field in an SS form instruction. */
#define SS_L (S_D2 + 1) #define SS_L (S_D2 + 1)
#define SS_L_MASK (0xffff<<16) #define SS_L_MASK (0xffff<<16)
{ 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" }, { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" },
@ -234,7 +234,7 @@ static i370_insn_t
insert_ss_b2 (insn, value, errmsg) insert_ss_b2 (insn, value, errmsg)
i370_insn_t insn; i370_insn_t insn;
long value; long value;
const char **errmsg; const char **errmsg ATTRIBUTE_UNUSED;
{ {
insn.i[1] |= (value & 0xf) << 28; insn.i[1] |= (value & 0xf) << 28;
return insn; return insn;
@ -244,7 +244,7 @@ static i370_insn_t
insert_ss_d2 (insn, value, errmsg) insert_ss_d2 (insn, value, errmsg)
i370_insn_t insn; i370_insn_t insn;
long value; long value;
const char **errmsg; const char **errmsg ATTRIBUTE_UNUSED;
{ {
insn.i[1] |= (value & 0xfff) << 16; insn.i[1] |= (value & 0xfff) << 16;
return insn; return insn;
@ -254,7 +254,7 @@ static i370_insn_t
insert_rxf_r3 (insn, value, errmsg) insert_rxf_r3 (insn, value, errmsg)
i370_insn_t insn; i370_insn_t insn;
long value; long value;
const char **errmsg; const char **errmsg ATTRIBUTE_UNUSED;
{ {
insn.i[1] |= (value & 0xf) << 28; insn.i[1] |= (value & 0xf) << 28;
return insn; return insn;
@ -263,7 +263,7 @@ insert_rxf_r3 (insn, value, errmsg)
static long static long
extract_ss_b2 (insn, invalid) extract_ss_b2 (insn, invalid)
i370_insn_t insn; i370_insn_t insn;
int *invalid; int *invalid ATTRIBUTE_UNUSED;
{ {
return (insn.i[1] >>28) & 0xf; return (insn.i[1] >>28) & 0xf;
} }
@ -271,7 +271,7 @@ extract_ss_b2 (insn, invalid)
static long static long
extract_ss_d2 (insn, invalid) extract_ss_d2 (insn, invalid)
i370_insn_t insn; i370_insn_t insn;
int *invalid; int *invalid ATTRIBUTE_UNUSED;
{ {
return (insn.i[1] >>16) & 0xfff; return (insn.i[1] >>16) & 0xfff;
} }
@ -279,7 +279,7 @@ extract_ss_d2 (insn, invalid)
static long static long
extract_rxf_r3 (insn, invalid) extract_rxf_r3 (insn, invalid)
i370_insn_t insn; i370_insn_t insn;
int *invalid; int *invalid ATTRIBUTE_UNUSED;
{ {
return (insn.i[1] >>28) & 0xf; return (insn.i[1] >>28) & 0xf;
} }
@ -341,7 +341,7 @@ extract_rxf_r3 (insn, invalid)
#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0) #define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)
/* An RX form instruction. */ /* An RX form instruction. */
#define RX(op, r1, x2, b2, d2) \ #define RX(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(x2)) & 0xf) << 16) | \ ((((unsigned short)(x2)) & 0xf) << 16) | \
@ -350,7 +350,7 @@ extract_rxf_r3 (insn, invalid)
#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0) #define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)
/* An RXE form instruction high word. */ /* An RXE form instruction high word. */
#define RXEH(op, r1, x2, b2, d2) \ #define RXEH(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(x2)) & 0xf) << 16) | \ ((((unsigned short)(x2)) & 0xf) << 16) | \
@ -359,13 +359,13 @@ extract_rxf_r3 (insn, invalid)
#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0) #define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)
/* An RXE form instruction low word. */ /* An RXE form instruction low word. */
#define RXEL(op) \ #define RXEL(op) \
((((unsigned short)(op)) & 0xff) << 16 ) ((((unsigned short)(op)) & 0xff) << 16 )
#define RXEL_MASK RXEL (0xff) #define RXEL_MASK RXEL (0xff)
/* An RXF form instruction high word. */ /* An RXF form instruction high word. */
#define RXFH(op, r1, x2, b2, d2) \ #define RXFH(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(x2)) & 0xf) << 16) | \ ((((unsigned short)(x2)) & 0xf) << 16) | \
@ -374,14 +374,14 @@ extract_rxf_r3 (insn, invalid)
#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0) #define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)
/* An RXF form instruction low word. */ /* An RXF form instruction low word. */
#define RXFL(op, r3) \ #define RXFL(op, r3) \
(((((unsigned short)(r3)) & 0xf) << 28 ) | \ (((((unsigned short)(r3)) & 0xf) << 28 ) | \
((((unsigned short)(op)) & 0xff) << 16 )) ((((unsigned short)(op)) & 0xff) << 16 ))
#define RXFL_MASK RXFL (0xff, 0) #define RXFL_MASK RXFL (0xff, 0)
/* An RS form instruction. */ /* An RS form instruction. */
#define RS(op, r1, b3, b2, d2) \ #define RS(op, r1, b3, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(b3)) & 0xf) << 16) | \ ((((unsigned short)(b3)) & 0xf) << 16) | \
@ -390,7 +390,7 @@ extract_rxf_r3 (insn, invalid)
#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0) #define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)
/* An RSI form instruction. */ /* An RSI form instruction. */
#define RSI(op, r1, r3, i2) \ #define RSI(op, r1, r3, i2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(r3)) & 0xf) << 16) | \ ((((unsigned short)(r3)) & 0xf) << 16) | \
@ -398,14 +398,14 @@ extract_rxf_r3 (insn, invalid)
#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0) #define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)
/* An RI form instruction. */ /* An RI form instruction. */
#define RI(op, r1, i2) \ #define RI(op, r1, i2) \
(ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ (ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(i2)) & 0xffff))) ((((unsigned short)(i2)) & 0xffff)))
#define RI_MASK RI (0xfff, 0x0, 0x0) #define RI_MASK RI (0xfff, 0x0, 0x0)
/* An SI form instruction. */ /* An SI form instruction. */
#define SI(op, i2, b1, d1) \ #define SI(op, i2, b1, d1) \
(XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) | \ (XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) | \
((((unsigned short)(b1)) & 0xf) << 12) | \ ((((unsigned short)(b1)) & 0xf) << 12) | \
@ -413,32 +413,32 @@ extract_rxf_r3 (insn, invalid)
#define SI_MASK SI (0xff, 0x0, 0x0, 0x0) #define SI_MASK SI (0xff, 0x0, 0x0, 0x0)
/* An S form instruction. */ /* An S form instruction. */
#define S(op, b2, d2) \ #define S(op, b2, d2) \
(SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) | \ (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) | \
((((unsigned short)(d2)) & 0xfff))) ((((unsigned short)(d2)) & 0xfff)))
#define S_MASK S (0xffff, 0x0, 0x0) #define S_MASK S (0xffff, 0x0, 0x0)
/* An SS form instruction high word. */ /* An SS form instruction high word. */
#define SSH(op, l, b1, d1) \ #define SSH(op, l, b1, d1) \
(XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) | \ (XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) | \
((((unsigned short)(b1)) & 0xf) << 12) | \ ((((unsigned short)(b1)) & 0xf) << 12) | \
((((unsigned short)(d1)) & 0xfff))) ((((unsigned short)(d1)) & 0xfff)))
/* An SS form instruction low word. */ /* An SS form instruction low word. */
#define SSL(b2, d2) \ #define SSL(b2, d2) \
( ((((unsigned short)(b1)) & 0xf) << 28) | \ ( ((((unsigned short)(b1)) & 0xf) << 28) | \
((((unsigned short)(d1)) & 0xfff) << 16 )) ((((unsigned short)(d1)) & 0xfff) << 16 ))
#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0) #define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)
/* An SSE form instruction high word. */ /* An SSE form instruction high word. */
#define SSEH(op, b1, d1) \ #define SSEH(op, b1, d1) \
(SOPS(op) | ((((unsigned short)(b1)) & 0xf) << 12) | \ (SOPS(op) | ((((unsigned short)(b1)) & 0xf) << 12) | \
((((unsigned short)(d1)) & 0xfff))) ((((unsigned short)(d1)) & 0xfff)))
/* An SSE form instruction low word. */ /* An SSE form instruction low word. */
#define SSEL(b2, d2) \ #define SSEL(b2, d2) \
( ((((unsigned short)(b1)) & 0xf) << 28) | \ ( ((((unsigned short)(b1)) & 0xf) << 28) | \
((((unsigned short)(d1)) & 0xfff) << 16 )) ((((unsigned short)(d1)) & 0xfff) << 16 ))
@ -495,414 +495,414 @@ extract_rxf_r3 (insn, invalid)
const struct i370_opcode i370_opcodes[] = { const struct i370_opcode i370_opcodes[] = {
/* E form instructions */ /* E form instructions */
{ "pr", 2, {E(0x0101), 0}, {E_MASK, 0}, IESA, {0} }, { "pr", 2, {{E(0x0101), 0}}, {{E_MASK, 0}}, IESA, {0} },
{ "trap2", 2, {E(0x01FF), 0}, {E_MASK, 0}, ITR, {0} }, { "trap2", 2, {{E(0x01FF), 0}}, {{E_MASK, 0}}, ITR, {0} },
{ "upt", 2, {E(0x0102), 0}, {E_MASK, 0}, IXA, {0} }, { "upt", 2, {{E(0x0102), 0}}, {{E_MASK, 0}}, IXA, {0} },
/* RR form instructions */ /* RR form instructions */
{ "ar", 2, {RR(0x1a,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "ar", 2, {{RR(0x1a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "adr", 2, {RR(0x2a,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "adr", 2, {{RR(0x2a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "aer", 2, {RR(0x3a,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "aer", 2, {{RR(0x3a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "alr", 2, {RR(0x1e,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "alr", 2, {{RR(0x1e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "aur", 2, {RR(0x2e,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "aur", 2, {{RR(0x2e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "awr", 2, {RR(0x3e,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "awr", 2, {{RR(0x3e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "axr", 2, {RR(0x36,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "axr", 2, {{RR(0x36,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "balr", 2, {RR(0x05,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "balr", 2, {{RR(0x05,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "basr", 2, {RR(0x0d,0,0), 0}, {RR_MASK, 0}, IXA, {RR_R1, RR_R2} }, { "basr", 2, {{RR(0x0d,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
{ "bassm", 2, {RR(0x0c,0,0), 0}, {RR_MASK, 0}, IXA, {RR_R1, RR_R2} }, { "bassm", 2, {{RR(0x0c,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
{ "bsm", 2, {RR(0x0b,0,0), 0}, {RR_MASK, 0}, IXA, {RR_R1, RR_R2} }, { "bsm", 2, {{RR(0x0b,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
{ "bcr", 2, {RR(0x07,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "bcr", 2, {{RR(0x07,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "bctr", 2, {RR(0x06,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "bctr", 2, {{RR(0x06,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "cdr", 2, {RR(0x29,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "cdr", 2, {{RR(0x29,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "cer", 2, {RR(0x39,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "cer", 2, {{RR(0x39,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "clr", 2, {RR(0x15,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "clr", 2, {{RR(0x15,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "clcl", 2, {RR(0x0f,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "clcl", 2, {{RR(0x0f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "cr", 2, {RR(0x19,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "cr", 2, {{RR(0x19,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ddr", 2, {RR(0x2d,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "ddr", 2, {{RR(0x2d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "der", 2, {RR(0x3d,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "der", 2, {{RR(0x3d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "dr", 2, {RR(0x1d,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "dr", 2, {{RR(0x1d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "hdr", 2, {RR(0x24,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "hdr", 2, {{RR(0x24,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "her", 2, {RR(0x34,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "her", 2, {{RR(0x34,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lcdr", 2, {RR(0x23,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lcdr", 2, {{RR(0x23,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lcer", 2, {RR(0x33,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lcer", 2, {{RR(0x33,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lcr", 2, {RR(0x13,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lcr", 2, {{RR(0x13,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ldr", 2, {RR(0x28,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "ldr", 2, {{RR(0x28,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ler", 2, {RR(0x38,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "ler", 2, {{RR(0x38,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lndr", 2, {RR(0x21,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lndr", 2, {{RR(0x21,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lner", 2, {RR(0x31,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lner", 2, {{RR(0x31,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lnr", 2, {RR(0x11,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lnr", 2, {{RR(0x11,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lpdr", 2, {RR(0x20,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lpdr", 2, {{RR(0x20,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lper", 2, {RR(0x30,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lper", 2, {{RR(0x30,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lpr", 2, {RR(0x10,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lpr", 2, {{RR(0x10,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lr", 2, {RR(0x18,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lr", 2, {{RR(0x18,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lrdr", 2, {RR(0x25,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lrdr", 2, {{RR(0x25,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lrer", 2, {RR(0x35,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lrer", 2, {{RR(0x35,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ltdr", 2, {RR(0x22,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "ltdr", 2, {{RR(0x22,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lter", 2, {RR(0x32,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "lter", 2, {{RR(0x32,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ltr", 2, {RR(0x12,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "ltr", 2, {{RR(0x12,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mdr", 2, {RR(0x2c,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "mdr", 2, {{RR(0x2c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mer", 2, {RR(0x3c,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "mer", 2, {{RR(0x3c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mr", 2, {RR(0x1c,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "mr", 2, {{RR(0x1c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mvcl", 2, {RR(0x0e,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "mvcl", 2, {{RR(0x0e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mxdr", 2, {RR(0x27,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "mxdr", 2, {{RR(0x27,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mxr", 2, {RR(0x26,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "mxr", 2, {{RR(0x26,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "nr", 2, {RR(0x14,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "nr", 2, {{RR(0x14,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "or", 2, {RR(0x16,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "or", 2, {{RR(0x16,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "sdr", 2, {RR(0x2b,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "sdr", 2, {{RR(0x2b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ser", 2, {RR(0x3b,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "ser", 2, {{RR(0x3b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "slr", 2, {RR(0x1f,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "slr", 2, {{RR(0x1f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "spm", 2, {RR(0x04,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1} }, { "spm", 2, {{RR(0x04,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1} },
{ "sr", 2, {RR(0x1b,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "sr", 2, {{RR(0x1b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "sur", 2, {RR(0x3f,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "sur", 2, {{RR(0x3f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "swr", 2, {RR(0x2f,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "swr", 2, {{RR(0x2f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "sxr", 2, {RR(0x37,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "sxr", 2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "xr", 2, {RR(0x17,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} }, { "xr", 2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
/* unusual RR formats */ /* unusual RR formats */
{ "svc", 2, {SVC(0x0a,0), 0}, {SVC_MASK, 0}, I370, {RR_I} }, { "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} },
/* RRE form instructions */ /* RRE form instructions */
{ "adbr", 4, {RRE(0xb31a,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "adbr", 4, {{RRE(0xb31a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "aebr", 4, {RRE(0xb30a,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "aebr", 4, {{RRE(0xb30a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "axbr", 4, {RRE(0xb34a,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "axbr", 4, {{RRE(0xb34a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "bakr", 4, {RRE(0xb240,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "bakr", 4, {{RRE(0xb240,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "bsa", 4, {RRE(0xb25a,0,0), 0}, {RRE_MASK, 0}, IBS, {RRE_R1, RRE_R2} }, { "bsa", 4, {{RRE(0xb25a,0,0), 0}}, {{RRE_MASK, 0}}, IBS, {RRE_R1, RRE_R2} },
{ "bsg", 4, {RRE(0xb258,0,0), 0}, {RRE_MASK, 0}, ISG, {RRE_R1, RRE_R2} }, { "bsg", 4, {{RRE(0xb258,0,0), 0}}, {{RRE_MASK, 0}}, ISG, {RRE_R1, RRE_R2} },
{ "cdbr", 4, {RRE(0xb319,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "cdbr", 4, {{RRE(0xb319,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cdfbr", 4, {RRE(0xb395,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "cdfbr", 4, {{RRE(0xb395,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cdfr", 4, {RRE(0xb3b5,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "cdfr", 4, {{RRE(0xb3b5,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "cebr", 4, {RRE(0xb309,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "cebr", 4, {{RRE(0xb309,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cefbr", 4, {RRE(0xb394,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "cefbr", 4, {{RRE(0xb394,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cefr", 4, {RRE(0xb3b4,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "cefr", 4, {{RRE(0xb3b4,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "cksm", 4, {RRE(0xb241,0,0), 0}, {RRE_MASK, 0}, ICK, {RRE_R1, RRE_R2} }, { "cksm", 4, {{RRE(0xb241,0,0), 0}}, {{RRE_MASK, 0}}, ICK, {RRE_R1, RRE_R2} },
{ "clst", 4, {RRE(0xb25d,0,0), 0}, {RRE_MASK, 0}, ISR, {RRE_R1, RRE_R2} }, { "clst", 4, {{RRE(0xb25d,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
{ "cpya", 4, {RRE(0xb24d,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "cpya", 4, {{RRE(0xb24d,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "cuse", 4, {RRE(0xb257,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "cuse", 4, {{RRE(0xb257,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "cxbr", 4, {RRE(0xb349,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "cxbr", 4, {{RRE(0xb349,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cxfbr", 4, {RRE(0xb396,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "cxfbr", 4, {{RRE(0xb396,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cxfr", 4, {RRE(0xb3b6,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "cxfr", 4, {{RRE(0xb3b6,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "cxr", 4, {RRE(0xb369,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "cxr", 4, {{RRE(0xb369,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "ddbr", 4, {RRE(0xb31d,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "ddbr", 4, {{RRE(0xb31d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "debr", 4, {RRE(0xb30d,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "debr", 4, {{RRE(0xb30d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "dxbr", 4, {RRE(0xb34d,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "dxbr", 4, {{RRE(0xb34d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "dxr", 4, {RRE(0xb22d,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} }, { "dxr", 4, {{RRE(0xb22d,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "ear", 4, {RRE(0xb24f,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "ear", 4, {{RRE(0xb24f,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "efpc", 4, {RRE(0xb38c,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "efpc", 4, {{RRE(0xb38c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "epar", 4, {RRE(0xb226,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1} }, { "epar", 4, {{RRE(0xb226,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
{ "ereg", 4, {RRE(0xb249,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "ereg", 4, {{RRE(0xb249,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "esar", 4, {RRE(0xb227,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1} }, { "esar", 4, {{RRE(0xb227,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
{ "esta", 4, {RRE(0xb24a,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "esta", 4, {{RRE(0xb24a,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "fidr", 4, {RRE(0xb37f,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "fidr", 4, {{RRE(0xb37f,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "fier", 4, {RRE(0xb377,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "fier", 4, {{RRE(0xb377,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "fixr", 4, {RRE(0xb367,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "fixr", 4, {{RRE(0xb367,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "iac", 4, {RRE(0xb224,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1} }, { "iac", 4, {{RRE(0xb224,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
{ "ipm", 4, {RRE(0xb222,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1} }, { "ipm", 4, {{RRE(0xb222,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
{ "ipte", 4, {RRE(0xb221,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} }, { "ipte", 4, {{RRE(0xb221,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "iske", 4, {RRE(0xb229,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} }, { "iske", 4, {{RRE(0xb229,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "ivsk", 4, {RRE(0xb223,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} }, { "ivsk", 4, {{RRE(0xb223,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "kdbr", 4, {RRE(0xb318,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "kdbr", 4, {{RRE(0xb318,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "kebr", 4, {RRE(0xb308,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "kebr", 4, {{RRE(0xb308,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "kxbr", 4, {RRE(0xb348,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "kxbr", 4, {{RRE(0xb348,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lcdbr", 4, {RRE(0xb313,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "lcdbr", 4, {{RRE(0xb313,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lcebr", 4, {RRE(0xb303,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "lcebr", 4, {{RRE(0xb303,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lcxbr", 4, {RRE(0xb343,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "lcxbr", 4, {{RRE(0xb343,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lcxr", 4, {RRE(0xb363,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "lcxr", 4, {{RRE(0xb363,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lder", 4, {RRE(0xb324,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "lder", 4, {{RRE(0xb324,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "ldxbr", 4, {RRE(0xb345,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "ldxbr", 4, {{RRE(0xb345,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "ledbr", 4, {RRE(0xb344,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "ledbr", 4, {{RRE(0xb344,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lexbr", 4, {RRE(0xb346,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "lexbr", 4, {{RRE(0xb346,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lexr", 4, {RRE(0xb366,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "lexr", 4, {{RRE(0xb366,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lndbr", 4, {RRE(0xb311,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "lndbr", 4, {{RRE(0xb311,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lnebr", 4, {RRE(0xb301,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "lnebr", 4, {{RRE(0xb301,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lnxbr", 4, {RRE(0xb341,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "lnxbr", 4, {{RRE(0xb341,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lnxr", 4, {RRE(0xb361,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "lnxr", 4, {{RRE(0xb361,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lpdbr", 4, {RRE(0xb310,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "lpdbr", 4, {{RRE(0xb310,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lpebr", 4, {RRE(0xb300,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "lpebr", 4, {{RRE(0xb300,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lpxbr", 4, {RRE(0xb340,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "lpxbr", 4, {{RRE(0xb340,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lpxr", 4, {RRE(0xb360,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "lpxr", 4, {{RRE(0xb360,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "ltdbr", 4, {RRE(0xb312,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "ltdbr", 4, {{RRE(0xb312,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "ltebr", 4, {RRE(0xb302,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "ltebr", 4, {{RRE(0xb302,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "ltxbr", 4, {RRE(0xb342,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "ltxbr", 4, {{RRE(0xb342,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "ltxr", 4, {RRE(0xb362,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "ltxr", 4, {{RRE(0xb362,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lura", 4, {RRE(0xb24b,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "lura", 4, {{RRE(0xb24b,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "lxdr", 4, {RRE(0xb325,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "lxdr", 4, {{RRE(0xb325,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lxer", 4, {RRE(0xb326,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "lxer", 4, {{RRE(0xb326,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lxr", 4, {RRE(0xb365,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} }, { "lxr", 4, {{RRE(0xb365,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "lzdr", 4, {RRE(0xb375,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} }, { "lzdr", 4, {{RRE(0xb375,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "lzer", 4, {RRE(0xb374,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} }, { "lzer", 4, {{RRE(0xb374,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "lzxr", 4, {RRE(0xb376,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} }, { "lzxr", 4, {{RRE(0xb376,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "mdbr", 4, {RRE(0xb31c,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "mdbr", 4, {{RRE(0xb31c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "mdebr", 4, {RRE(0xb30c,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "mdebr", 4, {{RRE(0xb30c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "meebr", 4, {RRE(0xb317,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "meebr", 4, {{RRE(0xb317,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "meer", 4, {RRE(0xb337,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "meer", 4, {{RRE(0xb337,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "msr", 4, {RRE(0xb252,0,0), 0}, {RRE_MASK, 0}, IIR, {RRE_R1, RRE_R2} }, { "msr", 4, {{RRE(0xb252,0,0), 0}}, {{RRE_MASK, 0}}, IIR, {RRE_R1, RRE_R2} },
{ "msta", 4, {RRE(0xb247,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1} }, { "msta", 4, {{RRE(0xb247,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1} },
{ "mvpg", 4, {RRE(0xb254,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "mvpg", 4, {{RRE(0xb254,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "mvst", 4, {RRE(0xb255,0,0), 0}, {RRE_MASK, 0}, ISR, {RRE_R1, RRE_R2} }, { "mvst", 4, {{RRE(0xb255,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
{ "mxbr", 4, {RRE(0xb34c,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "mxbr", 4, {{RRE(0xb34c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "mxdbr", 4, {RRE(0xb307,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "mxdbr", 4, {{RRE(0xb307,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "palb", 4, {RRE(0xb248,0,0), 0}, {RRE_MASK, 0}, IESA, {0} }, { "palb", 4, {{RRE(0xb248,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {0} },
{ "prbe", 4, {RRE(0xb22a,0,0), 0}, {RRE_MASK, 0}, I370, {RRE_R1, RRE_R2} }, { "prbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, I370, {RRE_R1, RRE_R2} },
{ "pt", 4, {RRE(0xb228,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} }, { "pt", 4, {{RRE(0xb228,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "rrbe", 4, {RRE(0xb22a,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} }, { "rrbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "sar", 4, {RRE(0xb24e,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "sar", 4, {{RRE(0xb24e,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "sdbr", 4, {RRE(0xb31b,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "sdbr", 4, {{RRE(0xb31b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "sebr", 4, {RRE(0xb30b,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "sebr", 4, {{RRE(0xb30b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "servc", 4, {RRE(0xb220,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "servc", 4, {{RRE(0xb220,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "sfpc", 4, {RRE(0xb384,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "sfpc", 4, {{RRE(0xb384,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "sqdbr", 4, {RRE(0xb315,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "sqdbr", 4, {{RRE(0xb315,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "sqdr", 4, {RRE(0xb244,0,0), 0}, {RRE_MASK, 0}, IQR, {RRE_R1, RRE_R2} }, { "sqdr", 4, {{RRE(0xb244,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} },
{ "sqebr", 4, {RRE(0xb314,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "sqebr", 4, {{RRE(0xb314,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "sqer", 4, {RRE(0xb245,0,0), 0}, {RRE_MASK, 0}, IQR, {RRE_R1, RRE_R2} }, { "sqer", 4, {{RRE(0xb245,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} },
{ "sqxbr", 4, {RRE(0xb316,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "sqxbr", 4, {{RRE(0xb316,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "sqxr", 4, {RRE(0xb336,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} }, { "sqxr", 4, {{RRE(0xb336,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "srst", 4, {RRE(0xb25e,0,0), 0}, {RRE_MASK, 0}, ISR, {RRE_R1, RRE_R2} }, { "srst", 4, {{RRE(0xb25e,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
{ "ssar", 4, {RRE(0xb225,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1} }, { "ssar", 4, {{RRE(0xb225,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
{ "sske", 4, {RRE(0xb22b,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} }, { "sske", 4, {{RRE(0xb22b,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "stura", 4, {RRE(0xb246,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "stura", 4, {{RRE(0xb246,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "sxbr", 4, {RRE(0xb34b,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} }, { "sxbr", 4, {{RRE(0xb34b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "tar", 4, {RRE(0xb24c,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} }, { "tar", 4, {{RRE(0xb24c,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "tb", 4, {RRE(0xb22c,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} }, { "tb", 4, {{RRE(0xb22c,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "thdr", 4, {RRE(0xb359,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} }, { "thdr", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "thder", 4, {RRE(0xb359,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} }, { "thder", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
/* RRF form instructions */ /* RRF form instructions */
{ "cfdbr", 4, {RRF(0xb399,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "cfdbr", 4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfdr", 4, {RRF(0xb3b9,0,0,0), 0}, {RRF_MASK, 0}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, { "cfdr", 4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfebr", 4, {RRF(0xb398,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "cfebr", 4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfer", 4, {RRF(0xb3b8,0,0,0), 0}, {RRF_MASK, 0}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, { "cfer", 4, {{RRF(0xb3b8,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfxbr", 4, {RRF(0xb39a,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "cfxbr", 4, {{RRF(0xb39a,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfxr", 4, {RRF(0xb3ba,0,0,0), 0}, {RRF_MASK, 0}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, { "cfxr", 4, {{RRF(0xb3ba,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
{ "didbr", 4, {RRF(0xb35b,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "didbr", 4, {{RRF(0xb35b,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "diebr", 4, {RRF(0xb353,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "diebr", 4, {{RRF(0xb353,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "fidbr", 4, {RRF(0xb35f,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "fidbr", 4, {{RRF(0xb35f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "fiebr", 4, {RRF(0xb357,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "fiebr", 4, {{RRF(0xb357,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "fixbr", 4, {RRF(0xb347,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "fixbr", 4, {{RRF(0xb347,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "madbr", 4, {RRF(0xb31e,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "madbr", 4, {{RRF(0xb31e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "maebr", 4, {RRF(0xb30e,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "maebr", 4, {{RRF(0xb30e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "msdbr", 4, {RRF(0xb31f,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "msdbr", 4, {{RRF(0xb31f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "msebr", 4, {RRF(0xb30f,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "msebr", 4, {{RRF(0xb30f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "tbdr", 4, {RRF(0xb351,0,0,0), 0}, {RRF_MASK, 0}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, { "tbdr", 4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
{ "tbedr", 4, {RRF(0xb350,0,0,0), 0}, {RRF_MASK, 0}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, { "tbedr", 4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
/* RX form instructions */ /* RX form instructions */
{ "a", 4, {RX(0x5a,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "a", 4, {{RX(0x5a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ad", 4, {RX(0x6a,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ad", 4, {{RX(0x6a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ae", 4, {RX(0x7a,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ae", 4, {{RX(0x7a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ah", 4, {RX(0x4a,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ah", 4, {{RX(0x4a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "al", 4, {RX(0x5e,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "al", 4, {{RX(0x5e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "au", 4, {RX(0x7e,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "au", 4, {{RX(0x7e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "aw", 4, {RX(0x6e,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "aw", 4, {{RX(0x6e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "bal", 4, {RX(0x45,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "bal", 4, {{RX(0x45,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "bas", 4, {RX(0x4d,0,0,0,0), 0}, {RX_MASK, 0}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "bas", 4, {{RX(0x4d,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "bc", 4, {RX(0x47,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "bc", 4, {{RX(0x47,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "bct", 4, {RX(0x46,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "bct", 4, {{RX(0x46,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "c", 4, {RX(0x59,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "c", 4, {{RX(0x59,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cd", 4, {RX(0x69,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "cd", 4, {{RX(0x69,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ce", 4, {RX(0x79,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ce", 4, {{RX(0x79,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ch", 4, {RX(0x49,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ch", 4, {{RX(0x49,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cl", 4, {RX(0x55,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "cl", 4, {{RX(0x55,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cvb", 4, {RX(0x4f,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "cvb", 4, {{RX(0x4f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cvd", 4, {RX(0x4e,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "cvd", 4, {{RX(0x4e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "d", 4, {RX(0x5d,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "d", 4, {{RX(0x5d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "dd", 4, {RX(0x6d,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "dd", 4, {{RX(0x6d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "de", 4, {RX(0x7d,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "de", 4, {{RX(0x7d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ex", 4, {RX(0x44,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ex", 4, {{RX(0x44,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ic", 4, {RX(0x43,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ic", 4, {{RX(0x43,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "l", 4, {RX(0x58,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "l", 4, {{RX(0x58,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "la", 4, {RX(0x41,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "la", 4, {{RX(0x41,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lae", 4, {RX(0x51,0,0,0,0), 0}, {RX_MASK, 0}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "lae", 4, {{RX(0x51,0,0,0,0), 0}}, {{RX_MASK, 0}}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ld", 4, {RX(0x68,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ld", 4, {{RX(0x68,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "le", 4, {RX(0x78,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "le", 4, {{RX(0x78,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lh", 4, {RX(0x48,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "lh", 4, {{RX(0x48,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lra", 4, {RX(0xb1,0,0,0,0), 0}, {RX_MASK, 0}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "lra", 4, {{RX(0xb1,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "m", 4, {RX(0x5c,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "m", 4, {{RX(0x5c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "md", 4, {RX(0x6c,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "md", 4, {{RX(0x6c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "me", 4, {RX(0x7c,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "me", 4, {{RX(0x7c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mh", 4, {RX(0x4c,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "mh", 4, {{RX(0x4c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ms", 4, {RX(0x71,0,0,0,0), 0}, {RX_MASK, 0}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ms", 4, {{RX(0x71,0,0,0,0), 0}}, {{RX_MASK, 0}}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mxd", 4, {RX(0x67,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "mxd", 4, {{RX(0x67,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "n", 4, {RX(0x54,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "n", 4, {{RX(0x54,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "o", 4, {RX(0x56,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "o", 4, {{RX(0x56,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "s", 4, {RX(0x5b,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "s", 4, {{RX(0x5b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sd", 4, {RX(0x6b,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "sd", 4, {{RX(0x6b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "se", 4, {RX(0x7b,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "se", 4, {{RX(0x7b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sh", 4, {RX(0x4b,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "sh", 4, {{RX(0x4b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sl", 4, {RX(0x5f,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "sl", 4, {{RX(0x5f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "st", 4, {RX(0x50,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "st", 4, {{RX(0x50,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "stc", 4, {RX(0x42,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "stc", 4, {{RX(0x42,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "std", 4, {RX(0x60,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "std", 4, {{RX(0x60,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ste", 4, {RX(0x70,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ste", 4, {{RX(0x70,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sth", 4, {RX(0x40,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "sth", 4, {{RX(0x40,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "su", 4, {RX(0x7f,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "su", 4, {{RX(0x7f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sw", 4, {RX(0x6f,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "sw", 4, {{RX(0x6f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "x", 4, {RX(0x57,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "x", 4, {{RX(0x57,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
/* RXE form instructions */ /* RXE form instructions */
{ "adb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x1a)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "adb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "aeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x0a)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "aeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x19)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "cdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ceb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x09)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x09)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ddb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x1d)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ddb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "deb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x0d)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "deb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "kdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x18)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "kdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x18)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "keb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x08)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "keb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x08)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lde", 6, {RXEH(0xed,0,0,0,0), RXEL(0x24)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "lde", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x24)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ldeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x04)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ldeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x04)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lxd", 6, {RXEH(0xed,0,0,0,0), RXEL(0x25)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "lxd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x25)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lxdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x05)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "lxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x05)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lxe", 6, {RXEH(0xed,0,0,0,0), RXEL(0x26)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "lxe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x26)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lxeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x06)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "lxeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x06)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x1c)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "mdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mdeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x0c)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "mdeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mee", 6, {RXEH(0xed,0,0,0,0), RXEL(0x37)}, {RXEH_MASK, RXEL_MASK}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "mee", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x37)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "meeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x17)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "meeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x17)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mxdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x07)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "mxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x07)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sqd", 6, {RXEH(0xed,0,0,0,0), RXEL(0x35)}, {RXEH_MASK, RXEL_MASK}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "sqd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x35)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sqdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x15)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "sqdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x15)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sqe", 6, {RXEH(0xed,0,0,0,0), RXEL(0x34)}, {RXEH_MASK, RXEL_MASK}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "sqe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x34)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sqeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x14)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "sqeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x14)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x1b)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "sdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "seb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x0b)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "seb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "tcdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x11)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "tcdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x11)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "tceb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x10)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "tceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "tcxb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x12)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "tcxb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
/* RXF form instructions */ /* RXF form instructions */
{ "madb", 6, {RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, { "madb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
{ "maeb", 6, {RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, { "maeb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
{ "msdb", 6, {RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, { "msdb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
{ "mseb", 6, {RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, { "mseb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
/* RS form instructions */ /* RS form instructions */
{ "bxh", 4, {RS(0x86,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "bxh", 4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "bxle", 4, {RS(0x87,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "bxle", 4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "cds", 4, {RS(0xbb,0,0,0,0), 0}, {RS_MASK, 0}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "cds", 4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "clcle", 4, {RS(0xa9,0,0,0,0), 0}, {RS_MASK, 0}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "clcle", 4, {{RS(0xa9,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "clm", 4, {RS(0xbd,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "clm", 4, {{RS(0xbd,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "cs", 4, {RS(0xba,0,0,0,0), 0}, {RS_MASK, 0}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "cs", 4, {{RS(0xba,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "icm", 4, {RS(0xbf,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "icm", 4, {{RS(0xbf,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "lam", 4, {RS(0x9a,0,0,0,0), 0}, {RS_MASK, 0}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "lam", 4, {{RS(0x9a,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "lctl", 4, {RS(0xb7,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "lctl", 4, {{RS(0xb7,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "lm", 4, {RS(0x98,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "lm", 4, {{RS(0x98,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "mvcle", 4, {RS(0xa8,0,0,0,0), 0}, {RS_MASK, 0}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "mvcle", 4, {{RS(0xa8,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "sigp", 4, {RS(0xae,0,0,0,0), 0}, {RS_MASK, 0}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "sigp", 4, {{RS(0xae,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "stam", 4, {RS(0x9b,0,0,0,0), 0}, {RS_MASK, 0}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "stam", 4, {{RS(0x9b,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "stcm", 4, {RS(0xbe,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "stcm", 4, {{RS(0xbe,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "stctl", 4, {RS(0xb6,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "stctl", 4, {{RS(0xb6,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "stm", 4, {RS(0x90,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "stm", 4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "trace", 4, {RS(0x99,0,0,0,0), 0}, {RS_MASK, 0}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "trace", 4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
/* RS form instructions with blank R3 and optional B2 (shift left/right) */ /* RS form instructions with blank R3 and optional B2 (shift left/right) */
{ "sla", 4, {RS(0x8b,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "sla", 4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "slda", 4, {RS(0x8f,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "slda", 4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "sldl", 4, {RS(0x8d,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "sldl", 4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "sll", 4, {RS(0x89,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "sll", 4, {{RS(0x89,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "sra", 4, {RS(0x8a,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "sra", 4, {{RS(0x8a,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "srda", 4, {RS(0x8e,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "srda", 4, {{RS(0x8e,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "srdl", 4, {RS(0x8c,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "srdl", 4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "srl", 4, {RS(0x88,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "srl", 4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
/* RSI form instructions */ /* RSI form instructions */
{ "brxh", 4, {RSI(0x84,0,0,0), 0}, {RSI_MASK, 0}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, { "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
{ "brxle", 4, {RSI(0x85,0,0,0), 0}, {RSI_MASK, 0}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, { "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
/* RI form instructions */ /* RI form instructions */
{ "ahi", 4, {RI(0xa7a,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} }, { "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "bras", 4, {RI(0xa75,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} }, { "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "brc", 4, {RI(0xa74,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} }, { "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "brct", 4, {RI(0xa76,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} }, { "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "chi", 4, {RI(0xa7e,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} }, { "chi", 4, {{RI(0xa7e,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "lhi", 4, {RI(0xa78,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} }, { "lhi", 4, {{RI(0xa78,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "mhi", 4, {RI(0xa7c,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} }, { "mhi", 4, {{RI(0xa7c,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "tmh", 4, {RI(0xa70,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} }, { "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "tml", 4, {RI(0xa71,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} }, { "tml", 4, {{RI(0xa71,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
/* SI form instructions */ /* SI form instructions */
{ "cli", 4, {SI(0x95,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} }, { "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "mc", 4, {SI(0xaf,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} }, { "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "mvi", 4, {SI(0x92,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} }, { "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "ni", 4, {SI(0x94,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} }, { "ni", 4, {{SI(0x94,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "oi", 4, {SI(0x96,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} }, { "oi", 4, {{SI(0x96,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "stnsm", 4, {SI(0xac,0,0,0), 0}, {SI_MASK, 0}, IXA, {SI_D1, SI_B1, SI_I2} }, { "stnsm", 4, {{SI(0xac,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} },
{ "stosm", 4, {SI(0xad,0,0,0), 0}, {SI_MASK, 0}, IXA, {SI_D1, SI_B1, SI_I2} }, { "stosm", 4, {{SI(0xad,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} },
{ "tm", 4, {SI(0x91,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} }, { "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "xi", 4, {SI(0x97,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} }, { "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
/* S form instructions */ /* S form instructions */
{ "cfc", 4, {S(0xb21a,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "csch", 4, {S(0xb230,0,0), 0}, {S_MASK, 0}, IXA, {0} }, { "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "hsch", 4, {S(0xb231,0,0), 0}, {S_MASK, 0}, IXA, {0} }, { "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "ipk", 4, {S(0xb20b,0,0), 0}, {S_MASK, 0}, IXA, {0} }, { "ipk", 4, {{S(0xb20b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "lfpc", 4, {S(0xb29d,0,0), 0}, {S_MASK, 0}, IBF, {S_D2, S_B2} }, { "lfpc", 4, {{S(0xb29d,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
{ "lpsw", 4, {S(0x8200,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} }, { "lpsw", 4, {{S(0x8200,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "msch", 4, {S(0xb232,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "msch", 4, {{S(0xb232,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "pc", 4, {S(0xb218,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "pc", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "pcf", 4, {S(0xb218,0,0), 0}, {S_MASK, 0}, IPC, {S_D2, S_B2} }, { "pcf", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IPC, {S_D2, S_B2} },
{ "ptlb", 4, {S(0xb20d,0,0), 0}, {S_MASK, 0}, IXA, {0} }, { "ptlb", 4, {{S(0xb20d,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "rchp", 4, {S(0xb23b,0,0), 0}, {S_MASK, 0}, IXA, {0} }, { "rchp", 4, {{S(0xb23b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "rp", 4, {S(0xb277,0,0), 0}, {S_MASK, 0}, IRP, {0} }, { "rp", 4, {{S(0xb277,0,0), 0}}, {{S_MASK, 0}}, IRP, {0} },
{ "rsch", 4, {S(0xb238,0,0), 0}, {S_MASK, 0}, IXA, {0} }, { "rsch", 4, {{S(0xb238,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "sac", 4, {S(0xb219,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "sac", 4, {{S(0xb219,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "sacf", 4, {S(0xb279,0,0), 0}, {S_MASK, 0}, ISA, {S_D2, S_B2} }, { "sacf", 4, {{S(0xb279,0,0), 0}}, {{S_MASK, 0}}, ISA, {S_D2, S_B2} },
{ "sal", 4, {S(0xb237,0,0), 0}, {S_MASK, 0}, IXA, {0} }, { "sal", 4, {{S(0xb237,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "schm", 4, {S(0xb23c,0,0), 0}, {S_MASK, 0}, IXA, {0} }, { "schm", 4, {{S(0xb23c,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "sck", 4, {S(0xb204,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} }, { "sck", 4, {{S(0xb204,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "sckc", 4, {S(0xb206,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "sckc", 4, {{S(0xb206,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "spka", 4, {S(0xb20a,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "spka", 4, {{S(0xb20a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "spt", 4, {S(0xb208,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "spt", 4, {{S(0xb208,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "spx", 4, {S(0xb210,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "spx", 4, {{S(0xb210,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "srnm", 4, {S(0xb299,0,0), 0}, {S_MASK, 0}, IBF, {S_D2, S_B2} }, { "srnm", 4, {{S(0xb299,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
{ "ssch", 4, {S(0xb233,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "ssch", 4, {{S(0xb233,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "ssm", 4, {S(0x8000,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} }, { "ssm", 4, {{S(0x8000,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "stap", 4, {S(0xb212,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "stap", 4, {{S(0xb212,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stck", 4, {S(0xb205,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "stck", 4, {{S(0xb205,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stckc", 4, {S(0xb207,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} }, { "stckc", 4, {{S(0xb207,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "stcps", 4, {S(0xb23a,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "stcps", 4, {{S(0xb23a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stcrw", 4, {S(0xb239,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "stcrw", 4, {{S(0xb239,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stfpc", 4, {S(0xb29c,0,0), 0}, {S_MASK, 0}, IBF, {S_D2, S_B2} }, { "stfpc", 4, {{S(0xb29c,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
{ "stidp", 4, {S(0xb202,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} }, { "stidp", 4, {{S(0xb202,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "stpt", 4, {S(0xb209,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "stpt", 4, {{S(0xb209,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stpx", 4, {S(0xb211,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "stpx", 4, {{S(0xb211,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stsch", 4, {S(0xb234,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "stsch", 4, {{S(0xb234,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "tpi", 4, {S(0xb236,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "tpi", 4, {{S(0xb236,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "trap4", 4, {S(0xb2ff,0,0), 0}, {S_MASK, 0}, ITR, {S_D2, S_B2} }, { "trap4", 4, {{S(0xb2ff,0,0), 0}}, {{S_MASK, 0}}, ITR, {S_D2, S_B2} },
{ "ts", 4, {S(0x9300,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} }, { "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "tsch", 4, {S(0xb235,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} }, { "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
/* SS form instructions */ /* SS form instructions */
{ "ap", 6, {SSH(0xfa,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "clc", 6, {SSH(0xd5,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "clc", 6, {{SSH(0xd5,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "cp", 6, {SSH(0xf9,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "cp", 6, {{SSH(0xf9,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "dp", 6, {SSH(0xfd,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "dp", 6, {{SSH(0xfd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "ed", 6, {SSH(0xde,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "ed", 6, {{SSH(0xde,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "edmk", 6, {SSH(0xdf,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "edmk", 6, {{SSH(0xdf,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvc", 6, {SSH(0xd2,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "mvc", 6, {{SSH(0xd2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvcin", 6, {SSH(0xe8,0,0,0), 0}, {SS_MASK, 0}, IMI, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "mvcin", 6, {{SSH(0xe8,0,0,0), 0}}, {{SS_MASK, 0}}, IMI, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvck", 6, {SSH(0xd9,0,0,0), 0}, {SS_MASK, 0}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "mvck", 6, {{SSH(0xd9,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvcp", 6, {SSH(0xda,0,0,0), 0}, {SS_MASK, 0}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "mvcp", 6, {{SSH(0xda,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvcs", 6, {SSH(0xdb,0,0,0), 0}, {SS_MASK, 0}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "mvcs", 6, {{SSH(0xdb,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvn", 6, {SSH(0xd1,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "mvn", 6, {{SSH(0xd1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvo", 6, {SSH(0xf1,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "mvo", 6, {{SSH(0xf1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvz", 6, {SSH(0xd3,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "mvz", 6, {{SSH(0xd3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "nc", 6, {SSH(0xd4,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "nc", 6, {{SSH(0xd4,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "oc", 6, {SSH(0xd6,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "oc", 6, {{SSH(0xd6,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "pack", 6, {SSH(0xf2,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "pack", 6, {{SSH(0xf2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "plo", 6, {SSH(0xee,0,0,0), 0}, {SS_MASK, 0}, IPL, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "plo", 6, {{SSH(0xee,0,0,0), 0}}, {{SS_MASK, 0}}, IPL, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "sp", 6, {SSH(0xfb,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "sp", 6, {{SSH(0xfb,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "srp", 6, {SSH(0xf0,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "srp", 6, {{SSH(0xf0,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "tr", 6, {SSH(0xdc,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "tr", 6, {{SSH(0xdc,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "trt", 6, {SSH(0xdd,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "trt", 6, {{SSH(0xdd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "unpk", 6, {SSH(0xf3,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "unpk", 6, {{SSH(0xf3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "xc", 6, {SSH(0xd7,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "xc", 6, {{SSH(0xd7,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "zap", 6, {SSH(0xf8,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "zap", 6, {{SSH(0xf8,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
/* SSE form instructions */ /* SSE form instructions */
{ "lasp", 6, {SSEH(0xe500,0,0), 0}, {SSE_MASK, 0}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, { "lasp", 6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
{ "mvcdk", 6, {SSEH(0xe50f,0,0), 0}, {SSE_MASK, 0}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, { "mvcdk", 6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
{ "mvcsk", 6, {SSEH(0xe50e,0,0), 0}, {SSE_MASK, 0}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, { "mvcsk", 6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
{ "tprot", 6, {SSEH(0xe501,0,0), 0}, {SSE_MASK, 0}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, { "tprot", 6, {{SSEH(0xe501,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
/* */ /* */
}; };

1441
opcodes/i960-dis.c
View File

File diff suppressed because it is too large Load Diff

17
opcodes/m32r-asm.c
View File

@ -35,14 +35,19 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "m32r-opc.h" #include "m32r-opc.h"
#include "opintl.h" #include "opintl.h"
#include "xregex.h" #include "xregex.h"
#include "libiberty.h"
#undef min #undef min
#define min(a,b) ((a) < (b) ? (a) : (b)) #define min(a,b) ((a) < (b) ? (a) : (b))
#undef max #undef max
#define max(a,b) ((a) > (b) ? (a) : (b)) #define max(a,b) ((a) > (b) ? (a) : (b))
static const char * parse_insn_normal static const char * parse_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); static const char * parse_hash PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_slo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_ulo16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
const char * m32r_cgen_parse_operand PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
/* -- assembler routines inserted here */ /* -- assembler routines inserted here */
@ -52,10 +57,10 @@ static const char * parse_insn_normal
static const char * static const char *
parse_hash (cd, strp, opindex, valuep) parse_hash (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
const char **strp; const char **strp;
int opindex; int opindex ATTRIBUTE_UNUSED;
unsigned long *valuep; unsigned long *valuep ATTRIBUTE_UNUSED;
{ {
if (**strp == '#') if (**strp == '#')
++*strp; ++*strp;
@ -352,7 +357,7 @@ char *
m32r_cgen_build_insn_regex (insn) m32r_cgen_build_insn_regex (insn)
CGEN_INSN *insn; CGEN_INSN *insn;
{ {
CGEN_OPCODE *opc = CGEN_INSN_OPCODE (insn); CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn);
int mnem_len; int mnem_len;
char rxbuf[CGEN_MAX_RX_ELEMENTS]; char rxbuf[CGEN_MAX_RX_ELEMENTS];

7
opcodes/m32r-desc.c
View File

@ -33,6 +33,13 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h" #include "opintl.h"
#include "libiberty.h" #include "libiberty.h"
static void init_tables PARAMS ((void));
static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
/* Attributes. */ /* Attributes. */
static const CGEN_ATTR_ENTRY bool_attr[] = static const CGEN_ATTR_ENTRY bool_attr[] =

52
opcodes/m32r-dis.c
View File

@ -47,10 +47,17 @@ static void print_keyword
static void print_insn_normal static void print_insn_normal
PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
bfd_vma, int)); bfd_vma, int));
static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, static int print_insn
disassemble_info *, char *, int)); PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int));
static int default_print_insn static void print_hash
PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static int my_print_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
void m32r_cgen_print_operand
PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int));
static int read_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
CGEN_EXTRACT_INFO *, unsigned long *));
/* -- disassembler routines inserted here */ /* -- disassembler routines inserted here */
@ -68,12 +75,12 @@ do { \
static void static void
print_hash (cd, dis_info, value, attrs, pc, length) print_hash (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info; PTR dis_info;
long value; long value ATTRIBUTE_UNUSED;
unsigned int attrs; unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc; bfd_vma pc ATTRIBUTE_UNUSED;
int length; int length ATTRIBUTE_UNUSED;
{ {
disassemble_info *info = (disassemble_info *) dis_info; disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "#"); (*info->fprintf_func) (info->stream, "#");
@ -156,7 +163,7 @@ m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
int opindex; int opindex;
PTR xinfo; PTR xinfo;
CGEN_FIELDS *fields; CGEN_FIELDS *fields;
void const *attrs; void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc; bfd_vma pc;
int length; int length;
{ {
@ -264,7 +271,7 @@ m32r_cgen_init_dis (cd)
static void static void
print_normal (cd, dis_info, value, attrs, pc, length) print_normal (cd, dis_info, value, attrs, pc, length)
#ifdef CGEN_PRINT_NORMAL #ifdef CGEN_PRINT_NORMAL
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
#else #else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
#endif #endif
@ -272,8 +279,8 @@ print_normal (cd, dis_info, value, attrs, pc, length)
long value; long value;
unsigned int attrs; unsigned int attrs;
#ifdef CGEN_PRINT_NORMAL #ifdef CGEN_PRINT_NORMAL
bfd_vma pc; bfd_vma pc ATTRIBUTE_UNUSED;
int length; int length ATTRIBUTE_UNUSED;
#else #else
bfd_vma pc ATTRIBUTE_UNUSED; bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED;
@ -299,7 +306,7 @@ print_normal (cd, dis_info, value, attrs, pc, length)
static void static void
print_address (cd, dis_info, value, attrs, pc, length) print_address (cd, dis_info, value, attrs, pc, length)
#ifdef CGEN_PRINT_NORMAL #ifdef CGEN_PRINT_NORMAL
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
#else #else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
#endif #endif
@ -307,8 +314,8 @@ print_address (cd, dis_info, value, attrs, pc, length)
bfd_vma value; bfd_vma value;
unsigned int attrs; unsigned int attrs;
#ifdef CGEN_PRINT_NORMAL #ifdef CGEN_PRINT_NORMAL
bfd_vma pc; bfd_vma pc ATTRIBUTE_UNUSED;
int length; int length ATTRIBUTE_UNUSED;
#else #else
bfd_vma pc ATTRIBUTE_UNUSED; bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED;
@ -397,7 +404,7 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
Returns 0 if all is well, non-zero otherwise. */ Returns 0 if all is well, non-zero otherwise. */
static int static int
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
bfd_vma pc; bfd_vma pc;
disassemble_info *info; disassemble_info *info;
char *buf; char *buf;
@ -475,8 +482,8 @@ print_insn (cd, pc, info, buf, buflen)
/* Base size may exceed this instruction's size. Extract the /* Base size may exceed this instruction's size. Extract the
relevant part from the buffer. */ relevant part from the buffer. */
if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen && if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen
(CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) && (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG); info->endian == BFD_ENDIAN_BIG);
else else
@ -491,8 +498,8 @@ print_insn (cd, pc, info, buf, buflen)
/* Make sure the entire insn is loaded into insn_value, if it /* Make sure the entire insn is loaded into insn_value, if it
can fit. */ can fit. */
if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize && if ((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize
(CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) && ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
{ {
unsigned long full_insn_value; unsigned long full_insn_value;
int rc = read_insn (cd, pc, info, buf, int rc = read_insn (cd, pc, info, buf,
@ -530,7 +537,9 @@ print_insn (cd, pc, info, buf, buflen)
#ifndef CGEN_PRINT_INSN #ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn #define CGEN_PRINT_INSN default_print_insn
#endif
static int default_print_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
static int static int
default_print_insn (cd, pc, info) default_print_insn (cd, pc, info)
@ -561,6 +570,7 @@ default_print_insn (cd, pc, info)
return print_insn (cd, pc, info, buf, buflen); return print_insn (cd, pc, info, buf, buflen);
} }
#endif
/* Main entry point. /* Main entry point.
Print one instruction from PC on INFO->STREAM. Print one instruction from PC on INFO->STREAM.

21
opcodes/m32r-ibld.c
View File

@ -58,7 +58,18 @@ static int extract_insn_normal
CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
static void put_insn_int_value static void put_insn_int_value
PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
const char * m32r_cgen_insert_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
int m32r_cgen_extract_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
int m32r_cgen_get_int_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
bfd_vma m32r_cgen_get_vma_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
void m32r_cgen_set_int_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
void m32r_cgen_set_vma_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
/* Operand insertion. */ /* Operand insertion. */
@ -797,7 +808,7 @@ cgen_extract_fn * const m32r_cgen_extract_handlers[] =
int int
m32r_cgen_get_int_operand (cd, opindex, fields) m32r_cgen_get_int_operand (cd, opindex, fields)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex; int opindex;
const CGEN_FIELDS * fields; const CGEN_FIELDS * fields;
{ {
@ -887,7 +898,7 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
bfd_vma bfd_vma
m32r_cgen_get_vma_operand (cd, opindex, fields) m32r_cgen_get_vma_operand (cd, opindex, fields)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex; int opindex;
const CGEN_FIELDS * fields; const CGEN_FIELDS * fields;
{ {
@ -982,7 +993,7 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
void void
m32r_cgen_set_int_operand (cd, opindex, fields, value) m32r_cgen_set_int_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex; int opindex;
CGEN_FIELDS * fields; CGEN_FIELDS * fields;
int value; int value;
@ -1068,7 +1079,7 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
void void
m32r_cgen_set_vma_operand (cd, opindex, fields, value) m32r_cgen_set_vma_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex; int opindex;
CGEN_FIELDS * fields; CGEN_FIELDS * fields;
bfd_vma value; bfd_vma value;

13
opcodes/m32r-opc.c
View File

@ -33,10 +33,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* The hash functions are recorded here to help keep assembler code out of /* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */ the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *)); static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Instruction formats. */ /* Instruction formats. */
@ -1601,7 +1602,7 @@ static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
static int static int
asm_hash_insn_p (insn) asm_hash_insn_p (insn)
const CGEN_INSN *insn; const CGEN_INSN *insn ATTRIBUTE_UNUSED;
{ {
return CGEN_ASM_HASH_P (insn); return CGEN_ASM_HASH_P (insn);
} }
@ -1652,7 +1653,7 @@ asm_hash_insn (mnem)
static unsigned int static unsigned int
dis_hash_insn (buf, value) dis_hash_insn (buf, value)
const char * buf; const char * buf;
CGEN_INSN_INT value; CGEN_INSN_INT value ATTRIBUTE_UNUSED;
{ {
return CGEN_DIS_HASH (buf, value); return CGEN_DIS_HASH (buf, value);
} }

6
opcodes/m32r-opinst.c
View File

@ -36,9 +36,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#else #else
#define OP_ENT(op) M32R_OPERAND_/**/op #define OP_ENT(op) M32R_OPERAND_/**/op
#endif #endif
#define INPUT CGEN_OPINST_INPUT #define INPUT CGEN_OPINST_INPUT
#define OUTPUT CGEN_OPINST_OUTPUT #define OUTPUT CGEN_OPINST_OUTPUT
#define END CGEN_OPINST_END #define END CGEN_OPINST_END, "", 0, 0, 0, 0, 0
#define COND_REF CGEN_OPINST_COND_REF #define COND_REF CGEN_OPINST_COND_REF
static const CGEN_OPINST sfmt_empty_ops[] = { static const CGEN_OPINST sfmt_empty_ops[] = {

12
opcodes/ns32k-dis.c
View File

@ -635,20 +635,20 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
break; break;
case 'W': case 'W':
Ivalue = bit_extract (buffer, *aoffsetp, 16); Ivalue = bit_extract (buffer, *aoffsetp, 16);
flip_bytes (&Ivalue, 2); flip_bytes ((char *) & Ivalue, 2);
*aoffsetp += 16; *aoffsetp += 16;
Ivalue = sign_extend (Ivalue, 16); Ivalue = sign_extend (Ivalue, 16);
sprintf (result, "$%d", Ivalue); sprintf (result, "$%d", Ivalue);
break; break;
case 'D': case 'D':
Ivalue = bit_extract (buffer, *aoffsetp, 32); Ivalue = bit_extract (buffer, *aoffsetp, 32);
flip_bytes (&Ivalue, 4); flip_bytes ((char *) & Ivalue, 4);
*aoffsetp += 32; *aoffsetp += 32;
sprintf (result, "$%d", Ivalue); sprintf (result, "$%d", Ivalue);
break; break;
case 'F': case 'F':
bit_copy (buffer, *aoffsetp, 32, (char *) &Fvalue); bit_copy (buffer, *aoffsetp, 32, (char *) &Fvalue);
flip_bytes (&Fvalue, 4); flip_bytes ((char *) & Fvalue, 4);
*aoffsetp += 32; *aoffsetp += 32;
if (INVALID_FLOAT (&Fvalue, 4)) if (INVALID_FLOAT (&Fvalue, 4))
sprintf (result, "<<invalid float 0x%.8x>>", *(int *) &Fvalue); sprintf (result, "<<invalid float 0x%.8x>>", *(int *) &Fvalue);
@ -657,7 +657,7 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
break; break;
case 'L': case 'L':
bit_copy (buffer, *aoffsetp, 64, (char *) &Lvalue); bit_copy (buffer, *aoffsetp, 64, (char *) &Lvalue);
flip_bytes (&Lvalue, 8); flip_bytes ((char *) & Lvalue, 8);
*aoffsetp += 64; *aoffsetp += 64;
if (INVALID_FLOAT (&Lvalue, 8)) if (INVALID_FLOAT (&Lvalue, 8))
sprintf (result, "<<invalid long 0x%.8x%.8x>>", sprintf (result, "<<invalid long 0x%.8x%.8x>>",
@ -840,13 +840,13 @@ get_displacement (buffer, aoffsetp)
break; break;
case 0x80: case 0x80:
Ivalue2 = bit_extract (buffer, *aoffsetp, 16); Ivalue2 = bit_extract (buffer, *aoffsetp, 16);
flip_bytes (&Ivalue2, 2); flip_bytes ((char *) & Ivalue2, 2);
Ivalue = sign_extend (Ivalue2, 14); Ivalue = sign_extend (Ivalue2, 14);
*aoffsetp += 16; *aoffsetp += 16;
break; break;
case 0xc0: case 0xc0:
Ivalue = bit_extract (buffer, *aoffsetp, 32); Ivalue = bit_extract (buffer, *aoffsetp, 32);
flip_bytes (&Ivalue, 4); flip_bytes ((char *) & Ivalue, 4);
Ivalue = sign_extend (Ivalue, 30); Ivalue = sign_extend (Ivalue, 30);
*aoffsetp += 32; *aoffsetp += 32;
break; break;

13
opcodes/openrisc-asm.c
View File

@ -35,6 +35,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "openrisc-opc.h" #include "openrisc-opc.h"
#include "opintl.h" #include "opintl.h"
#include "xregex.h" #include "xregex.h"
#include "libiberty.h"
#undef min #undef min
#define min(a,b) ((a) < (b) ? (a) : (b)) #define min(a,b) ((a) < (b) ? (a) : (b))
@ -43,6 +44,14 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
static const char * parse_insn_normal static const char * parse_insn_normal
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
long openrisc_sign_extend_16bit
PARAMS ((long));
static const char * parse_hi16
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_lo16
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
const char * openrisc_cgen_parse_operand
PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
/* -- assembler routines inserted here */ /* -- assembler routines inserted here */
@ -181,7 +190,7 @@ openrisc_cgen_parse_operand (cd, opindex, strp, fields)
{ {
const char * errmsg = NULL; const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */ /* Used by scalar operands that still need to be parsed. */
long junk; long junk ATTRIBUTE_UNUSED;
switch (opindex) switch (opindex)
{ {
@ -276,7 +285,7 @@ char *
openrisc_cgen_build_insn_regex (insn) openrisc_cgen_build_insn_regex (insn)
CGEN_INSN *insn; CGEN_INSN *insn;
{ {
CGEN_OPCODE *opc = CGEN_INSN_OPCODE (insn); CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn);
int mnem_len; int mnem_len;
char rxbuf[CGEN_MAX_RX_ELEMENTS]; char rxbuf[CGEN_MAX_RX_ELEMENTS];

7
opcodes/openrisc-desc.c
View File

@ -34,6 +34,13 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h" #include "opintl.h"
#include "libiberty.h" #include "libiberty.h"
static void init_tables PARAMS ((void));
static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
/* Attributes. */ /* Attributes. */
static const CGEN_ATTR_ENTRY bool_attr[] = static const CGEN_ATTR_ENTRY bool_attr[] =

14
opcodes/openrisc-dis.c
View File

@ -51,6 +51,10 @@ static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
disassemble_info *, char *, int)); disassemble_info *, char *, int));
static int default_print_insn static int default_print_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
void openrisc_cgen_print_operand
PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int));
static int read_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, unsigned long *));
/* -- disassembler routines inserted here */ /* -- disassembler routines inserted here */
@ -77,7 +81,7 @@ openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
int opindex; int opindex;
PTR xinfo; PTR xinfo;
CGEN_FIELDS *fields; CGEN_FIELDS *fields;
void const *attrs; void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc; bfd_vma pc;
int length; int length;
{ {
@ -288,7 +292,7 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
Returns 0 if all is well, non-zero otherwise. */ Returns 0 if all is well, non-zero otherwise. */
static int static int
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
bfd_vma pc; bfd_vma pc;
disassemble_info *info; disassemble_info *info;
char *buf; char *buf;
@ -367,7 +371,7 @@ print_insn (cd, pc, info, buf, buflen)
/* Base size may exceed this instruction's size. Extract the /* Base size may exceed this instruction's size. Extract the
relevant part from the buffer. */ relevant part from the buffer. */
if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen && if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG); info->endian == BFD_ENDIAN_BIG);
else else
@ -382,8 +386,8 @@ print_insn (cd, pc, info, buf, buflen)
/* Make sure the entire insn is loaded into insn_value, if it /* Make sure the entire insn is loaded into insn_value, if it
can fit. */ can fit. */
if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize && if ( (unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
(CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
{ {
unsigned long full_insn_value; unsigned long full_insn_value;
int rc = read_insn (cd, pc, info, buf, int rc = read_insn (cd, pc, info, buf,

23
opcodes/openrisc-ibld.c
View File

@ -59,7 +59,18 @@ static int extract_insn_normal
CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
static void put_insn_int_value static void put_insn_int_value
PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
const char * openrisc_cgen_insert_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
int openrisc_cgen_extract_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
int openrisc_cgen_get_int_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
bfd_vma openrisc_cgen_get_vma_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
void openrisc_cgen_set_int_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
void openrisc_cgen_set_vma_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
/* Operand insertion. */ /* Operand insertion. */
@ -703,6 +714,8 @@ openrisc_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2); length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2);
if (length <= 0) break; if (length <= 0) break;
{ {
extern long openrisc_sign_extend_16bit PARAMS ((long));
FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1)))); FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1))));
} }
} }
@ -741,7 +754,7 @@ cgen_extract_fn * const openrisc_cgen_extract_handlers[] =
int int
openrisc_cgen_get_int_operand (cd, opindex, fields) openrisc_cgen_get_int_operand (cd, opindex, fields)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex; int opindex;
const CGEN_FIELDS * fields; const CGEN_FIELDS * fields;
{ {
@ -801,7 +814,7 @@ openrisc_cgen_get_int_operand (cd, opindex, fields)
bfd_vma bfd_vma
openrisc_cgen_get_vma_operand (cd, opindex, fields) openrisc_cgen_get_vma_operand (cd, opindex, fields)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex; int opindex;
const CGEN_FIELDS * fields; const CGEN_FIELDS * fields;
{ {
@ -866,7 +879,7 @@ openrisc_cgen_get_vma_operand (cd, opindex, fields)
void void
openrisc_cgen_set_int_operand (cd, opindex, fields, value) openrisc_cgen_set_int_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex; int opindex;
CGEN_FIELDS * fields; CGEN_FIELDS * fields;
int value; int value;
@ -923,7 +936,7 @@ openrisc_cgen_set_int_operand (cd, opindex, fields, value)
void void
openrisc_cgen_set_vma_operand (cd, opindex, fields, value) openrisc_cgen_set_vma_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd; CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex; int opindex;
CGEN_FIELDS * fields; CGEN_FIELDS * fields;
bfd_vma value; bfd_vma value;

13
opcodes/openrisc-opc.c
View File

@ -35,10 +35,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* The hash functions are recorded here to help keep assembler code out of /* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */ the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *)); static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Instruction formats. */ /* Instruction formats. */
@ -594,7 +595,7 @@ static const CGEN_OPCODE openrisc_cgen_macro_insn_opcode_table[] =
static int static int
asm_hash_insn_p (insn) asm_hash_insn_p (insn)
const CGEN_INSN *insn; const CGEN_INSN *insn ATTRIBUTE_UNUSED;
{ {
return CGEN_ASM_HASH_P (insn); return CGEN_ASM_HASH_P (insn);
} }
@ -645,7 +646,7 @@ asm_hash_insn (mnem)
static unsigned int static unsigned int
dis_hash_insn (buf, value) dis_hash_insn (buf, value)
const char * buf; const char * buf;
CGEN_INSN_INT value; CGEN_INSN_INT value ATTRIBUTE_UNUSED;
{ {
return CGEN_DIS_HASH (buf, value); return CGEN_DIS_HASH (buf, value);
} }

1
opcodes/pdp11-dis.c
View File

@ -15,6 +15,7 @@ You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sysdep.h"
#include "dis-asm.h" #include "dis-asm.h"
#include "opcode/pdp11.h" #include "opcode/pdp11.h"

3
opcodes/tic54x-dis.c
View File

@ -197,7 +197,8 @@ print_instruction (info, memaddr, opcode, tm_name, tm_operands, size, ext)
/* string storage for multiple operands */ /* string storage for multiple operands */
char operand[4][64] = { {0},{0},{0},{0}, }; char operand[4][64] = { {0},{0},{0},{0}, };
bfd_byte buf[2]; bfd_byte buf[2];
unsigned long opcode2, lkaddr; unsigned long opcode2 = 0;
unsigned long lkaddr = 0;
enum optype src = OP_None; enum optype src = OP_None;
enum optype dst = OP_None; enum optype dst = OP_None;
int i, shift; int i, shift;

77
opcodes/v850-opc.c
View File

@ -34,42 +34,28 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* two-word opcodes */ /* two-word opcodes */
#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
static long unsigned int insert_d9 static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **));
PARAMS ((long unsigned int, long int, const char **)); static long unsigned extract_d9 PARAMS ((long unsigned, int *));
static long unsigned int extract_d9 static long unsigned insert_d22 PARAMS ((long unsigned, long, const char **));
PARAMS ((long unsigned int, int *)); static long unsigned extract_d22 PARAMS ((long unsigned, int *));
static long unsigned int insert_d22 static long unsigned insert_d16_15 PARAMS ((long unsigned, long, const char **));
PARAMS ((long unsigned int, long int, const char **)); static long unsigned extract_d16_15 PARAMS ((long unsigned, int *));
static long unsigned int extract_d22 static long unsigned insert_d8_7 PARAMS ((long unsigned, long, const char **));
PARAMS ((long unsigned int, int *)); static long unsigned extract_d8_7 PARAMS ((long unsigned, int *));
static long unsigned int insert_d16_15 static long unsigned insert_d8_6 PARAMS ((long unsigned, long, const char **));
PARAMS ((long unsigned int, long int, const char **)); static long unsigned extract_d8_6 PARAMS ((long unsigned, int *));
static long unsigned int extract_d16_15 static long unsigned insert_d5_4 PARAMS ((long unsigned, long, const char **));
PARAMS ((long unsigned int, int *)); static long unsigned extract_d5_4 PARAMS ((long unsigned, int *));
static long unsigned int insert_d8_7 static long unsigned insert_d16_16 PARAMS ((long unsigned, long, const char **));
PARAMS ((long unsigned int, long int, const char **)); static long unsigned extract_d16_16 PARAMS ((long unsigned, int *));
static long unsigned int extract_d8_7 PARAMS ((long unsigned int, int *)); static long unsigned insert_i9 PARAMS ((long unsigned, long, const char **));
static long unsigned int insert_d8_6 static long unsigned extract_i9 PARAMS ((long unsigned, int *));
PARAMS ((long unsigned int, long int, const char **)); static long unsigned insert_u9 PARAMS ((long unsigned, long, const char **));
static long unsigned int extract_d8_6 PARAMS ((long unsigned int, int *)); static long unsigned extract_u9 PARAMS ((long unsigned, int *));
static long unsigned int insert_d5_4 static long unsigned insert_spe PARAMS ((long unsigned, long, const char **));
PARAMS ((long unsigned int, long int, const char **)); static long unsigned extract_spe PARAMS ((long unsigned, int *));
static long unsigned int extract_d5_4 PARAMS ((long unsigned int, int *)); static long unsigned insert_i5div PARAMS ((long unsigned, long, const char **));
static long unsigned int insert_d16_16 static long unsigned extract_i5div PARAMS ((long unsigned, int *));
PARAMS ((long unsigned int, long int, const char **));
static long unsigned int extract_d16_16 PARAMS ((long unsigned int, int *));
static long unsigned int insert_i9
PARAMS ((long unsigned int, long int, const char **));
static long unsigned int extract_i9 PARAMS ((long unsigned int, int *));
static long unsigned int insert_u9
PARAMS ((long unsigned int, long unsigned int, const char **));
static long unsigned int extract_u9 PARAMS ((long unsigned int, int *));
static long unsigned int insert_spe
PARAMS ((long unsigned int, long unsigned int, const char **));
static long unsigned int extract_spe PARAMS ((long unsigned int, int *));
static long unsigned int insert_i5div
PARAMS ((long unsigned int, long unsigned int, const char **));
static long unsigned int extract_i5div PARAMS ((long unsigned int, int *));
/* The functions used to insert and extract complicated operands. */ /* The functions used to insert and extract complicated operands. */
@ -322,11 +308,12 @@ extract_i9 (insn, invalid)
} }
static unsigned long static unsigned long
insert_u9 (insn, value, errmsg) insert_u9 (insn, v, errmsg)
unsigned long insn; unsigned long insn;
unsigned long value; long v;
const char ** errmsg; const char ** errmsg;
{ {
unsigned long value = (unsigned long) v;
if (value > 0x1ff) if (value > 0x1ff)
* errmsg = _(immediate_out_of_range); * errmsg = _(immediate_out_of_range);
@ -348,11 +335,13 @@ extract_u9 (insn, invalid)
} }
static unsigned long static unsigned long
insert_spe (insn, value, errmsg) insert_spe (insn, v, errmsg)
unsigned long insn; unsigned long insn;
unsigned long value; long v;
const char ** errmsg; const char ** errmsg;
{ {
unsigned long value = (unsigned long) v;
if (value != 3) if (value != 3)
* errmsg = _("invalid register for stack adjustment"); * errmsg = _("invalid register for stack adjustment");
@ -368,11 +357,13 @@ extract_spe (insn, invalid)
} }
static unsigned long static unsigned long
insert_i5div (insn, value, errmsg) insert_i5div (insn, v, errmsg)
unsigned long insn; unsigned long insn;
unsigned long value; long v;
const char ** errmsg; const char ** errmsg;
{ {
unsigned long value = (unsigned long) v;
if (value > 0x1ff) if (value > 0x1ff)
{ {
if (value & 1) if (value & 1)
@ -405,7 +396,7 @@ extract_i5div (insn, invalid)
/* Warning: code in gas/config/tc-v850.c examines the contents of this array. /* Warning: code in gas/config/tc-v850.c examines the contents of this array.
If you change any of the values here, be sure to look for side effects in If you change any of the values here, be sure to look for side effects in
that code. */ that code. */
const struct v850_operand v850_operands[] = const struct v850_operand v850_operands[] =
{ {
#define UNUSED 0 #define UNUSED 0

4
opcodes/vax-dis.c
View File

@ -112,7 +112,7 @@ print_insn_vax (memaddr, info)
disassemble_info *info; disassemble_info *info;
{ {
const struct vot *votp; const struct vot *votp;
const char *argp = NULL; const char *argp;
unsigned char *arg; unsigned char *arg;
struct private priv; struct private priv;
bfd_byte *buffer = priv.the_buffer; bfd_byte *buffer = priv.the_buffer;
@ -120,12 +120,14 @@ print_insn_vax (memaddr, info)
info->private_data = (PTR) &priv; info->private_data = (PTR) &priv;
priv.max_fetched = priv.the_buffer; priv.max_fetched = priv.the_buffer;
priv.insn_start = memaddr; priv.insn_start = memaddr;
if (setjmp (priv.bailout) != 0) if (setjmp (priv.bailout) != 0)
{ {
/* Error return. */ /* Error return. */
return -1; return -1;
} }
argp = NULL;
/* Check if the info buffer has more than one byte left since /* Check if the info buffer has more than one byte left since
the last opcode might be a single byte with no argument data. */ the last opcode might be a single byte with no argument data. */
if (info->buffer_length - (memaddr - info->buffer_vma) > 1) if (info->buffer_length - (memaddr - info->buffer_vma) > 1)

2
opcodes/w65-opc.h
View File

@ -402,7 +402,7 @@ struct opinfo optable[257]={
{0x42, O_wdm, "wdm", ADDR_IMPLIED}, {0x42, O_wdm, "wdm", ADDR_IMPLIED},
{0xEB, O_xba, "xba", ADDR_IMPLIED}, {0xEB, O_xba, "xba", ADDR_IMPLIED},
{0xFB, O_xce, "xce", ADDR_IMPLIED}, {0xFB, O_xce, "xce", ADDR_IMPLIED},
{ 0 } { 0, 0, NULL, 0 }
}; };
#endif #endif
#define DISASM()\ #define DISASM()\

2
opcodes/z8k-opc.h
View File

@ -248,7 +248,7 @@ int flags;
#endif #endif
char *name; char *name;
unsigned char opcode; unsigned char opcode;
void (*func)(); void (*func) PARAMS ((void));
unsigned int arg_info[4]; unsigned int arg_info[4];
unsigned int byte_info[10]; unsigned int byte_info[10];
int noperands; int noperands;

2
opcodes/z8kgen.c
View File

@ -1227,7 +1227,7 @@ gas ()
printf ("#endif\n"); printf ("#endif\n");
printf ("char *name;\n"); printf ("char *name;\n");
printf ("unsigned char opcode;\n"); printf ("unsigned char opcode;\n");
printf ("void (*func)();\n"); printf ("void (*func) PARAMS ((void));\n");
printf ("unsigned int arg_info[4];\n"); printf ("unsigned int arg_info[4];\n");
printf ("unsigned int byte_info[%d];\n", BYTE_INFO_LEN); printf ("unsigned int byte_info[%d];\n", BYTE_INFO_LEN);
printf ("int noperands;\n"); printf ("int noperands;\n");