2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
gas/ * config/tc-i386.c (cpu_arch): Remove cvt16. (md_show_usage): Same. * doc/c-i386.texi: Same. gas/testsuite/ * gas/i386/cvt16.d: Removed. * gas/i386/cvt16.s: Removed. * gas/i386/x86-64-cvt16.d: Removed. * gas/i386/x86-64-cvt16.s: Removed. * gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests. opcodes/ * i386-dis.c (VEX_LEN_XOP_08_A0): Removed. (VEX_LEN_XOP_08_A1): Removed. (xop_table): Remove entries for VEX_LEN_XOP_08_A0 and VEX_LEN_XOP_08_A1. (vex_len_table): Same. * i386-gen.c (CPU_CVT16_FLAGS): Removed. (cpu_flags): Remove field for CpuCVT16. * i386-opc.h (CpuCVT16): Removed. (i386_cpu_flags): Remove bitfield cpucvt16. (i386-opc.tbl): Remove CVT16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
This commit is contained in:
Sebastian Pop
parent
d72de478df
commit
f0ae4a24b0
@ -1,3 +1,9 @@
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2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
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* config/tc-i386.c (cpu_arch): Remove cvt16.
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(md_show_usage): Same.
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* doc/c-i386.texi: Same.
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2009-11-18 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (arm_fpus): Add fpv4-sp-d16.
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@ -644,8 +644,6 @@ static const arch_entry cpu_arch[] =
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CPU_FMA4_FLAGS },
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{ ".xop", PROCESSOR_UNKNOWN,
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CPU_XOP_FLAGS },
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{ ".cvt16", PROCESSOR_UNKNOWN,
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CPU_CVT16_FLAGS },
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{ ".lwp", PROCESSOR_UNKNOWN,
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CPU_LWP_FLAGS },
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{ ".movbe", PROCESSOR_UNKNOWN,
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@ -8127,7 +8125,7 @@ md_show_usage (stream)
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ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
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vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
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clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
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svme, abm, padlock, fma4, xop, cvt16, lwp\n"));
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svme, abm, padlock, fma4, xop, lwp\n"));
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fprintf (stream, _("\
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-mtune=CPU optimize for CPU, CPU is one of:\n\
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i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
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@ -144,7 +144,6 @@ accept various extension mnemonics. For example,
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@code{lwp},
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@code{fma4},
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@code{xop},
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@code{cvt16},
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@code{syscall},
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@code{rdtscp},
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@code{3dnow},
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@ -925,7 +924,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.ept} @tab @samp{.clflush}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cvt16}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
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@item @samp{.padlock}
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@end multitable
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@ -1,3 +1,11 @@
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2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
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* gas/i386/cvt16.d: Removed.
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* gas/i386/cvt16.s: Removed.
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* gas/i386/x86-64-cvt16.d: Removed.
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* gas/i386/x86-64-cvt16.s: Removed.
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* gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests.
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2009-11-18 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/rex.d: Remove suffix on fxsave.
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@ -1,73 +0,0 @@
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#objdump: -dw
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#name: i386 CVT16
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 8f e8 78 a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm7,%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a0 3b 00[ ]+vcvtph2ps \$0x0,\(%ebx\),%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a0 e8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm5
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[ ]*[a-f0-9]+: 8f e8 78 a0 c5 ff[ ]+vcvtph2ps \$0xff,%xmm5,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm7,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 ed 00[ ]+vcvtph2ps \$0x0,%xmm5,%xmm5
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[ ]*[a-f0-9]+: 8f e8 78 a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a0 00 03[ ]+vcvtph2ps \$0x3,\(%eax\),%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 03 ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 38 00[ ]+vcvtph2ps \$0x0,\(%eax\),%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm7,%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a0 ed ff[ ]+vcvtph2ps \$0xff,%xmm5,%xmm5
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[ ]*[a-f0-9]+: 8f e8 78 a0 2b ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%xmm5
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[ ]*[a-f0-9]+: 8f e8 78 a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm7,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 38 03[ ]+vcvtph2ps \$0x3,\(%eax\),%xmm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm7,%ymm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 3b 00[ ]+vcvtph2ps \$0x0,\(%ebx\),%ymm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 e8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm5
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[ ]*[a-f0-9]+: 8f e8 7c a0 c5 ff[ ]+vcvtph2ps \$0xff,%xmm5,%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm7,%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 ed 00[ ]+vcvtph2ps \$0x0,%xmm5,%ymm5
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[ ]*[a-f0-9]+: 8f e8 7c a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 00 03[ ]+vcvtph2ps \$0x3,\(%eax\),%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 03 ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 38 00[ ]+vcvtph2ps \$0x0,\(%eax\),%ymm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm7,%ymm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 ed ff[ ]+vcvtph2ps \$0xff,%xmm5,%ymm5
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[ ]*[a-f0-9]+: 8f e8 7c a0 2b ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%ymm5
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[ ]*[a-f0-9]+: 8f e8 7c a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm7,%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 38 03[ ]+vcvtph2ps \$0x3,\(%eax\),%ymm7
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[ ]*[a-f0-9]+: 8f e8 78 a1 2b 00[ ]+vcvtps2ph \$0x0,%xmm5,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 3e 00[ ]+vcvtps2ph \$0x0,%xmm7,\(%esi\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 00 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 ea ff[ ]+vcvtps2ph \$0xff,%xmm5,%xmm2
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[ ]*[a-f0-9]+: 8f e8 78 a1 c2 03[ ]+vcvtps2ph \$0x3,%xmm0,%xmm2
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[ ]*[a-f0-9]+: 8f e8 78 a1 ea 03[ ]+vcvtps2ph \$0x3,%xmm5,%xmm2
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[ ]*[a-f0-9]+: 8f e8 78 a1 c7 00[ ]+vcvtps2ph \$0x0,%xmm0,%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a1 06 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%esi\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 f8 ff[ ]+vcvtps2ph \$0xff,%xmm7,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a1 3b 00[ ]+vcvtps2ph \$0x0,%xmm7,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 2b ff[ ]+vcvtps2ph \$0xff,%xmm5,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 00 ff[ ]+vcvtps2ph \$0xff,%xmm0,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 38 ff[ ]+vcvtps2ph \$0xff,%xmm7,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 3b 03[ ]+vcvtps2ph \$0x3,%xmm7,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 28 03[ ]+vcvtps2ph \$0x3,%xmm5,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 ef ff[ ]+vcvtps2ph \$0xff,%xmm5,%xmm7
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[ ]*[a-f0-9]+: 8f e8 7c a1 2b 00[ ]+vcvtps2ph \$0x0,%ymm5,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 3e 00[ ]+vcvtps2ph \$0x0,%ymm7,\(%esi\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 00 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 ea ff[ ]+vcvtps2ph \$0xff,%ymm5,%xmm2
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[ ]*[a-f0-9]+: 8f e8 7c a1 c2 03[ ]+vcvtps2ph \$0x3,%ymm0,%xmm2
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[ ]*[a-f0-9]+: 8f e8 7c a1 ea 03[ ]+vcvtps2ph \$0x3,%ymm5,%xmm2
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[ ]*[a-f0-9]+: 8f e8 7c a1 c7 00[ ]+vcvtps2ph \$0x0,%ymm0,%xmm7
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[ ]*[a-f0-9]+: 8f e8 7c a1 06 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%esi\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 f8 ff[ ]+vcvtps2ph \$0xff,%ymm7,%xmm0
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[ ]*[a-f0-9]+: 8f e8 7c a1 3b 00[ ]+vcvtps2ph \$0x0,%ymm7,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 2b ff[ ]+vcvtps2ph \$0xff,%ymm5,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 00 ff[ ]+vcvtps2ph \$0xff,%ymm0,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 38 ff[ ]+vcvtps2ph \$0xff,%ymm7,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 3b 03[ ]+vcvtps2ph \$0x3,%ymm7,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 28 03[ ]+vcvtps2ph \$0x3,%ymm5,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 ef ff[ ]+vcvtps2ph \$0xff,%ymm5,%xmm7
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#pass
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@ -1,74 +0,0 @@
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# Check CVT16 instructions (maxcombos=16, maxops=3, archbits=32, seed=1)
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.allow_index_reg
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.text
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_start:
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# Tests for op VCVTPH2PS imm8, xmm2/mem64, xmm1 (at&t syntax)
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VCVTPH2PS $0x0,%xmm7,%xmm7
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VCVTPH2PS $0x0,(%ebx),%xmm7
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VCVTPH2PS $0x0,%xmm0,%xmm5
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VCVTPH2PS $0xFF,%xmm5,%xmm0
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VCVTPH2PS $0x3,%xmm0,%xmm0
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VCVTPH2PS $0x3,%xmm7,%xmm0
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VCVTPH2PS $0x0,%xmm5,%xmm5
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VCVTPH2PS $0x0,%xmm0,%xmm7
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VCVTPH2PS $0x3,(%eax),%xmm0
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VCVTPH2PS $0xFF,(%ebx),%xmm0
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VCVTPH2PS $0x0,(%eax),%xmm7
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VCVTPH2PS $0xFF,%xmm7,%xmm7
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VCVTPH2PS $0xFF,%xmm5,%xmm5
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VCVTPH2PS $0xFF,(%ebx),%xmm5
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VCVTPH2PS $0xFF,%xmm7,%xmm0
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VCVTPH2PS $0x3,(%eax),%xmm7
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# Tests for op VCVTPH2PS imm8, xmm2/mem128, ymm1 (at&t syntax)
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VCVTPH2PS $0x0,%xmm7,%ymm7
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VCVTPH2PS $0x0,(%ebx),%ymm7
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VCVTPH2PS $0x0,%xmm0,%ymm5
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VCVTPH2PS $0xFF,%xmm5,%ymm0
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VCVTPH2PS $0x3,%xmm0,%ymm0
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VCVTPH2PS $0x3,%xmm7,%ymm0
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VCVTPH2PS $0x0,%xmm5,%ymm5
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VCVTPH2PS $0x0,%xmm0,%ymm7
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VCVTPH2PS $0x3,(%eax),%ymm0
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VCVTPH2PS $0xFF,(%ebx),%ymm0
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VCVTPH2PS $0x0,(%eax),%ymm7
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VCVTPH2PS $0xFF,%xmm7,%ymm7
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VCVTPH2PS $0xFF,%xmm5,%ymm5
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VCVTPH2PS $0xFF,(%ebx),%ymm5
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VCVTPH2PS $0xFF,%xmm7,%ymm0
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VCVTPH2PS $0x3,(%eax),%ymm7
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# Tests for op VCVTPS2PH imm8, xmm2, xmm1/mem64 (at&t syntax)
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VCVTPS2PH $0x0,%xmm5,(%ebx)
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VCVTPS2PH $0x0,%xmm7,(%esi)
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VCVTPS2PH $0x0,%xmm0,(%eax)
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VCVTPS2PH $0xFF,%xmm5,%xmm2
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VCVTPS2PH $0x3,%xmm0,%xmm2
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VCVTPS2PH $0x3,%xmm5,%xmm2
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VCVTPS2PH $0x0,%xmm0,%xmm7
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VCVTPS2PH $0x0,%xmm0,(%esi)
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VCVTPS2PH $0xFF,%xmm7,%xmm0
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VCVTPS2PH $0x0,%xmm7,(%ebx)
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VCVTPS2PH $0xFF,%xmm5,(%ebx)
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VCVTPS2PH $0xFF,%xmm0,(%eax)
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VCVTPS2PH $0xFF,%xmm7,(%eax)
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VCVTPS2PH $0x3,%xmm7,(%ebx)
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VCVTPS2PH $0x3,%xmm5,(%eax)
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VCVTPS2PH $0xFF,%xmm5,%xmm7
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# Tests for op VCVTPS2PH imm8, ymm2, xmm1/mem128 (at&t syntax)
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VCVTPS2PH $0x0,%ymm5,(%ebx)
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VCVTPS2PH $0x0,%ymm7,(%esi)
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VCVTPS2PH $0x0,%ymm0,(%eax)
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VCVTPS2PH $0xFF,%ymm5,%xmm2
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VCVTPS2PH $0x3,%ymm0,%xmm2
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VCVTPS2PH $0x3,%ymm5,%xmm2
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VCVTPS2PH $0x0,%ymm0,%xmm7
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VCVTPS2PH $0x0,%ymm0,(%esi)
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VCVTPS2PH $0xFF,%ymm7,%xmm0
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VCVTPS2PH $0x0,%ymm7,(%ebx)
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VCVTPS2PH $0xFF,%ymm5,(%ebx)
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VCVTPS2PH $0xFF,%ymm0,(%eax)
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VCVTPS2PH $0xFF,%ymm7,(%eax)
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VCVTPS2PH $0x3,%ymm7,(%ebx)
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VCVTPS2PH $0x3,%ymm5,(%eax)
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VCVTPS2PH $0xFF,%ymm5,%xmm7
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@ -163,7 +163,6 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "fma4"
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run_dump_test "lwp"
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run_dump_test "xop"
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run_dump_test "cvt16"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -339,7 +338,6 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-fma4"
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run_dump_test "x86-64-lwp"
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run_dump_test "x86-64-xop"
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run_dump_test "x86-64-cvt16"
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if { ![istarget "*-*-aix*"]
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&& ![istarget "*-*-beos*"]
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@ -1,73 +0,0 @@
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#objdump: -dw
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#name: x86-64 CVT16
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 8f 48 78 a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm15,%xmm15
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[ ]*[a-f0-9]+: 8f 68 78 a0 3e 00[ ]+vcvtph2ps \$0x0,\(%rsi\),%xmm15
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[ ]*[a-f0-9]+: 8f 68 78 a0 d8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm11
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[ ]*[a-f0-9]+: 8f c8 78 a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm15,%xmm0
|
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[ ]*[a-f0-9]+: 8f e8 78 a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%xmm0
|
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[ ]*[a-f0-9]+: 8f c8 78 a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm15,%xmm0
|
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[ ]*[a-f0-9]+: 8f 48 78 a0 db 00[ ]+vcvtph2ps \$0x0,%xmm11,%xmm11
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[ ]*[a-f0-9]+: 8f 68 78 a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm15
|
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[ ]*[a-f0-9]+: 8f e8 78 a0 01 03[ ]+vcvtph2ps \$0x3,\(%rcx\),%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 06 ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%xmm0
|
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[ ]*[a-f0-9]+: 8f 68 78 a0 3f 00[ ]+vcvtph2ps \$0x0,\(%rdi\),%xmm15
|
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[ ]*[a-f0-9]+: 8f 48 78 a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm15,%xmm15
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[ ]*[a-f0-9]+: 8f 48 78 a0 db ff[ ]+vcvtph2ps \$0xff,%xmm11,%xmm11
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a0 1e ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%xmm11
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a0 3f 03[ ]+vcvtph2ps \$0x3,\(%rdi\),%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a0 df 03[ ]+vcvtph2ps \$0x3,%xmm15,%xmm11
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm15,%ymm15
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 3e 00[ ]+vcvtph2ps \$0x0,\(%rsi\),%ymm15
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 d8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm11
|
||||
[ ]*[a-f0-9]+: 8f c8 7c a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm15,%ymm0
|
||||
[ ]*[a-f0-9]+: 8f e8 7c a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%ymm0
|
||||
[ ]*[a-f0-9]+: 8f c8 7c a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm15,%ymm0
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a0 db 00[ ]+vcvtph2ps \$0x0,%xmm11,%ymm11
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm15
|
||||
[ ]*[a-f0-9]+: 8f e8 7c a0 01 03[ ]+vcvtph2ps \$0x3,\(%rcx\),%ymm0
|
||||
[ ]*[a-f0-9]+: 8f e8 7c a0 06 ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%ymm0
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 3f 00[ ]+vcvtph2ps \$0x0,\(%rdi\),%ymm15
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm15,%ymm15
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a0 db ff[ ]+vcvtph2ps \$0xff,%xmm11,%ymm11
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 1e ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%ymm11
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 3f 03[ ]+vcvtph2ps \$0x3,\(%rdi\),%ymm15
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a0 df 03[ ]+vcvtph2ps \$0x3,%xmm15,%ymm11
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 18 00[ ]+vcvtps2ph \$0x0,%xmm11,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 3f 00[ ]+vcvtps2ph \$0x0,%xmm15,\(%rdi\)
|
||||
[ ]*[a-f0-9]+: 8f c8 78 a1 04 24 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a1 df ff[ ]+vcvtps2ph \$0xff,%xmm11,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f c8 78 a1 c7 03[ ]+vcvtps2ph \$0x3,%xmm0,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a1 df 03[ ]+vcvtps2ph \$0x3,%xmm11,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f e8 78 a1 c4 00[ ]+vcvtps2ph \$0x0,%xmm0,%xmm4
|
||||
[ ]*[a-f0-9]+: 8f e8 78 a1 07 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%rdi\)
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 f8 ff[ ]+vcvtps2ph \$0xff,%xmm15,%xmm0
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 38 00[ ]+vcvtps2ph \$0x0,%xmm15,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 18 ff[ ]+vcvtps2ph \$0xff,%xmm11,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f c8 78 a1 04 24 ff[ ]+vcvtps2ph \$0xff,%xmm0,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a1 3c 24 ff[ ]+vcvtps2ph \$0xff,%xmm15,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 38 03[ ]+vcvtps2ph \$0x3,%xmm15,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a1 1c 24 03[ ]+vcvtps2ph \$0x3,%xmm11,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 dc ff[ ]+vcvtps2ph \$0xff,%xmm11,%xmm4
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 18 00[ ]+vcvtps2ph \$0x0,%ymm11,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 3f 00[ ]+vcvtps2ph \$0x0,%ymm15,\(%rdi\)
|
||||
[ ]*[a-f0-9]+: 8f c8 7c a1 04 24 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a1 df ff[ ]+vcvtps2ph \$0xff,%ymm11,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f c8 7c a1 c7 03[ ]+vcvtps2ph \$0x3,%ymm0,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a1 df 03[ ]+vcvtps2ph \$0x3,%ymm11,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f e8 7c a1 c4 00[ ]+vcvtps2ph \$0x0,%ymm0,%xmm4
|
||||
[ ]*[a-f0-9]+: 8f e8 7c a1 07 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%rdi\)
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 f8 ff[ ]+vcvtps2ph \$0xff,%ymm15,%xmm0
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 38 00[ ]+vcvtps2ph \$0x0,%ymm15,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 18 ff[ ]+vcvtps2ph \$0xff,%ymm11,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f c8 7c a1 04 24 ff[ ]+vcvtps2ph \$0xff,%ymm0,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a1 3c 24 ff[ ]+vcvtps2ph \$0xff,%ymm15,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 38 03[ ]+vcvtps2ph \$0x3,%ymm15,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a1 1c 24 03[ ]+vcvtps2ph \$0x3,%ymm11,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 dc ff[ ]+vcvtps2ph \$0xff,%ymm11,%xmm4
|
||||
#pass
|
||||
@ -1,74 +0,0 @@
|
||||
# Check CVT16 instructions (maxcombos=16, maxops=3, archbits=64, seed=1)
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
# Tests for op VCVTPH2PS imm8, xmm2/mem64, xmm1 (at&t syntax)
|
||||
VCVTPH2PS $0x0,%xmm15,%xmm15
|
||||
VCVTPH2PS $0x0,(%rsi),%xmm15
|
||||
VCVTPH2PS $0x0,%xmm0,%xmm11
|
||||
VCVTPH2PS $0xFF,%xmm15,%xmm0
|
||||
VCVTPH2PS $0x3,%xmm0,%xmm0
|
||||
VCVTPH2PS $0x3,%xmm15,%xmm0
|
||||
VCVTPH2PS $0x0,%xmm11,%xmm11
|
||||
VCVTPH2PS $0x0,%xmm0,%xmm15
|
||||
VCVTPH2PS $0x3,(%rcx),%xmm0
|
||||
VCVTPH2PS $0xFF,(%rsi),%xmm0
|
||||
VCVTPH2PS $0x0,(%rdi),%xmm15
|
||||
VCVTPH2PS $0xFF,%xmm15,%xmm15
|
||||
VCVTPH2PS $0xFF,%xmm11,%xmm11
|
||||
VCVTPH2PS $0xFF,(%rsi),%xmm11
|
||||
VCVTPH2PS $0x3,(%rdi),%xmm15
|
||||
VCVTPH2PS $0x3,%xmm15,%xmm11
|
||||
# Tests for op VCVTPH2PS imm8, xmm2/mem128, ymm1 (at&t syntax)
|
||||
VCVTPH2PS $0x0,%xmm15,%ymm15
|
||||
VCVTPH2PS $0x0,(%rsi),%ymm15
|
||||
VCVTPH2PS $0x0,%xmm0,%ymm11
|
||||
VCVTPH2PS $0xFF,%xmm15,%ymm0
|
||||
VCVTPH2PS $0x3,%xmm0,%ymm0
|
||||
VCVTPH2PS $0x3,%xmm15,%ymm0
|
||||
VCVTPH2PS $0x0,%xmm11,%ymm11
|
||||
VCVTPH2PS $0x0,%xmm0,%ymm15
|
||||
VCVTPH2PS $0x3,(%rcx),%ymm0
|
||||
VCVTPH2PS $0xFF,(%rsi),%ymm0
|
||||
VCVTPH2PS $0x0,(%rdi),%ymm15
|
||||
VCVTPH2PS $0xFF,%xmm15,%ymm15
|
||||
VCVTPH2PS $0xFF,%xmm11,%ymm11
|
||||
VCVTPH2PS $0xFF,(%rsi),%ymm11
|
||||
VCVTPH2PS $0x3,(%rdi),%ymm15
|
||||
VCVTPH2PS $0x3,%xmm15,%ymm11
|
||||
# Tests for op VCVTPS2PH imm8, xmm2, xmm1/mem64 (at&t syntax)
|
||||
VCVTPS2PH $0x0,%xmm11,(%rax)
|
||||
VCVTPS2PH $0x0,%xmm15,(%rdi)
|
||||
VCVTPS2PH $0x0,%xmm0,(%r12)
|
||||
VCVTPS2PH $0xFF,%xmm11,%xmm15
|
||||
VCVTPS2PH $0x3,%xmm0,%xmm15
|
||||
VCVTPS2PH $0x3,%xmm11,%xmm15
|
||||
VCVTPS2PH $0x0,%xmm0,%xmm4
|
||||
VCVTPS2PH $0x0,%xmm0,(%rdi)
|
||||
VCVTPS2PH $0xFF,%xmm15,%xmm0
|
||||
VCVTPS2PH $0x0,%xmm15,(%rax)
|
||||
VCVTPS2PH $0xFF,%xmm11,(%rax)
|
||||
VCVTPS2PH $0xFF,%xmm0,(%r12)
|
||||
VCVTPS2PH $0xFF,%xmm15,(%r12)
|
||||
VCVTPS2PH $0x3,%xmm15,(%rax)
|
||||
VCVTPS2PH $0x3,%xmm11,(%r12)
|
||||
VCVTPS2PH $0xFF,%xmm11,%xmm4
|
||||
# Tests for op VCVTPS2PH imm8, ymm2, xmm1/mem128 (at&t syntax)
|
||||
VCVTPS2PH $0x0,%ymm11,(%rax)
|
||||
VCVTPS2PH $0x0,%ymm15,(%rdi)
|
||||
VCVTPS2PH $0x0,%ymm0,(%r12)
|
||||
VCVTPS2PH $0xFF,%ymm11,%xmm15
|
||||
VCVTPS2PH $0x3,%ymm0,%xmm15
|
||||
VCVTPS2PH $0x3,%ymm11,%xmm15
|
||||
VCVTPS2PH $0x0,%ymm0,%xmm4
|
||||
VCVTPS2PH $0x0,%ymm0,(%rdi)
|
||||
VCVTPS2PH $0xFF,%ymm15,%xmm0
|
||||
VCVTPS2PH $0x0,%ymm15,(%rax)
|
||||
VCVTPS2PH $0xFF,%ymm11,(%rax)
|
||||
VCVTPS2PH $0xFF,%ymm0,(%r12)
|
||||
VCVTPS2PH $0xFF,%ymm15,(%r12)
|
||||
VCVTPS2PH $0x3,%ymm15,(%rax)
|
||||
VCVTPS2PH $0x3,%ymm11,(%r12)
|
||||
VCVTPS2PH $0xFF,%ymm11,%xmm4
|
||||
@ -1,3 +1,18 @@
|
||||
2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
|
||||
|
||||
* i386-dis.c (VEX_LEN_XOP_08_A0): Removed.
|
||||
(VEX_LEN_XOP_08_A1): Removed.
|
||||
(xop_table): Remove entries for VEX_LEN_XOP_08_A0 and
|
||||
VEX_LEN_XOP_08_A1.
|
||||
(vex_len_table): Same.
|
||||
* i386-gen.c (CPU_CVT16_FLAGS): Removed.
|
||||
(cpu_flags): Remove field for CpuCVT16.
|
||||
* i386-opc.h (CpuCVT16): Removed.
|
||||
(i386_cpu_flags): Remove bitfield cpucvt16.
|
||||
(i386-opc.tbl): Remove CVT16 instructions.
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Regenerated.
|
||||
|
||||
2009-11-17 Sebastian Pop <sebastian.pop@amd.com>
|
||||
Quentin Neill <quentin.neill@amd.com>
|
||||
|
||||
|
||||
@ -1293,8 +1293,6 @@ enum
|
||||
VEX_LEN_3A7E_P_2,
|
||||
VEX_LEN_3A7F_P_2,
|
||||
VEX_LEN_3ADF_P_2,
|
||||
VEX_LEN_XOP_08_A0,
|
||||
VEX_LEN_XOP_08_A1,
|
||||
VEX_LEN_XOP_09_80,
|
||||
VEX_LEN_XOP_09_81
|
||||
};
|
||||
@ -6573,8 +6571,8 @@ static const struct dis386 xop_table[][256] = {
|
||||
{ "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
/* a0 */
|
||||
{ VEX_LEN_TABLE (VEX_LEN_XOP_08_A0) },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_XOP_08_A1) },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
@ -9353,16 +9351,6 @@ static const struct dis386 vex_len_table[][2] = {
|
||||
{ "vaeskeygenassist", { XM, EXx, Ib } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
/* VEX_LEN_XOP_08_A0 */
|
||||
{
|
||||
{ "vcvtph2ps", { XM, EXq, Ib } },
|
||||
{ "vcvtph2ps", { XM, EXxmm, Ib } },
|
||||
},
|
||||
/* VEX_LEN_XOP_08_A1 */
|
||||
{
|
||||
{ "vcvtps2ph", { EXq, XM, Ib } },
|
||||
{ "vcvtps2ph", { EXxmm, XM, Ib } },
|
||||
},
|
||||
/* VEX_LEN_XOP_09_80 */
|
||||
{
|
||||
{ "vfrczps", { XM, EXxmm } },
|
||||
|
||||
@ -129,9 +129,7 @@ static initializer cpu_flag_init[] =
|
||||
{ "CPU_FMA4_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA4" },
|
||||
{ "CPU_XOP_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP|CpuCVT16" },
|
||||
{ "CPU_CVT16_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP|CpuCVT16" },
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" },
|
||||
{ "CPU_LWP_FLAGS",
|
||||
"CpuLWP" },
|
||||
{ "CPU_MOVBE_FLAGS",
|
||||
@ -303,7 +301,6 @@ static bitfield cpu_flags[] =
|
||||
BITFIELD (CpuFMA),
|
||||
BITFIELD (CpuFMA4),
|
||||
BITFIELD (CpuXOP),
|
||||
BITFIELD (CpuCVT16),
|
||||
BITFIELD (CpuLWP),
|
||||
BITFIELD (CpuLM),
|
||||
BITFIELD (CpuMovbe),
|
||||
|
||||
@ -22,292 +22,287 @@
|
||||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 0, 1, 1 } }
|
||||
1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0 } }
|
||||
1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0 } }
|
||||
1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0 } }
|
||||
1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_8087_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_287_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_387_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY87_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CVT16_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_LWP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_L1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 0, 1, 1 } }
|
||||
1, 0, 1, 1 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
||||
@ -104,8 +104,6 @@ enum
|
||||
CpuFMA4,
|
||||
/* XOP support required */
|
||||
CpuXOP,
|
||||
/* CVT16 support required */
|
||||
CpuCVT16,
|
||||
/* LWP support required */
|
||||
CpuLWP,
|
||||
/* MOVBE Instuction support required */
|
||||
@ -175,7 +173,6 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpufma:1;
|
||||
unsigned int cpufma4:1;
|
||||
unsigned int cpuxop:1;
|
||||
unsigned int cpucvt16:1;
|
||||
unsigned int cpulwp:1;
|
||||
unsigned int cpumovbe:1;
|
||||
unsigned int cpuept:1;
|
||||
|
||||
@ -2548,13 +2548,6 @@ vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sourc
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
// CVT16 instructions
|
||||
|
||||
vcvtph2ps, 3, 0xa0, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vcvtph2ps, 3, 0xa0, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM }
|
||||
vcvtps2ph, 3, 0xa1, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM, Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex }
|
||||
vcvtps2ph, 3, 0xa1, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Imm8, RegYMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex }
|
||||
|
||||
// XOP instructions
|
||||
|
||||
vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
|
||||
4880
opcodes/i386-tbl.h
4880
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user