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2003-01-14 Chris Demetriou <cgd@broadcom.com>

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* mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
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Chris Demetriou 2003-01-14 19:01:41 +00:00
parent a0d9b83140
commit d29e330fda
2 changed files with 38 additions and 0 deletions
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4
sim/mips/ChangeLog
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@ -1,3 +1,7 @@
2003-01-14 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
2003-01-14 Chris Demetriou <cgd@broadcom.com>
* mips.igen (EI, DI): Remove.

34
sim/mips/mips.igen
View File

@ -4271,6 +4271,22 @@
}
010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
"luxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsV:
*mips64:
{
address_word base = GPR[BASE];
address_word index = GPR[INDEX];
address_word vaddr = base + index;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
if ((vaddr & 0x7) != 0)
index -= (vaddr & 0x7);
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
}
110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
@ -4743,6 +4759,24 @@
}
010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
"suxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsV:
*mips64:
{
unsigned64 v;
address_word base = GPR[BASE];
address_word index = GPR[INDEX];
address_word vaddr = base + index;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
if ((vaddr & 0x7) != 0)
index -= (vaddr & 0x7);
do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
}
010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
"sqrt.%s<FMT> f<FD>, f<FS>"
*mipsII: