Peter Targett's backwards compatibility and other arc fixes.

bfd/ChangeLog

@@ -1,3 +1,13 @@
+2001-05-12  Peter Targett  <peter.targett@arccores.com>
+
+	* cpu-arc.c (arch_info_struct): Add entry 'base' representing old
+	name for 'arc5' core versions.
+	(bfd_arc_arch): Make bfd_mach_arc_6 default.
+
+	* elf32-arc.c (arc_elf_object_p): Make E_ARC_MACH_ARC6 default
+	architecture.
+	(arc_elf_final_write_processing): Make bfd_mach_arc_6 default.
+
 2001-05-11  Jakub Jelinek  <jakub@redhat.com>
 
 	* elfxx-ia64.c (is_unwind_section_name): Consider linkonce unwind

bfd/cpu-arc.c

@@ -41,13 +41,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 static const bfd_arch_info_type arch_info_struct[] =
 {
   ARC ( bfd_mach_arc_5, "arc5", false, &arch_info_struct[1] ),
-  ARC ( bfd_mach_arc_6, "arc6", false, &arch_info_struct[2] ),
+  ARC ( bfd_mach_arc_5, "base", false, &arch_info_struct[2] ),
-  ARC ( bfd_mach_arc_7, "arc7", false, &arch_info_struct[3] ),
+  ARC ( bfd_mach_arc_6, "arc6", false, &arch_info_struct[3] ),
+  ARC ( bfd_mach_arc_7, "arc7", false, &arch_info_struct[4] ),
   ARC ( bfd_mach_arc_8, "arc8", false, NULL ),
 };
 
 const bfd_arch_info_type bfd_arc_arch =
-  ARC ( bfd_mach_arc_5, "arc", true, &arch_info_struct[0] );
+  ARC ( bfd_mach_arc_6, "arc", true, &arch_info_struct[0] );
 
 /* Utility routines.  */
 

bfd/elf32-arc.c

@@ -155,7 +155,7 @@ static boolean
 arc_elf_object_p (abfd)
      bfd *abfd;
 {
-  int mach = bfd_mach_arc_5;
+  int mach = bfd_mach_arc_6;
 
   if (elf_elfheader(abfd)->e_machine == EM_ARC)
     {
@@ -163,10 +163,10 @@ arc_elf_object_p (abfd)
 
       switch (arch)
 	{
-	default:
 	case E_ARC_MACH_ARC5:
 	  mach = bfd_mach_arc_5;
 	  break;
+	default:
 	case E_ARC_MACH_ARC6:
 	  mach = bfd_mach_arc_6;
 	  break;
@@ -193,10 +193,10 @@ arc_elf_final_write_processing (abfd, linker)
 
   switch (bfd_get_mach (abfd))
     {
-    default:
     case bfd_mach_arc_5:
       val = E_ARC_MACH_ARC5;
       break;
+    default:
     case bfd_mach_arc_6:
       val = E_ARC_MACH_ARC6;
       break;

gas/ChangeLog

@@ -1,3 +1,21 @@
+2001-05-12  Peter Targett  <peter.targett@arccores.com>
+
+	* config/tc-arc.c: Update copyright and tidy source comments.
+	(md_pseudo_table): Add directive .cpu back as an alias for
+	.option.  Add .file and .line for dwarf2 support.
+	(arc_mach_type): Make bfd_mach_arc_6 default.
+	(md_longopts): Add entry 'pre-v6' representing old command line
+	option when assembling for 'arc5' core versions.
+	(md_parse_option): Make OPTION_ARC same as OPTION_ARC6, for new
+	default behaviour.
+	(arc_code_symbol): Make symbol value for @h30 fixup expression
+	equal to O_constant.
+	(md_assemble): Call dwarf2_emit_insn.
+	Include "dwarf2dbg2.h".  Formatting fixes throughout file.
+	* config/tc-arc.h (DWARF2_LINE_MIN_INSN_LENGTH): Define.
+
+	* doc/c-arc.texi (ARC_CORE_DEFAULT): Update to new default.
+
 2001-05-11  Jakub Jelinek  <jakub@redhat.com>
 
 	* config/tc-ia64.c (special_linkonce_name): New.

gas/config/tc-arc.c

@@ -28,6 +28,7 @@
 #include "opcode/arc.h"
 #include "../opcodes/arc-ext.h"
 #include "elf/arc.h"
+#include "dwarf2dbg.h"
 
 extern int arc_get_mach PARAMS ((char *));
 extern int arc_operand_type PARAMS ((int));
@@ -76,7 +77,7 @@ const struct syntax_classes {
 #define MAXSYNTAXCLASS (sizeof (syntaxclass) / sizeof (struct syntax_classes))
 
 const pseudo_typeS md_pseudo_table[] = {
-  { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0) */
+  { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
   { "comm", arc_common, 0 },
   { "common", arc_common, 0 },
   { "lcomm", arc_common, 1 },
@@ -88,7 +89,10 @@ const pseudo_typeS md_pseudo_table[] = {
   { "4byte", cons, 4 },
   { "word", cons, 4 },
   { "option", arc_option, 0 },
+  { "cpu", arc_option, 0 },
   { "block", s_space, 0 },
+  { "file", dwarf2_directive_file, 0 },
+  { "loc", dwarf2_directive_loc, 0 },
   { "extcondcode", arc_extoper, 0 },
   { "extcoreregister", arc_extoper, 1 },
   { "extauxregister", arc_extoper, 2 },
@@ -97,7 +101,7 @@ const pseudo_typeS md_pseudo_table[] = {
 };
 
 /* This array holds the chars that always start a comment.  If the
-   pre-processor is disabled, these aren't very useful */
+   pre-processor is disabled, these aren't very useful.  */
 const char comment_chars[] = "#;";
 
 /* This array holds the chars that only start a comment at the beginning of
@@ -112,12 +116,11 @@ const char line_comment_chars[] = "#";
 
 const char line_separator_chars[] = "";
 
-/* Chars that can be used to separate mant from exp in floating point nums */
+/* Chars that can be used to separate mant from exp in floating point nums.  */
 const char EXP_CHARS[] = "eE";
 
-/* Chars that mean this number is a floating point constant */
+/* Chars that mean this number is a floating point constant
-/* As in 0f12.456 */
+   As in 0f12.456 or 0d1.2345e12.  */
-/* or    0d1.2345e12 */
 const char FLT_CHARS[] = "rRsSfFdD";
 
 /* Byte order.  */
@@ -128,13 +131,13 @@ static int byte_order = DEFAULT_BYTE_ORDER;
 static segT arcext_section;
 
 /* One of bfd_mach_arc_n.  */
-static int arc_mach_type = bfd_mach_arc_5;
+static int arc_mach_type = bfd_mach_arc_6;
 
 /* Non-zero if the cpu type has been explicitly specified.  */
 static int mach_type_specified_p = 0;
 
 /* Non-zero if opcode tables have been initialized.
-   A .cpu command must appear before any instructions.  */
+   A .option command must appear before any instructions.  */
 static int cpu_tables_init_p = 0;
 
 static struct hash_control *arc_suffix_hash = NULL;
@@ -147,6 +150,7 @@ struct option md_longopts[] = {
   { "EL", no_argument, NULL, OPTION_EL },
 #define OPTION_ARC5 (OPTION_MD_BASE + 2)
   { "marc5", no_argument, NULL, OPTION_ARC5 },
+  { "pre-v6", no_argument, NULL, OPTION_ARC5 },
 #define OPTION_ARC6 (OPTION_MD_BASE + 3)
   { "marc6", no_argument, NULL, OPTION_ARC6 },
 #define OPTION_ARC7 (OPTION_MD_BASE + 4)
@@ -174,10 +178,10 @@ md_parse_option (c, arg)
 {
   switch (c)
     {
-    case OPTION_ARC:
     case OPTION_ARC5:
       arc_mach_type = bfd_mach_arc_5;
       break;
+    case OPTION_ARC:
     case OPTION_ARC6:
       arc_mach_type = bfd_mach_arc_6;
       break;
@@ -214,7 +218,7 @@ ARC Options:\n\
 
 /* This function is called once, at assembler startup time.  It should
    set up all the tables, etc. that the MD part of the assembler will need.
-   Opcode selection is defered until later because we might see a .cpu
+   Opcode selection is deferred until later because we might see a .option
    command.  */
 
 void
@@ -226,16 +230,14 @@ md_begin ()
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
     as_warn ("could not set architecture and machine");
 
-  /* This call is necessary because we need to
+  /* This call is necessary because we need to initialize `arc_operand_map'
-     initialize `arc_operand_map' which may be needed before we see the
+     which may be needed before we see the first insn.  */
-     first insn.  */
   arc_opcode_init_tables (arc_get_opcode_mach (arc_mach_type,
 					       target_big_endian));
 }
 
 /* Initialize the various opcode and operand tables.
    MACH is one of bfd_mach_arc_xxx.  */
-
 static void
 init_opcode_tables (mach)
      int mach;
@@ -277,8 +279,10 @@ init_opcode_tables (mach)
 	continue;
       /* Use symbol_create here instead of symbol_new so we don't try to
 	 output registers into the object file's symbol table.  */
-      symbol_table_insert (symbol_create (arc_reg_names[i].name, reg_section,
+      symbol_table_insert (symbol_create (arc_reg_names[i].name,
-                           (int) &arc_reg_names[i], &zero_address_frag));
+					  reg_section,
+					  (int) &arc_reg_names[i],
+					  &zero_address_frag));
     }
 
   /* Tell `.option' it's too late.  */
@@ -381,7 +385,7 @@ md_assemble (str)
   static int init_tables_p = 0;
 
   /* Opcode table initialization is deferred until here because we have to
-     wait for a possible .cpu command.  */
+     wait for a possible .option command.  */
   if (!init_tables_p)
     {
       init_opcode_tables (arc_mach_type);
@@ -866,6 +870,8 @@ md_assemble (str)
 			   (bfd_reloc_code_real_type) reloc_type);
 	    }
 
+	  dwarf2_emit_insn (4);
+
 	  /* All done.  */
 	  return;
 	}
@@ -1631,6 +1637,7 @@ arc_code_symbol (expressionP)
     {
       expressionS two;
       expressionP->X_op = O_right_shift;
+      expressionP->X_add_symbol->sy_value.X_op = O_constant;
       two.X_op = O_constant;
       two.X_add_symbol = two.X_op_symbol = NULL;
       two.X_add_number = 2;
@@ -1687,7 +1694,8 @@ md_operand (expressionP)
 	arc_code_symbol (expressionP);
       }
     else
-      {       /* It could be a register.  */
+      {
+	/* It could be a register.  */
 	int i, l;
 	struct arc_ext_operand_value *ext_oper = arc_ext_operands;
 	p++;

gas/config/tc-arc.h

@@ -66,3 +66,5 @@ arc_parse_cons_expression (EXP, NBYTES)
 extern void arc_cons_fix_new ();
 #define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \
 arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP)
+
+#define DWARF2_LINE_MIN_INSN_LENGTH 4

gas/doc/c-arc.texi

@@ -13,7 +13,7 @@
 @chapter ARC Dependent Features
 @end ifclear
 
-@set ARC_CORE_DEFAULT 5
+@set ARC_CORE_DEFAULT 6
 
 @cindex ARC support
 @menu

gas/testsuite/ChangeLog

@@ -1,3 +1,8 @@
+2001-05-12  Peter Targett  <peter.targett@arccores.com>
+
+	* gas/arc/st.s: Add test case @h30 fixup.
+	* gas/arc/st.d: Update to suit.
+
 2001-05-12  Alan Modra  <amodra@one.net.au>
 
 	* gas/i386/sse2.s: Correct cvtps2dq, movdq2q, and movq2dq

gas/testsuite/gas/arc/st.d

@@ -23,5 +23,11 @@ Disassembly of section .text:
   34:	02 02 01 14 	14010202     st.di      r1,\[r2,2\]
   38:	03 02 01 15 	15010203     st.a.di    r1,\[r2,3\]
   3c:	04 02 81 15 	15810204     stw.a.di   r1,\[r2,4\]
-  40:	00 02 01 12 	12010200     sr         r1,\[r2\]
+  40:	04 7c 06 10 	10067c04     st         80,\[r12,4\]
-  44:	0e 82 1f 12 	121f820e     sr         r1,\[0xe\]
+  44:	50 00 00 00 
+			44: R_ARC_32	.text
+  48:	04 7c 06 10 	10067c04     st         20,\[r12,4\]
+  4c:	14 00 00 00 
+			4c: R_ARC_B26	.text
+  50:	00 02 01 12 	12010200     sr         r1,\[r2\]
+  54:	0e 82 1f 12 	121f820e     sr         r1,\[0xe\]

gas/testsuite/gas/arc/st.s

@@ -14,5 +14,9 @@
 	st.a.di	r1,[r2,3]
 	stw.a.di r1,[r2,4]
 
+	st .L1,[r12,4]
+	st .L1@h30,[r12,4]
+.L1:
+
 	sr	r1,[r2]
 	sr	r1,[14]

opcodes/ChangeLog

@@ -1,3 +1,8 @@
+2001-05-12  Peter Targett  <peter.targett@arccores.com>
+
+	* arc-opc.c (arc_reg_names): Correct attribute for lp_count
+	register to r/w.  Formatting fixes throughout file.
+
 2001-05-12  Alan Modra  <amodra@one.net.au>
 
 	* i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and

opcodes/arc-opc.c

@@ -382,7 +382,7 @@ const struct arc_operand_value arc_reg_names[] =
   { "r59", 59, REG, 0 },
 
   /* Loop count register (24 bits).  */
-  { "lp_count", 60, REG, ARC_REGISTER_READONLY },
+  { "lp_count", 60, REG, 0 },
   /* Short immediate data indicator setting flags.  */
   { "r61", 61, REG, ARC_REGISTER_READONLY },
   /* Long immediate data indicator setting flags.  */
@@ -1060,6 +1060,7 @@ extract_st_syntax (insn, operand, mods, opval, invalid)
 ((ls_operand[LS_VALUE]  == (V) && \
   ls_operand[LS_BASE]   == (B) && \
   ls_operand[LS_OFFSET] == (O)))
+
   if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
 	|| ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
 	|| (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
@@ -1092,7 +1093,7 @@ arc_limm_fixup_adjust(insn)
       if (retval & 0x100) /* sign extend 9 bit offset.  */
 	retval |= ~0x1ff;
     }
-  return(-retval); /* negate offset for return.  */
+  return -retval; /* negate offset for return.  */
 }
 
 /* Used in st insns to do final syntax check.  */
@@ -1326,8 +1327,8 @@ insert_jumpflags (insn, operand, mods, reg, value, errmsg)
       *errmsg = "bad jump flags value";
     }
   jumpflags_p = 1;
-  limm = (limm & ((1 << operand->shift) - 1))
+  limm = ((limm & ((1 << operand->shift) - 1))
-    | ((value & ((1 << operand->bits) - 1)) << operand->shift); 
+	  | ((value & ((1 << operand->bits) - 1)) << operand->shift));
   return insn;
 }
 
@@ -1687,8 +1688,8 @@ extract_ld_offset (insn, operand, mods, opval, invalid)
       return(value);
     }
   /* if it isn't in the insn, it's concealed behind reg 'c'.  */
-  return extract_reg(insn,
+  return extract_reg (insn, &arc_operands[arc_operand_map['c']],
-                     &arc_operands[arc_operand_map['c']], mods, opval, invalid);
+		      mods, opval, invalid);
 }
 
 /* The only thing this does is set the `invalid' flag if B != C.
@@ -1779,8 +1780,8 @@ int
 arc_insn_not_jl(insn)
   arc_insn insn;
 {
-  return (insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) !=
+  return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1)))
-    (I(0x7) | R(-1,9,1));
+	  != (I(0x7) | R(-1,9,1)));
 }
 
 int
@@ -1814,11 +1815,11 @@ get_ext_suffix(s)
 	return(&suffix->operand);
       suffix = suffix->next;
     }
-  return(NULL);
+  return NULL;
 }
 
 int
 arc_get_noshortcut_flag()
 {
-  return(ARC_REGISTER_NOSHORT_CUT);
+  return ARC_REGISTER_NOSHORT_CUT;
 }