gdb: Add OpenRISC or1k and or1knd target support
This patch prepares the current GDB port of the OpenRISC processor from https://github.com/openrisc/binutils-gdb for upstream merging. Testing has been done with a cgen sim provided in a separate patch. This has been tested with 2 toolchains. GCC [1] 5.4.0 from the OpenRISC project with Newlib [2] and GCC 5.4.0 with Musl [3] 1.1.4. It supports or1knd (no delay slot target). The default target is or1k (with delay slot). You can change the target arch with: (gdb) set architecture or1knd The target architecture is assumed to be or1knd [1] https://github.com/openrisc/or1k-gcc [2] https://github.com/openrisc/newlib [3] https://github.com/openrisc/musl-cross gdb/doc/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Stefan Wallentowitz <stefan@wallentowitz.de> Franck Jullien <franck.jullien@gmail.com> Jeremy Bennett <jeremy.bennett@embecosm.com> * gdb.texinfo: Add OpenRISC documentation. gdb/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Stefan Wallentowitz <stefan@wallentowitz.de> Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Franck Jullien <franck.jullien@gmail.com> Jeremy Bennett <jeremy.bennett@embecosm.com> * configure.tgt: Add targets for or1k and or1knd. * or1k-tdep.c: New file. * or1k-tdep.h: New file. * features/Makefile: Add or1k.xml to build. * features/or1k.xml: New file. * features/or1k-core.xml: New file. * features/or1k.c: Generated.
This commit is contained in:
Franck Jullien
Stafford Horne
parent
db9077b727
commit
a994fec4f8
@ -1,3 +1,17 @@
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2017-12-12 Stafford Horne <shorne@gmail.com>
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Stefan Wallentowitz <stefan@wallentowitz.de>
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Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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Franck Jullien <franck.jullien@gmail.com>
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Jeremy Bennett <jeremy.bennett@embecosm.com>
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* configure.tgt: Add targets for or1k and or1knd.
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* or1k-tdep.c: New file.
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* or1k-tdep.h: New file.
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* features/Makefile: Add or1k.xml to build.
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* features/or1k.xml: New file.
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* features/or1k-core.xml: New file.
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* features/or1k.c: Generated.
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2017-12-12 Alan Modra <amodra@gmail.com>
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PR tdep/22576
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@ -463,6 +463,12 @@ nios2*-*-*)
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gdb_target_obs="nios2-tdep.o"
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;;
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or1k-*-* | or1knd-*-*)
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# Target: OpenCores OpenRISC 1000 32-bit implementation bare metal
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gdb_target_obs="or1k-tdep.o"
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gdb_sim=../sim/or1k/libsim.a
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;;
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powerpc*-*-freebsd*)
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# Target: FreeBSD/powerpc
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gdb_target_obs="rs6000-tdep.o ppc-sysv-tdep.o ppc64-tdep.o \
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@ -1,3 +1,10 @@
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2017-12-12 Stafford Horne <shorne@gmail.com>
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Stefan Wallentowitz <stefan@wallentowitz.de>
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Franck Jullien <franck.jullien@gmail.com>
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Jeremy Bennett <jeremy.bennett@embecosm.com>
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* gdb.texinfo: Add OpenRISC documentation.
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2017-12-08 Jan Kratochvil <jan.kratochvil@redhat.com>
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* gdb.texinfo (Index Files): Document .debug_names and -dwarf-5.
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@ -546,6 +546,11 @@ was developed by SRI International and the University of Cambridge
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Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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("CTSRD"), as part of the DARPA CRASH research programme.
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The original port to the OpenRISC 1000 is believed to be due to
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Alessandro Forin and Per Bothner. More recent ports have been the work
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of Jeremy Bennett, Franck Jullien, Stefan Wallentowitz and
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Stafford Horne.
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@node Sample Session
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@chapter A Sample @value{GDBN} Session
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@ -22442,6 +22447,7 @@ acceptable commands.
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* M68K:: Motorola M68K
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* MicroBlaze:: Xilinx MicroBlaze
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* MIPS Embedded:: MIPS Embedded
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* OpenRISC 1000:: OpenRISC 1000 (or1k)
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* PowerPC Embedded:: PowerPC Embedded
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* AVR:: Atmel AVR
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* CRIS:: CRIS
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@ -22651,6 +22657,38 @@ As usual, you can inquire about the @code{mipsfpu} variable with
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@samp{show mipsfpu}.
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@end table
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@node OpenRISC 1000
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@subsection OpenRISC 1000
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@cindex OpenRISC 1000
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@noindent
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The OpenRISC 1000 provides a free RISC instruction set architecture. It is
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mainly provided as a soft-core which can run on Xilinx, Altera and other
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FPGA's.
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@value{GDBN} for OpenRISC supports the below commands when connecting to
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a target:
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@table @code
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@kindex target sim
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@item target sim
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Runs the builtin CPU simulator which can run very basic
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programs but does not support most hardware functions like MMU.
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For more complex use cases the user is advised to run an external
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target, and connect using @samp{target remote}.
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Example: @code{target sim}
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@item set debug or1k
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Toggle whether to display OpenRISC-specific debugging messages from the
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OpenRISC target support subsystem.
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@item show debug or1k
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Show whether OpenRISC-specific debugging messages are enabled.
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@end table
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@node PowerPC Embedded
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@subsection PowerPC Embedded
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@ -41739,6 +41777,7 @@ registers using the capitalization used in the description.
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* M68K Features::
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* NDS32 Features::
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* Nios II Features::
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* OpenRISC 1000 Features::
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* PowerPC Features::
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* S/390 and System z Features::
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* Sparc Features::
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@ -42025,6 +42064,14 @@ targets. It should contain the 32 core registers (@samp{zero},
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@samp{pc}, and the 16 control registers (@samp{status} through
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@samp{mpuacc}).
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@node OpenRISC 1000 Features
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@subsection Openrisc 1000 Features
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@cindex target descriptions, OpenRISC 1000 features
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The @samp{org.gnu.gdb.or1k.group0} feature is required for OpenRISC 1000
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targets. It should contain the 32 general purpose registers (@samp{r0}
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through @samp{r31}), @samp{ppc}, @samp{npc} and @samp{sr}.
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@node PowerPC Features
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@subsection PowerPC Features
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@cindex target descriptions, PowerPC features
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@ -93,6 +93,7 @@ mips64-expedite = r29,pc
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mips64-dsp-expedite = r29,pc
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microblaze-expedite = r1,rpc
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nios2-linux-expedite = sp,pc
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or1k-expedite = r1,npc
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powerpc-expedite = r1,pc
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rs6000/powerpc-cell32l-expedite = r1,pc,r0,orig_r3,r4
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rs6000/powerpc-cell64l-expedite = r1,pc,r0,orig_r3,r4
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@ -136,6 +137,7 @@ XMLTOC = \
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mips64-linux.xml \
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nds32.xml \
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nios2.xml \
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or1k.xml \
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rs6000/powerpc-32.xml \
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rs6000/powerpc-32l.xml \
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rs6000/powerpc-403.xml \
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65
gdb/features/or1k-core.xml
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65
gdb/features/or1k-core.xml
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@ -0,0 +1,65 @@
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<?xml version="1.0"?>
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<!-- Copyright (C) 2017 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.or1k.group0">
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<reg name="r0" bitsize="32" type="int"/>
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<reg name="r1" bitsize="32" type="data_ptr"/>
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<reg name="r2" bitsize="32" type="data_ptr"/>
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<reg name="r3" bitsize="32" type="int"/>
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<reg name="r4" bitsize="32" type="int"/>
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<reg name="r5" bitsize="32" type="int"/>
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<reg name="r6" bitsize="32" type="int"/>
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<reg name="r7" bitsize="32" type="int"/>
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<reg name="r8" bitsize="32" type="int"/>
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<reg name="r9" bitsize="32" type="code_ptr"/>
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<reg name="r10" bitsize="32" type="int"/>
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<reg name="r11" bitsize="32" type="int"/>
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<reg name="r12" bitsize="32" type="int"/>
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<reg name="r13" bitsize="32" type="int"/>
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<reg name="r14" bitsize="32" type="int"/>
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<reg name="r15" bitsize="32" type="int"/>
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<reg name="r16" bitsize="32" type="int"/>
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<reg name="r17" bitsize="32" type="int"/>
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<reg name="r18" bitsize="32" type="int"/>
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<reg name="r19" bitsize="32" type="int"/>
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<reg name="r20" bitsize="32" type="int"/>
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<reg name="r21" bitsize="32" type="int"/>
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<reg name="r22" bitsize="32" type="int"/>
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<reg name="r23" bitsize="32" type="int"/>
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<reg name="r24" bitsize="32" type="int"/>
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<reg name="r25" bitsize="32" type="int"/>
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<reg name="r26" bitsize="32" type="int"/>
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<reg name="r27" bitsize="32" type="int"/>
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<reg name="r28" bitsize="32" type="int"/>
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<reg name="r29" bitsize="32" type="int"/>
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<reg name="r30" bitsize="32" type="int"/>
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<reg name="r31" bitsize="32" type="int"/>
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<reg name="ppc" bitsize="32" type="code_ptr"/>
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<reg name="npc" bitsize="32" type="code_ptr"/>
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<flags id="sr_flags" size="4">
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<field name="SM" start="0" end="0"/>
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<field name="TEE" start="1" end="1"/>
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<field name="IEE" start="2" end="2"/>
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<field name="DCE" start="3" end="3"/>
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<field name="ICE" start="4" end="4"/>
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<field name="DME" start="5" end="5"/>
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<field name="IME" start="6" end="6"/>
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<field name="LEE" start="7" end="7"/>
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<field name="CE" start="8" end="8"/>
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<field name="F" start="9" end="9"/>
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<field name="CY" start="10" end="10"/>
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<field name="OV" start="11" end="11"/>
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<field name="OVE" start="12" end="12"/>
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<field name="DSX" start="13" end="13"/>
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<field name="EPH" start="14" end="14"/>
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<field name="FO" start="15" end="15"/>
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<field name="SUMRA" start="16" end="16"/>
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<field name="CID" start="28" end="31"/>
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</flags>
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<reg name="sr" bitsize="32" type="sr_flags"/>
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</feature>
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77
gdb/features/or1k.c
Normal file
77
gdb/features/or1k.c
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@ -0,0 +1,77 @@
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/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
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Original: or1k.xml */
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#include "defs.h"
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#include "osabi.h"
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#include "target-descriptions.h"
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struct target_desc *tdesc_or1k;
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static void
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initialize_tdesc_or1k (void)
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{
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struct target_desc *result = allocate_target_description ();
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set_tdesc_architecture (result, bfd_scan_arch ("or1k"));
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struct tdesc_feature *feature;
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feature = tdesc_create_feature (result, "org.gnu.gdb.or1k.group0");
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tdesc_type_with_fields *type_with_fields;
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tdesc_type *field_type;
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type_with_fields = tdesc_create_flags (feature, "sr_flags", 4);
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tdesc_add_flag (type_with_fields, 0, "SM");
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tdesc_add_flag (type_with_fields, 1, "TEE");
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tdesc_add_flag (type_with_fields, 2, "IEE");
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tdesc_add_flag (type_with_fields, 3, "DCE");
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tdesc_add_flag (type_with_fields, 4, "ICE");
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tdesc_add_flag (type_with_fields, 5, "DME");
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tdesc_add_flag (type_with_fields, 6, "IME");
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tdesc_add_flag (type_with_fields, 7, "LEE");
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tdesc_add_flag (type_with_fields, 8, "CE");
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tdesc_add_flag (type_with_fields, 9, "F");
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tdesc_add_flag (type_with_fields, 10, "CY");
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tdesc_add_flag (type_with_fields, 11, "OV");
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tdesc_add_flag (type_with_fields, 12, "OVE");
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tdesc_add_flag (type_with_fields, 13, "DSX");
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tdesc_add_flag (type_with_fields, 14, "EPH");
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tdesc_add_flag (type_with_fields, 15, "FO");
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tdesc_add_flag (type_with_fields, 16, "SUMRA");
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tdesc_add_bitfield (type_with_fields, "CID", 28, 31);
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tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
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tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "data_ptr");
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tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "code_ptr");
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tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "ppc", 32, 1, NULL, 32, "code_ptr");
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tdesc_create_reg (feature, "npc", 33, 1, NULL, 32, "code_ptr");
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tdesc_create_reg (feature, "sr", 34, 1, NULL, 32, "sr_flags");
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tdesc_or1k = result;
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}
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12
gdb/features/or1k.xml
Normal file
12
gdb/features/or1k.xml
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<?xml version="1.0"?>
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<!-- Copyright (C) 2016 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
|
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notice and this notice are preserved. -->
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<!DOCTYPE target SYSTEM "gdb-target.dtd">
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<target>
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<architecture>or1k</architecture>
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<xi:include href="or1k-core.xml"/>
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</target>
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1294
gdb/or1k-tdep.c
Normal file
1294
gdb/or1k-tdep.c
Normal file
File diff suppressed because it is too large
Load Diff
56
gdb/or1k-tdep.h
Normal file
56
gdb/or1k-tdep.h
Normal file
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/* Definitions to target GDB to OpenRISC 1000 32-bit targets.
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Copyright (C) 2008-2017 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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With this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef OR1K_TDEP__H
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#define OR1K_TDEP__H
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#ifndef TARGET_OR1K
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#define TARGET_OR1K
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#endif
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#include "opcodes/or1k-desc.h"
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#include "opcodes/or1k-opc.h"
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/* General Purpose Registers */
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#define OR1K_ZERO_REGNUM 0
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#define OR1K_SP_REGNUM 1
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#define OR1K_FP_REGNUM 2
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#define OR1K_FIRST_ARG_REGNUM 3
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#define OR1K_LAST_ARG_REGNUM 8
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#define OR1K_LR_REGNUM 9
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#define OR1K_FIRST_SAVED_REGNUM 10
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#define OR1K_RV_REGNUM 11
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#define OR1K_PPC_REGNUM (OR1K_MAX_GPR_REGS + 0)
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#define OR1K_NPC_REGNUM (OR1K_MAX_GPR_REGS + 1)
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#define OR1K_SR_REGNUM (OR1K_MAX_GPR_REGS + 2)
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/* Properties of the architecture. GDB mapping of registers is all the GPRs
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and SPRs followed by the PPC, NPC and SR at the end. Red zone is the area
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past the end of the stack reserved for exception handlers etc. */
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#define OR1K_MAX_GPR_REGS 32
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#define OR1K_NUM_PSEUDO_REGS 0
|
||||
#define OR1K_NUM_REGS (OR1K_MAX_GPR_REGS + 3)
|
||||
#define OR1K_STACK_ALIGN 4
|
||||
#define OR1K_INSTLEN 4
|
||||
#define OR1K_INSTBITLEN (OR1K_INSTLEN * 8)
|
||||
#define OR1K_NUM_TAP_RECORDS 8
|
||||
#define OR1K_FRAME_RED_ZONE_SIZE 2536
|
||||
|
||||
#endif /* OR1K_TDEP__H */
|
||||
Loading…
Reference in New Issue
Block a user