Improve -mlfence-after-load
1.Implict load for POP/POPF/POPA/XLATB, no load for Anysize insns 2. Add -mlfence-before-ret=shl/yes, adjust operand size of or/not/shl according to ret's. 3. Issue warning for REP CMPS/SCAS since they would affect control flow behavior. 4. Adjust testcases and documents. gas/Changelog: * config/tc-i386.c (lfence_before_ret_shl): New member. (load_insn_p): implict load for POP/POPA/POPF/XLATB, no load for Anysize insns. (insert_after_load): Issue warning for REP CMPS/SCAS. (insert_before_before): Handle iret, Handle -mlfence-before-ret=shl, Adjust operand size of or/not/shl to ret's, (md_parse_option): Change -mlfence-before-ret=[none|not|or] to -mlfence-before-ret=[none/not/or/shl/yes]. Enable -mlfence-before-ret=shl when -mlfence-beofre-indirect-branch=all and no explict -mlfence-before-ret option. (md_show_usage): Ditto. * doc/c-i386.texi: Ditto. * testsuite/gas/i386/i386.exp: Add new testcases. * testsuite/gas/i386/lfence-load-b.d: New. * testsuite/gas/i386/lfence-load-b.e: New. * testsuite/gas/i386/lfence-load.d: Modified. * testsuite/gas/i386/lfence-load.e: New. * testsuite/gas/i386/lfence-load.s: Modified. * testsuite/gas/i386/lfence-ret-a.d: Modified. * testsuite/gas/i386/lfence-ret-b.d: Modified. * testsuite/gas/i386/lfence-ret-c.d: New. * testsuite/gas/i386/lfence-ret-d.d: New. * testsuite/gas/i386/lfence-ret.s: Modified. * testsuite/gas/i386/x86-64-lfence-load-b.d: New. * testsuite/gas/i386/x86-64-lfence-load.d: Modified. * testsuite/gas/i386/x86-64-lfence-load.s: Modified. * testsuite/gas/i386/x86-64-lfence-ret-a.d: Modified. * testsuite/gas/i386/x86-64-lfence-ret-b.d: Modified. * testsuite/gas/i386/x86-64-lfence-ret-c.d: New. * testsuite/gas/i386/x86-64-lfence-ret-d.d: New * testsuite/gas/i386/x86-64-lfence-ret-e.d: New. * testsuite/gas/i386/x86-64-lfence-ret.e: New. * testsuite/gas/i386/x86-64-lfence-ret.s: New.
This commit is contained in:
liuhongt
parent
ec9c4d8322
commit
a09f656b26
@ -1,3 +1,39 @@
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2020-04-26 Hongtao Liu <hongtao.liu@intel.com
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* config/tc-i386.c (lfence_before_ret_shl): New member.
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(load_insn_p): implict load for POP/POPA/POPF/XLATB, no load
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for Anysize insns.
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(insert_after_load): Issue warning for REP CMPS/SCAS.
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(insert_before_before): Handle iret, Handle
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-mlfence-before-ret=shl, Adjust operand size of or/not/shl to ret's,
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(md_parse_option): Change -mlfence-before-ret=[none|not|or] to
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-mlfence-before-ret=[none/not/or/shl/yes].
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Enable -mlfence-before-ret=shl when
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-mlfence-beofre-indirect-branch=all and no explict -mlfence-before-ret option.
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(md_show_usage): Ditto.
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* doc/c-i386.texi: Ditto.
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* testsuite/gas/i386/i386.exp: Add new testcases.
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* testsuite/gas/i386/lfence-load-b.d: New.
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* testsuite/gas/i386/lfence-load-b.e: New.
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* testsuite/gas/i386/lfence-load.d: Modified.
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* testsuite/gas/i386/lfence-load.e: New.
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* testsuite/gas/i386/lfence-load.s: Modified.
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* testsuite/gas/i386/lfence-ret-a.d: Modified.
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* testsuite/gas/i386/lfence-ret-b.d: Modified.
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* testsuite/gas/i386/lfence-ret-c.d: New.
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* testsuite/gas/i386/lfence-ret-d.d: New.
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* testsuite/gas/i386/lfence-ret.s: Modified.
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* testsuite/gas/i386/x86-64-lfence-load-b.d: New.
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* testsuite/gas/i386/x86-64-lfence-load.d: Modified.
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* testsuite/gas/i386/x86-64-lfence-load.s: Modified.
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* testsuite/gas/i386/x86-64-lfence-ret-a.d: Modified.
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* testsuite/gas/i386/x86-64-lfence-ret-b.d: Modified.
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* testsuite/gas/i386/x86-64-lfence-ret-c.d: New.
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* testsuite/gas/i386/x86-64-lfence-ret-d.d: New
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* testsuite/gas/i386/x86-64-lfence-ret-e.d: New.
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* testsuite/gas/i386/x86-64-lfence-ret.e: New.
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* testsuite/gas/i386/x86-64-lfence-ret.s: New.
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2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
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2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
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PR ld/25861
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PR ld/25861
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@ -647,7 +647,8 @@ static enum lfence_before_ret_kind
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{
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{
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lfence_before_ret_none = 0,
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lfence_before_ret_none = 0,
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lfence_before_ret_not,
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lfence_before_ret_not,
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lfence_before_ret_or
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lfence_before_ret_or,
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lfence_before_ret_shl
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}
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}
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lfence_before_ret;
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lfence_before_ret;
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@ -4350,22 +4351,28 @@ load_insn_p (void)
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if (!any_vex_p)
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if (!any_vex_p)
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{
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{
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/* lea */
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/* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
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if (i.tm.base_opcode == 0x8d)
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prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
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bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
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if (i.tm.opcode_modifier.anysize)
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return 0;
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return 0;
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/* pop */
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/* pop, popf, popa. */
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if ((i.tm.base_opcode & ~7) == 0x58
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if (strcmp (i.tm.name, "pop") == 0
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|| (i.tm.base_opcode == 0x8f && i.tm.extension_opcode == 0))
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|| i.tm.base_opcode == 0x9d
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|| i.tm.base_opcode == 0x61)
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return 1;
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return 1;
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/* movs, cmps, lods, scas. */
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/* movs, cmps, lods, scas. */
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if ((i.tm.base_opcode | 0xb) == 0xaf)
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if ((i.tm.base_opcode | 0xb) == 0xaf)
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return 1;
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return 1;
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/* outs */
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/* outs, xlatb. */
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if (base_opcode == 0x6f)
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if (base_opcode == 0x6f
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|| i.tm.base_opcode == 0xd7)
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return 1;
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return 1;
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/* NB: For AMD-specific insns with implicit memory operands,
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they're intentionally not covered. */
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}
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}
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/* No memory operand. */
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/* No memory operand. */
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@ -4506,6 +4513,22 @@ insert_lfence_after (void)
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{
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{
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if (lfence_after_load && load_insn_p ())
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if (lfence_after_load && load_insn_p ())
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{
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{
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/* There are also two REP string instructions that require
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special treatment. Specifically, the compare string (CMPS)
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and scan string (SCAS) instructions set EFLAGS in a manner
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that depends on the data being compared/scanned. When used
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with a REP prefix, the number of iterations may therefore
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vary depending on this data. If the data is a program secret
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chosen by the adversary using an LVI method,
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then this data-dependent behavior may leak some aspect
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of the secret. */
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if (((i.tm.base_opcode | 0x1) == 0xa7
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|| (i.tm.base_opcode | 0x1) == 0xaf)
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&& i.prefix[REP_PREFIX])
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{
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as_warn (_("`%s` changes flags which would affect control flow behavior"),
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i.tm.name);
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}
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char *p = frag_more (3);
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char *p = frag_more (3);
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*p++ = 0xf;
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*p++ = 0xf;
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*p++ = 0xae;
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*p++ = 0xae;
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@ -4568,12 +4591,13 @@ insert_lfence_before (void)
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return;
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return;
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}
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}
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/* Output or/not and lfence before ret. */
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/* Output or/not/shl and lfence before ret/lret/iret. */
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if (lfence_before_ret != lfence_before_ret_none
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if (lfence_before_ret != lfence_before_ret_none
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&& (i.tm.base_opcode == 0xc2
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&& (i.tm.base_opcode == 0xc2
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|| i.tm.base_opcode == 0xc3
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|| i.tm.base_opcode == 0xc3
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|| i.tm.base_opcode == 0xca
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|| i.tm.base_opcode == 0xca
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|| i.tm.base_opcode == 0xcb))
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|| i.tm.base_opcode == 0xcb
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|| i.tm.base_opcode == 0xcf))
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{
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{
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if (last_insn.kind != last_insn_other
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if (last_insn.kind != last_insn_other
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&& last_insn.seg == now_seg)
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&& last_insn.seg == now_seg)
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@ -4583,33 +4607,59 @@ insert_lfence_before (void)
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last_insn.name, i.tm.name);
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last_insn.name, i.tm.name);
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return;
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return;
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}
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}
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if (lfence_before_ret == lfence_before_ret_or)
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/* lret or iret. */
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bfd_boolean lret = (i.tm.base_opcode | 0x5) == 0xcf;
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bfd_boolean has_rexw = i.prefix[REX_PREFIX] & REX_W;
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char prefix = 0x0;
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/* Default operand size for far return is 32 bits,
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64 bits for near return. */
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/* Near ret ingore operand size override under CPU64. */
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if ((!lret && flag_code == CODE_64BIT) || has_rexw)
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prefix = 0x48;
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else if (i.prefix[DATA_PREFIX])
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prefix = 0x66;
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if (lfence_before_ret == lfence_before_ret_not)
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{
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{
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/* orl: 0x830c2400. */
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/* not: 0xf71424, may add prefix
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p = frag_more ((flag_code == CODE_64BIT ? 1 : 0) + 4 + 3);
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for operand size override or 64-bit code. */
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if (flag_code == CODE_64BIT)
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p = frag_more ((prefix ? 2 : 0) + 6 + 3);
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*p++ = 0x48;
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if (prefix)
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*p++ = 0x83;
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*p++ = prefix;
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*p++ = 0xc;
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*p++ = 0xf7;
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*p++ = 0x14;
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*p++ = 0x24;
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if (prefix)
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*p++ = prefix;
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*p++ = 0xf7;
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*p++ = 0x14;
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*p++ = 0x24;
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*p++ = 0x24;
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*p++ = 0x0;
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}
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}
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else
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else
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{
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{
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p = frag_more ((flag_code == CODE_64BIT ? 2 : 0) + 6 + 3);
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p = frag_more ((prefix ? 1 : 0) + 4 + 3);
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/* notl: 0xf71424. */
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if (prefix)
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if (flag_code == CODE_64BIT)
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*p++ = prefix;
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*p++ = 0x48;
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if (lfence_before_ret == lfence_before_ret_or)
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*p++ = 0xf7;
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{
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*p++ = 0x14;
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/* or: 0x830c2400, may add prefix
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*p++ = 0x24;
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for operand size override or 64-bit code. */
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/* notl: 0xf71424. */
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*p++ = 0x83;
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if (flag_code == CODE_64BIT)
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*p++ = 0x0c;
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*p++ = 0x48;
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}
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*p++ = 0xf7;
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else
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*p++ = 0x14;
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{
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/* shl: 0xc1242400, may add prefix
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for operand size override or 64-bit code. */
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*p++ = 0xc1;
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*p++ = 0x24;
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}
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*p++ = 0x24;
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*p++ = 0x24;
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*p++ = 0x0;
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}
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}
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*p++ = 0xf;
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*p++ = 0xf;
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*p++ = 0xae;
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*p++ = 0xae;
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*p = 0xe8;
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*p = 0xe8;
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@ -12995,7 +13045,11 @@ md_parse_option (int c, const char *arg)
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case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH:
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case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH:
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if (strcasecmp (arg, "all") == 0)
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if (strcasecmp (arg, "all") == 0)
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lfence_before_indirect_branch = lfence_branch_all;
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{
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lfence_before_indirect_branch = lfence_branch_all;
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if (lfence_before_ret == lfence_before_ret_none)
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lfence_before_ret = lfence_before_ret_shl;
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}
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else if (strcasecmp (arg, "memory") == 0)
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else if (strcasecmp (arg, "memory") == 0)
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lfence_before_indirect_branch = lfence_branch_memory;
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lfence_before_indirect_branch = lfence_branch_memory;
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else if (strcasecmp (arg, "register") == 0)
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else if (strcasecmp (arg, "register") == 0)
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@ -13012,6 +13066,8 @@ md_parse_option (int c, const char *arg)
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lfence_before_ret = lfence_before_ret_or;
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lfence_before_ret = lfence_before_ret_or;
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else if (strcasecmp (arg, "not") == 0)
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else if (strcasecmp (arg, "not") == 0)
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lfence_before_ret = lfence_before_ret_not;
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lfence_before_ret = lfence_before_ret_not;
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else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0)
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lfence_before_ret = lfence_before_ret_shl;
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else if (strcasecmp (arg, "none") == 0)
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else if (strcasecmp (arg, "none") == 0)
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lfence_before_ret = lfence_before_ret_none;
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lfence_before_ret = lfence_before_ret_none;
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else
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else
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@ -13382,7 +13438,7 @@ md_show_usage (FILE *stream)
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-mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
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-mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
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generate lfence before indirect near branch\n"));
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generate lfence before indirect near branch\n"));
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fprintf (stream, _("\
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fprintf (stream, _("\
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-mlfence-before-ret=[none|or|not] (default: none)\n\
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-mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
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generate lfence before ret\n"));
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generate lfence before ret\n"));
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fprintf (stream, _("\
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fprintf (stream, _("\
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-mamd64 accept only AMD64 ISA [default]\n"));
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-mamd64 accept only AMD64 ISA [default]\n"));
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@ -488,6 +488,8 @@ before indirect near branch instructions.
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@option{-mlfence-before-indirect-branch=@var{all}} will generate lfence
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@option{-mlfence-before-indirect-branch=@var{all}} will generate lfence
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before indirect near branch via register and issue a warning before
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before indirect near branch via register and issue a warning before
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indirect near branch via memory.
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indirect near branch via memory.
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It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when
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there's no explict @option{-mlfence-before-ret=}.
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@option{-mlfence-before-indirect-branch=@var{register}} will generate
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@option{-mlfence-before-indirect-branch=@var{register}} will generate
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lfence before indirect near branch via register.
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lfence before indirect near branch via register.
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@option{-mlfence-before-indirect-branch=@var{memory}} will issue a
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@option{-mlfence-before-indirect-branch=@var{memory}} will issue a
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@ -501,15 +503,17 @@ after loading branch target register.
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@cindex @samp{-mlfence-before-ret=} option, i386
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@cindex @samp{-mlfence-before-ret=} option, i386
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@cindex @samp{-mlfence-before-ret=} option, x86-64
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@cindex @samp{-mlfence-before-ret=} option, x86-64
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@item -mlfence-before-ret=@var{none}
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@item -mlfence-before-ret=@var{none}
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@item -mlfence-before-ret=@var{shl}
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@item -mlfence-before-ret=@var{or}
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@item -mlfence-before-ret=@var{or}
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@item -mlfence-before-ret=@var{yes}
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@itemx -mlfence-before-ret=@var{not}
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@itemx -mlfence-before-ret=@var{not}
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These options control whether the assembler should generate lfence
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These options control whether the assembler should generate lfence
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before ret. @option{-mlfence-before-ret=@var{or}} will generate
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before ret. @option{-mlfence-before-ret=@var{or}} will generate
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generate or instruction with lfence.
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generate or instruction with lfence.
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@option{-mlfence-before-ret=@var{not}} will generate not instruction
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@option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction
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with lfence.
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with lfence. @option{-mlfence-before-ret=@var{not}} will generate not
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@option{-mlfence-before-ret=@var{none}} will not generate lfence,
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instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not
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which is the default.
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generate lfence, which is the default.
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@cindex @samp{-mx86-used-note=} option, i386
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@cindex @samp{-mx86-used-note=} option, i386
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@cindex @samp{-mx86-used-note=} option, x86-64
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@cindex @samp{-mx86-used-note=} option, x86-64
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|
|||||||
@ -535,6 +535,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||||||
run_dump_test "lfence-indbr-c"
|
run_dump_test "lfence-indbr-c"
|
||||||
run_dump_test "lfence-ret-a"
|
run_dump_test "lfence-ret-a"
|
||||||
run_dump_test "lfence-ret-b"
|
run_dump_test "lfence-ret-b"
|
||||||
|
run_dump_test "lfence-ret-c"
|
||||||
|
run_dump_test "lfence-ret-d"
|
||||||
run_dump_test "lfence-byte"
|
run_dump_test "lfence-byte"
|
||||||
|
|
||||||
# These tests require support for 8 and 16 bit relocs,
|
# These tests require support for 8 and 16 bit relocs,
|
||||||
@ -1122,6 +1124,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||||||
run_dump_test "x86-64-lfence-indbr-c"
|
run_dump_test "x86-64-lfence-indbr-c"
|
||||||
run_dump_test "x86-64-lfence-ret-a"
|
run_dump_test "x86-64-lfence-ret-a"
|
||||||
run_dump_test "x86-64-lfence-ret-b"
|
run_dump_test "x86-64-lfence-ret-b"
|
||||||
|
run_dump_test "x86-64-lfence-ret-c"
|
||||||
|
run_dump_test "x86-64-lfence-ret-d"
|
||||||
|
run_dump_test "x86-64-lfence-ret-e"
|
||||||
run_dump_test "x86-64-lfence-byte"
|
run_dump_test "x86-64-lfence-byte"
|
||||||
|
|
||||||
if { ![istarget "*-*-aix*"]
|
if { ![istarget "*-*-aix*"]
|
||||||
|
|||||||
@ -1,5 +1,6 @@
|
|||||||
#as: -mlfence-after-load=yes
|
#as: -mlfence-after-load=yes
|
||||||
#objdump: -dw
|
#objdump: -dw
|
||||||
|
#warning_output: lfence-load.e
|
||||||
#name: -mlfence-after-load=yes
|
#name: -mlfence-after-load=yes
|
||||||
|
|
||||||
.*: +file format .*
|
.*: +file format .*
|
||||||
@ -15,6 +16,31 @@ Disassembly of section .text:
|
|||||||
+[a-f0-9]+: 0f c7 75 00 vmptrld 0x0\(%ebp\)
|
+[a-f0-9]+: 0f c7 75 00 vmptrld 0x0\(%ebp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
+[a-f0-9]+: 66 0f c7 75 00 vmclear 0x0\(%ebp\)
|
+[a-f0-9]+: 66 0f c7 75 00 vmclear 0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: 66 0f 38 82 55 00 invpcid 0x0\(%ebp\),%edx
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 0f 01 7d 00 invlpg 0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: 0f ae 7d 00 clflush 0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: 66 0f ae 7d 00 clflushopt 0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: 66 0f ae 75 00 clwb 0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: 0f 1c 45 00 cldemote 0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: f3 0f 1b 4d 00 bndmk 0x0\(%ebp\),%bnd1
|
||||||
|
+[a-f0-9]+: f3 0f 1a 4d 00 bndcl 0x0\(%ebp\),%bnd1
|
||||||
|
+[a-f0-9]+: f2 0f 1a 4d 00 bndcu 0x0\(%ebp\),%bnd1
|
||||||
|
+[a-f0-9]+: f2 0f 1b 4d 00 bndcn 0x0\(%ebp\),%bnd1
|
||||||
|
+[a-f0-9]+: 0f 1b 4d 00 bndstx %bnd1,0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: 0f 1a 4d 00 bndldx 0x0\(%ebp\),%bnd1
|
||||||
|
+[a-f0-9]+: 0f 18 4d 00 prefetcht0 0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%ebp\)
|
||||||
|
+[a-f0-9]+: 1f pop %ds
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 9d popf
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 61 popa
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: d7 xlat %ds:\(%ebx\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
+[a-f0-9]+: d9 55 00 fsts 0x0\(%ebp\)
|
+[a-f0-9]+: d9 55 00 fsts 0x0\(%ebp\)
|
||||||
+[a-f0-9]+: d9 45 00 flds 0x0\(%ebp\)
|
+[a-f0-9]+: d9 45 00 flds 0x0\(%ebp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
|||||||
3
gas/testsuite/gas/i386/lfence-load.e
Normal file
3
gas/testsuite/gas/i386/lfence-load.e
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
.*: Assembler messages:
|
||||||
|
.*:??: Warning: `scas` changes flags which would affect control flow behavior
|
||||||
|
.*:??: Warning: `cmps` changes flags which would affect control flow behavior
|
||||||
@ -4,6 +4,26 @@ _start:
|
|||||||
lgdt (%ebp)
|
lgdt (%ebp)
|
||||||
vmptrld (%ebp)
|
vmptrld (%ebp)
|
||||||
vmclear (%ebp)
|
vmclear (%ebp)
|
||||||
|
invpcid (%ebp), %edx
|
||||||
|
invlpg (%ebp)
|
||||||
|
clflush (%ebp)
|
||||||
|
clflushopt (%ebp)
|
||||||
|
clwb (%ebp)
|
||||||
|
cldemote (%ebp)
|
||||||
|
bndmk (%ebp), %bnd1
|
||||||
|
bndcl (%ebp), %bnd1
|
||||||
|
bndcu (%ebp), %bnd1
|
||||||
|
bndcn (%ebp), %bnd1
|
||||||
|
bndstx %bnd1, (%ebp)
|
||||||
|
bndldx (%ebp), %bnd1
|
||||||
|
prefetcht0 (%ebp)
|
||||||
|
prefetcht1 (%ebp)
|
||||||
|
prefetcht2 (%ebp)
|
||||||
|
prefetchw (%ebp)
|
||||||
|
pop %ds
|
||||||
|
popf
|
||||||
|
popa
|
||||||
|
xlatb (%ebx)
|
||||||
fsts (%ebp)
|
fsts (%ebp)
|
||||||
flds (%ebp)
|
flds (%ebp)
|
||||||
fistl (%ebp)
|
fistl (%ebp)
|
||||||
|
|||||||
@ -9,10 +9,28 @@
|
|||||||
Disassembly of section .text:
|
Disassembly of section .text:
|
||||||
|
|
||||||
0+ <_start>:
|
0+ <_start>:
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c3 retw
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c2 14 00 retw \$0x14
|
||||||
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
+[a-f0-9]+: c3 ret
|
+[a-f0-9]+: c3 ret
|
||||||
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
+[a-f0-9]+: c2 1e 00 ret \$0x1e
|
+[a-f0-9]+: c2 1e 00 ret \$0x1e
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 cb lretw
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
|
||||||
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: cb lret
|
||||||
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: ca 28 00 lret \$0x28
|
||||||
#pass
|
#pass
|
||||||
|
|||||||
@ -9,6 +9,14 @@
|
|||||||
Disassembly of section .text:
|
Disassembly of section .text:
|
||||||
|
|
||||||
0+ <_start>:
|
0+ <_start>:
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c3 retw
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c2 14 00 retw \$0x14
|
||||||
+[a-f0-9]+: f7 14 24 notl \(%esp\)
|
+[a-f0-9]+: f7 14 24 notl \(%esp\)
|
||||||
+[a-f0-9]+: f7 14 24 notl \(%esp\)
|
+[a-f0-9]+: f7 14 24 notl \(%esp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
@ -17,4 +25,20 @@ Disassembly of section .text:
|
|||||||
+[a-f0-9]+: f7 14 24 notl \(%esp\)
|
+[a-f0-9]+: f7 14 24 notl \(%esp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
+[a-f0-9]+: c2 1e 00 ret \$0x1e
|
+[a-f0-9]+: c2 1e 00 ret \$0x1e
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 cb lretw
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
|
||||||
|
+[a-f0-9]+: f7 14 24 notl \(%esp\)
|
||||||
|
+[a-f0-9]+: f7 14 24 notl \(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: cb lret
|
||||||
|
+[a-f0-9]+: f7 14 24 notl \(%esp\)
|
||||||
|
+[a-f0-9]+: f7 14 24 notl \(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: ca 28 00 lret \$0x28
|
||||||
#pass
|
#pass
|
||||||
|
|||||||
35
gas/testsuite/gas/i386/lfence-ret-c.d
Normal file
35
gas/testsuite/gas/i386/lfence-ret-c.d
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
#source: lfence-ret.s
|
||||||
|
#as: -mlfence-before-ret=or -mlfence-before-indirect-branch=all
|
||||||
|
#objdump: -dw
|
||||||
|
|
||||||
|
.*: +file format .*
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section .text:
|
||||||
|
|
||||||
|
0+ <_start>:
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c3 retw
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c2 14 00 retw \$0x14
|
||||||
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: c3 ret
|
||||||
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: c2 1e 00 ret \$0x1e
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 cb lretw
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
|
||||||
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: cb lret
|
||||||
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: ca 28 00 lret \$0x28
|
||||||
|
#pass
|
||||||
36
gas/testsuite/gas/i386/lfence-ret-d.d
Normal file
36
gas/testsuite/gas/i386/lfence-ret-d.d
Normal file
@ -0,0 +1,36 @@
|
|||||||
|
#source: lfence-ret.s
|
||||||
|
#as: -mlfence-before-ret=shl
|
||||||
|
#objdump: -dw
|
||||||
|
#name: -mlfence-before-ret=shl
|
||||||
|
|
||||||
|
.*: +file format .*
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section .text:
|
||||||
|
|
||||||
|
0+ <_start>:
|
||||||
|
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c3 retw
|
||||||
|
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c2 14 00 retw \$0x14
|
||||||
|
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: c3 ret
|
||||||
|
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: c2 1e 00 ret \$0x1e
|
||||||
|
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 cb lretw
|
||||||
|
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
|
||||||
|
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: cb lret
|
||||||
|
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%esp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: ca 28 00 lret \$0x28
|
||||||
|
#pass
|
||||||
@ -1,4 +1,10 @@
|
|||||||
.text
|
.text
|
||||||
_start:
|
_start:
|
||||||
|
retw
|
||||||
|
retw $20
|
||||||
ret
|
ret
|
||||||
ret $30
|
ret $30
|
||||||
|
lretw
|
||||||
|
lretw $40
|
||||||
|
lret
|
||||||
|
lret $40
|
||||||
|
|||||||
@ -1,5 +1,6 @@
|
|||||||
#as: -mlfence-after-load=yes
|
#as: -mlfence-after-load=yes
|
||||||
#objdump: -dw
|
#objdump: -dw
|
||||||
|
#warning_output: lfence-load.e
|
||||||
#name: x86-64 -mlfence-after-load=yes
|
#name: x86-64 -mlfence-after-load=yes
|
||||||
|
|
||||||
.*: +file format .*
|
.*: +file format .*
|
||||||
@ -15,6 +16,29 @@ Disassembly of section .text:
|
|||||||
+[a-f0-9]+: 0f c7 75 00 vmptrld 0x0\(%rbp\)
|
+[a-f0-9]+: 0f c7 75 00 vmptrld 0x0\(%rbp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
+[a-f0-9]+: 66 0f c7 75 00 vmclear 0x0\(%rbp\)
|
+[a-f0-9]+: 66 0f c7 75 00 vmclear 0x0\(%rbp\)
|
||||||
|
+[a-f0-9]+: 66 0f 38 82 55 00 invpcid 0x0\(%rbp\),%rdx
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 67 0f 01 38 invlpg \(%eax\)
|
||||||
|
+[a-f0-9]+: 0f ae 7d 00 clflush 0x0\(%rbp\)
|
||||||
|
+[a-f0-9]+: 66 0f ae 7d 00 clflushopt 0x0\(%rbp\)
|
||||||
|
+[a-f0-9]+: 66 0f ae 75 00 clwb 0x0\(%rbp\)
|
||||||
|
+[a-f0-9]+: 0f 1c 45 00 cldemote 0x0\(%rbp\)
|
||||||
|
+[a-f0-9]+: f3 0f 1b 4d 00 bndmk 0x0\(%rbp\),%bnd1
|
||||||
|
+[a-f0-9]+: f3 0f 1a 4d 00 bndcl 0x0\(%rbp\),%bnd1
|
||||||
|
+[a-f0-9]+: f2 0f 1a 4d 00 bndcu 0x0\(%rbp\),%bnd1
|
||||||
|
+[a-f0-9]+: f2 0f 1b 4d 00 bndcn 0x0\(%rbp\),%bnd1
|
||||||
|
+[a-f0-9]+: 0f 1b 4d 00 bndstx %bnd1,0x0\(%rbp\)
|
||||||
|
+[a-f0-9]+: 0f 1a 4d 00 bndldx 0x0\(%rbp\),%bnd1
|
||||||
|
+[a-f0-9]+: 0f 18 4d 00 prefetcht0 0x0\(%rbp\)
|
||||||
|
+[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%rbp\)
|
||||||
|
+[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%rbp\)
|
||||||
|
+[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\)
|
||||||
|
+[a-f0-9]+: 0f a1 popq %fs
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 9d popfq
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: d7 xlat %ds:\(%rbx\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
+[a-f0-9]+: d9 55 00 fsts 0x0\(%rbp\)
|
+[a-f0-9]+: d9 55 00 fsts 0x0\(%rbp\)
|
||||||
+[a-f0-9]+: d9 45 00 flds 0x0\(%rbp\)
|
+[a-f0-9]+: d9 45 00 flds 0x0\(%rbp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
|||||||
@ -4,6 +4,25 @@ _start:
|
|||||||
lgdt (%rbp)
|
lgdt (%rbp)
|
||||||
vmptrld (%rbp)
|
vmptrld (%rbp)
|
||||||
vmclear (%rbp)
|
vmclear (%rbp)
|
||||||
|
invpcid (%rbp), %rdx
|
||||||
|
invlpg (%eax)
|
||||||
|
clflush (%rbp)
|
||||||
|
clflushopt (%rbp)
|
||||||
|
clwb (%rbp)
|
||||||
|
cldemote (%rbp)
|
||||||
|
bndmk (%rbp), %bnd1
|
||||||
|
bndcl (%rbp), %bnd1
|
||||||
|
bndcu (%rbp), %bnd1
|
||||||
|
bndcn (%rbp), %bnd1
|
||||||
|
bndstx %bnd1, (%rbp)
|
||||||
|
bndldx (%rbp), %bnd1
|
||||||
|
prefetcht0 (%rbp)
|
||||||
|
prefetcht1 (%rbp)
|
||||||
|
prefetcht2 (%rbp)
|
||||||
|
prefetchw (%rbp)
|
||||||
|
pop %fs
|
||||||
|
popf
|
||||||
|
xlatb (%rbx)
|
||||||
fsts (%rbp)
|
fsts (%rbp)
|
||||||
flds (%rbp)
|
flds (%rbp)
|
||||||
fistl (%rbp)
|
fistl (%rbp)
|
||||||
|
|||||||
@ -1,6 +1,7 @@
|
|||||||
#source: lfence-ret.s
|
#source: x86-64-lfence-ret.s
|
||||||
#as: -mlfence-before-ret=or
|
#as: -mlfence-before-ret=or
|
||||||
#objdump: -dw
|
#warning_output: x86-64-lfence-ret.e
|
||||||
|
#objdump: -dw -Mintel64
|
||||||
#name: x86-64 -mlfence-before-ret=or
|
#name: x86-64 -mlfence-before-ret=or
|
||||||
|
|
||||||
.*: +file format .*
|
.*: +file format .*
|
||||||
@ -9,10 +10,40 @@
|
|||||||
Disassembly of section .text:
|
Disassembly of section .text:
|
||||||
|
|
||||||
0+ <_start>:
|
0+ <_start>:
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c3 data16 retq
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c2 14 00 data16 retq \$0x14
|
||||||
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
+[a-f0-9]+: c3 retq
|
+[a-f0-9]+: c3 retq
|
||||||
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
+[a-f0-9]+: c2 1e 00 retq \$0x1e
|
+[a-f0-9]+: c2 1e 00 retq \$0x1e
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 48 c3 data16 rex.W retq
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 cb lretw
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
|
||||||
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: cb lret
|
||||||
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: ca 28 00 lret \$0x28
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 48 cb lretq
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
|
||||||
#pass
|
#pass
|
||||||
|
|||||||
@ -1,6 +1,7 @@
|
|||||||
#source: lfence-ret.s
|
#source: x86-64-lfence-ret.s
|
||||||
#as: -mlfence-before-ret=not
|
#as: -mlfence-before-ret=not
|
||||||
#objdump: -dw
|
#warning_output: x86-64-lfence-ret.e
|
||||||
|
#objdump: -dw -Mintel64
|
||||||
#name: x86-64 -mlfence-before-ret=not
|
#name: x86-64 -mlfence-before-ret=not
|
||||||
|
|
||||||
.*: +file format .*
|
.*: +file format .*
|
||||||
@ -9,6 +10,14 @@
|
|||||||
Disassembly of section .text:
|
Disassembly of section .text:
|
||||||
|
|
||||||
0+ <_start>:
|
0+ <_start>:
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c3 data16 retq
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c2 14 00 data16 retq \$0x14
|
||||||
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
@ -17,4 +26,36 @@ Disassembly of section .text:
|
|||||||
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
+[a-f0-9]+: 0f ae e8 lfence
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
+[a-f0-9]+: c2 1e 00 retq \$0x1e
|
+[a-f0-9]+: c2 1e 00 retq \$0x1e
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 48 c3 data16 rex.W retq
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 cb lretw
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
|
||||||
|
+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
|
||||||
|
+[a-f0-9]+: f7 14 24 notl \(%rsp\)
|
||||||
|
+[a-f0-9]+: f7 14 24 notl \(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: cb lret
|
||||||
|
+[a-f0-9]+: f7 14 24 notl \(%rsp\)
|
||||||
|
+[a-f0-9]+: f7 14 24 notl \(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: ca 28 00 lret \$0x28
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 48 cb lretq
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
|
||||||
#pass
|
#pass
|
||||||
|
|||||||
48
gas/testsuite/gas/i386/x86-64-lfence-ret-c.d
Normal file
48
gas/testsuite/gas/i386/x86-64-lfence-ret-c.d
Normal file
@ -0,0 +1,48 @@
|
|||||||
|
#source: x86-64-lfence-ret.s
|
||||||
|
#as: -mlfence-before-ret=or -mlfence-before-indirect-branch=all
|
||||||
|
#warning_output: x86-64-lfence-ret.e
|
||||||
|
#objdump: -dw -Mintel64
|
||||||
|
|
||||||
|
.*: +file format .*
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section .text:
|
||||||
|
|
||||||
|
0+ <_start>:
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c3 data16 retq
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c2 14 00 data16 retq \$0x14
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: c3 retq
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: c2 1e 00 retq \$0x1e
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 48 c3 data16 rex.W retq
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 cb lretw
|
||||||
|
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
|
||||||
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: cb lret
|
||||||
|
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: ca 28 00 lret \$0x28
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 48 cb lretq
|
||||||
|
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
|
||||||
|
#pass
|
||||||
49
gas/testsuite/gas/i386/x86-64-lfence-ret-d.d
Normal file
49
gas/testsuite/gas/i386/x86-64-lfence-ret-d.d
Normal file
@ -0,0 +1,49 @@
|
|||||||
|
#source: x86-64-lfence-ret.s
|
||||||
|
#as: -mlfence-before-ret=shl
|
||||||
|
#warning_output: x86-64-lfence-ret.e
|
||||||
|
#objdump: -dw -Mintel64
|
||||||
|
#name: x86-64 -mlfence-before-ret=shl
|
||||||
|
|
||||||
|
.*: +file format .*
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section .text:
|
||||||
|
|
||||||
|
0+ <_start>:
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c3 data16 retq
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c2 14 00 data16 retq \$0x14
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: c3 retq
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: c2 1e 00 retq \$0x1e
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 48 c3 data16 rex.W retq
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
|
||||||
|
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 cb lretw
|
||||||
|
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
|
||||||
|
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: cb lret
|
||||||
|
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: ca 28 00 lret \$0x28
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 48 cb lretq
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
|
||||||
|
#pass
|
||||||
49
gas/testsuite/gas/i386/x86-64-lfence-ret-e.d
Normal file
49
gas/testsuite/gas/i386/x86-64-lfence-ret-e.d
Normal file
@ -0,0 +1,49 @@
|
|||||||
|
#source: x86-64-lfence-ret.s
|
||||||
|
#as: -mlfence-before-ret=shl
|
||||||
|
#warning_output: x86-64-lfence-ret.e
|
||||||
|
#objdump: -dw -Mintel64
|
||||||
|
#name: x86-64 -mlfence-before-ret=yes
|
||||||
|
|
||||||
|
.*: +file format .*
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section .text:
|
||||||
|
|
||||||
|
0+ <_start>:
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c3 data16 retq
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 c2 14 00 data16 retq \$0x14
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: c3 retq
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: c2 1e 00 retq \$0x1e
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 48 c3 data16 rex.W retq
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
|
||||||
|
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 cb lretw
|
||||||
|
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
|
||||||
|
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: cb lret
|
||||||
|
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: ca 28 00 lret \$0x28
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 48 cb lretq
|
||||||
|
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||||
|
+[a-f0-9]+: 0f ae e8 lfence
|
||||||
|
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
|
||||||
|
#pass
|
||||||
3
gas/testsuite/gas/i386/x86-64-lfence-ret.e
Normal file
3
gas/testsuite/gas/i386/x86-64-lfence-ret.e
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
.*: Assembler messages:
|
||||||
|
.*:??: Warning: no instruction mnemonic suffix given and no register operands; using default for `lret'
|
||||||
|
.*:??: Warning: no instruction mnemonic suffix given and no register operands; using default for `lret'
|
||||||
14
gas/testsuite/gas/i386/x86-64-lfence-ret.s
Normal file
14
gas/testsuite/gas/i386/x86-64-lfence-ret.s
Normal file
@ -0,0 +1,14 @@
|
|||||||
|
.text
|
||||||
|
_start:
|
||||||
|
retw
|
||||||
|
retw $20
|
||||||
|
ret
|
||||||
|
ret $30
|
||||||
|
data16 rex.w ret
|
||||||
|
data16 rex.w ret $40
|
||||||
|
lretw
|
||||||
|
lretw $40
|
||||||
|
lret
|
||||||
|
lret $40
|
||||||
|
lretq
|
||||||
|
lretq $40
|
||||||
Loading…
Reference in New Issue
Block a user