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x86-64: optimize certain commutative VEX-encoded insns

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When they're in the 0F opcode space, swapping their source operands may
allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN
behavior precludes us doing so for many packed and scalar floating point
insns; such an optimization would need to be done by the compiler
instead in this case, when it knows that NaN-s have undefined behavior
anyway.

While for explicitly specified AVX/AVX2 insns the optimization (for now
at least) gets done only for -O2 and -Os, it is utilized by default in
SSE2AVX mode, as there we're re-writing the programmer's specified insns
anyway.

Rather than introducing a new attribute flag, the change re-uses one
which so far was meaningful only for EVEX-encoded insns.
This commit is contained in:
Jan Beulich 2019-07-01 08:33:56 +02:00
parent a80195f122
commit 79dec6b7ba
17 changed files with 1419 additions and 1580 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
gas/ChangeLog
View File

@ -1,3 +1,23 @@
2019-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (commutative): New.
(build_vex_prefix): Handle commutative case.
(optimize_encoding): Set commutative flag when appropriate.
* doc/c-i386.texi: Update -O2 documentation.
* testsuite/gas/i386/ilp32/x86-64-sse2avx.d: Re-use parent dir
output.
* testsuite/gas/i386/x86-64-sse2avx.s: Add tests with high
numbered source operands.
* testsuite/gas/i386/x86-64-optimize-2.d,
testsuite/gas/i386/x86-64-optimize-2b.d,
testsuite/gas/i386/x86-64-optimize-3.d,
testsuite/gas/i386/x86-64-optimize-5.d,
testsuite/gas/i386/x86-64-optimize-6.d,
testsuite/gas/i386/x86-64-sse2avx.d: Adjust expectations.
* testsuite/gas/i386/x86-64-avx-swap-2.d,
testsuite/gas/i386/x86-64-avx-swap-2.s: New.
* testsuite/gas/i386/i386.exp: Run new test.
2019-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (is_evex_encoding): Don't check for SAE.

43
gas/config/tc-i386.c
View File

@ -98,6 +98,9 @@
#define END_OF_INSN '\0'
/* This matches the C -> StaticRounding alias in the opcode table. */
#define commutative staticrounding
/*
'templates' is for grouping together 'template' structures for opcodes
of the same name. This is only used for storing the insns in the grand
@ -3438,6 +3441,43 @@ build_vex_prefix (const insn_template *t)
i.tm = t[1];
}
/* Use 2-byte VEX prefix by swapping commutative source operands if there
are no memory operands and at least 3 register ones. */
if (i.reg_operands >= 3
&& i.vec_encoding != vex_encoding_vex3
&& i.reg_operands == i.operands - i.imm_operands
&& i.tm.opcode_modifier.vex
&& i.tm.opcode_modifier.commutative
&& (i.tm.opcode_modifier.sse2avx || optimize > 1)
&& i.rex == REX_B
&& i.vex.register_specifier
&& !(i.vex.register_specifier->reg_flags & RegRex))
{
unsigned int xchg = i.operands - i.reg_operands;
union i386_op temp_op;
i386_operand_type temp_type;
gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F);
gas_assert (!i.tm.opcode_modifier.sae);
gas_assert (operand_type_equal (&i.types[i.operands - 2],
&i.types[i.operands - 3]));
gas_assert (i.rm.mode == 3);
temp_type = i.types[xchg];
i.types[xchg] = i.types[xchg + 1];
i.types[xchg + 1] = temp_type;
temp_op = i.op[xchg];
i.op[xchg] = i.op[xchg + 1];
i.op[xchg + 1] = temp_op;
i.rex = 0;
xchg = i.rm.regmem | 8;
i.rm.regmem = ~register_specifier & 0xf;
gas_assert (!(i.rm.regmem & 8));
i.vex.register_specifier += xchg - i.rm.regmem;
register_specifier = ~xchg & 0xf;
}
if (i.tm.opcode_modifier.vex == VEXScalar)
vector_length = avxscalar;
else if (i.tm.opcode_modifier.vex == VEX256)
@ -4157,6 +4197,9 @@ optimize_encoding (void)
i.tm.opcode_modifier.vex
= i.types[0].bitfield.ymmword ? VEX256 : VEX128;
i.tm.opcode_modifier.vexw = VEXW0;
/* VPAND, VPOR, and VPXOR are commutative. */
if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df)
i.tm.opcode_modifier.commutative = 1;
i.tm.opcode_modifier.evex = 0;
i.tm.opcode_modifier.masking = 0;
i.tm.opcode_modifier.broadcast = 0;

5
gas/doc/c-i386.texi
View File

@ -474,7 +474,10 @@ instructions with 128-bit/256-bit VEX packed integer logical.
@samp{-O2} includes @samp{-O1} optimization plus encodes
256-bit/512-bit EVEX vector register clearing instructions with 128-bit
EVEX vector register clearing instructions.
EVEX vector register clearing instructions. In 64-bit mode VEX encoded
instructions with commutative source operands will also have their
source operands swapped if this allows using the 2-byte VEX prefix form
instead of the 3-byte one.
@samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
and 64-bit register tests with immediate as 8-bit register test with

1
gas/testsuite/gas/i386/i386.exp
View File

@ -811,6 +811,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-sse2avx-opts-intel"
run_dump_test "x86-64-avx-swap"
run_dump_test "x86-64-avx-swap-intel"
run_dump_test "x86-64-avx-swap-2"
run_dump_test "x86-64-bmi2"
run_dump_test "x86-64-bmi2-intel"
run_dump_test "x86-64-fma"

1226
gas/testsuite/gas/i386/ilp32/x86-64-sse2avx.d
View File

File diff suppressed because it is too large Load Diff

380
gas/testsuite/gas/i386/x86-64-avx-swap-2.d Normal file
View File

@ -0,0 +1,380 @@
#as: -O2
#objdump: -dw
#name: x86-64 AVX/AVX2 w/ source swapping
.*: file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: c4 c1 4d 58 d6 vaddpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c 58 d6 vaddps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d d0 d6 vaddsubpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4f d0 d6 vaddsubps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 55 d6 vandnpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c 55 d6 vandnps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d 54 d6 vandpd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c 54 d6 vandps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 5e d6 vdivpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c 5e d6 vdivps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 7c d6 vhaddpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4f 7c d6 vhaddps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 7d d6 vhsubpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4f 7d d6 vhsubps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 5f d6 vmaxpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c 5f d6 vmaxps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 5d d6 vminpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c 5d d6 vminps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 59 d6 vmulpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c 59 d6 vmulps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d 56 d6 vorpd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c 56 d6 vorps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d fc d6 vpaddb %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d fd d6 vpaddw %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d fe d6 vpaddd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d d4 d6 vpaddq %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d ec d6 vpaddsb %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d ed d6 vpaddsw %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d dc d6 vpaddusb %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d dd d6 vpaddusw %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d db d6 vpand %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d df d6 vpandn %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d e0 d6 vpavgb %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d e3 d6 vpavgw %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d 74 d6 vpcmpeqb %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d 75 d6 vpcmpeqw %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d 76 d6 vpcmpeqd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 29 d6 vpcmpeqq %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 64 d6 vpcmpgtb %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 65 d6 vpcmpgtw %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 66 d6 vpcmpgtd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 37 d6 vpcmpgtq %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d f5 d6 vpmaddwd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 3c d6 vpmaxsb %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d ee d6 vpmaxsw %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 3d d6 vpmaxsd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d de d6 vpmaxub %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 3e d6 vpmaxuw %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 3f d6 vpmaxud %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 38 d6 vpminsb %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d ea d6 vpminsw %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 39 d6 vpminsd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d da d6 vpminub %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 3a d6 vpminuw %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 3b d6 vpminud %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d e4 d6 vpmulhuw %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d e5 d6 vpmulhw %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d d5 d6 vpmullw %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 40 d6 vpmulld %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d f4 d6 vpmuludq %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c2 4d 28 d6 vpmuldq %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d eb d6 vpor %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d f6 d6 vpsadbw %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d f8 d6 vpsubb %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d f9 d6 vpsubw %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d fa d6 vpsubd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d fb d6 vpsubq %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d e8 d6 vpsubsb %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d e9 d6 vpsubsw %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d d8 d6 vpsubusb %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d d9 d6 vpsubusw %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d ef d6 vpxor %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d 5c d6 vsubpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c 5c d6 vsubps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d 57 d6 vxorpd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c 57 d6 vxorps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 00 vcmpeqpd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 01 vcmpltpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 02 vcmplepd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 03 vcmpunordpd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 04 vcmpneqpd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 05 vcmpnltpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 06 vcmpnlepd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 07 vcmpordpd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 08 vcmpeq_uqpd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 09 vcmpngepd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 0a vcmpngtpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 0b vcmpfalsepd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 0c vcmpneq_oqpd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 0d vcmpgepd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 0e vcmpgtpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 0f vcmptruepd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 10 vcmpeq_ospd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 11 vcmplt_oqpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 12 vcmple_oqpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 13 vcmpunord_spd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 14 vcmpneq_uspd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 15 vcmpnlt_uqpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 16 vcmpnle_uqpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 17 vcmpord_spd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 18 vcmpeq_uspd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 19 vcmpnge_uqpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 1a vcmpngt_uqpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 1b vcmpfalse_ospd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 1c vcmpneq_ospd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 1d vcmpge_oqpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 1e vcmpgt_oqpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8d c2 d6 1f vcmptrue_uspd %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 00 vcmpeqps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 01 vcmpltps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 02 vcmpleps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 03 vcmpunordps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 04 vcmpneqps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 05 vcmpnltps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 06 vcmpnleps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 07 vcmpordps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 08 vcmpeq_uqps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 09 vcmpngeps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 0a vcmpngtps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 0b vcmpfalseps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 0c vcmpneq_oqps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 0d vcmpgeps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 0e vcmpgtps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 0f vcmptrueps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 10 vcmpeq_osps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 11 vcmplt_oqps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 12 vcmple_oqps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 13 vcmpunord_sps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 14 vcmpneq_usps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 15 vcmpnlt_uqps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 16 vcmpnle_uqps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 17 vcmpord_sps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 18 vcmpeq_usps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 19 vcmpnge_uqps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 1a vcmpngt_uqps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 1b vcmpfalse_osps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 1c vcmpneq_osps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 1d vcmpge_oqps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 1e vcmpgt_oqps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 8c c2 d6 1f vcmptrue_usps %ymm6,%ymm14,%ymm2
[ ]*[a-f0-9]+: c4 c1 4d c2 d6 07 vcmpordpd %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 4c c2 d6 07 vcmpordps %ymm14,%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 c1 49 58 d6 vaddpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 58 d6 vaddps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 d0 d6 vaddsubpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b d0 d6 vaddsubps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 55 d6 vandnpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 55 d6 vandnps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 54 d6 vandpd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 54 d6 vandps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 5e d6 vdivpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 5e d6 vdivps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 7c d6 vhaddpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b 7c d6 vhaddps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 7d d6 vhsubpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b 7d d6 vhsubps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 5f d6 vmaxpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 5f d6 vmaxps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 5d d6 vminpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 5d d6 vminps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 59 d6 vmulpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 59 d6 vmulps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 56 d6 vorpd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 56 d6 vorps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 fc d6 vpaddb %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 fd d6 vpaddw %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 fe d6 vpaddd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 d4 d6 vpaddq %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 ec d6 vpaddsb %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 ed d6 vpaddsw %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 dc d6 vpaddusb %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 dd d6 vpaddusw %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 db d6 vpand %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 df d6 vpandn %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 e0 d6 vpavgb %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 e3 d6 vpavgw %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 74 d6 vpcmpeqb %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 75 d6 vpcmpeqw %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 76 d6 vpcmpeqd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 29 d6 vpcmpeqq %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 64 d6 vpcmpgtb %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 65 d6 vpcmpgtw %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 66 d6 vpcmpgtd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 37 d6 vpcmpgtq %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 f5 d6 vpmaddwd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 3c d6 vpmaxsb %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 ee d6 vpmaxsw %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 3d d6 vpmaxsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 de d6 vpmaxub %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 3e d6 vpmaxuw %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 3f d6 vpmaxud %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 38 d6 vpminsb %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 ea d6 vpminsw %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 39 d6 vpminsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 da d6 vpminub %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 3a d6 vpminuw %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 3b d6 vpminud %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 e4 d6 vpmulhuw %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 e5 d6 vpmulhw %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 d5 d6 vpmullw %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 40 d6 vpmulld %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 f4 d6 vpmuludq %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c2 49 28 d6 vpmuldq %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 eb d6 vpor %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 f6 d6 vpsadbw %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 f8 d6 vpsubb %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 f9 d6 vpsubw %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 fa d6 vpsubd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 fb d6 vpsubq %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 e8 d6 vpsubsb %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 e9 d6 vpsubsw %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 d8 d6 vpsubusb %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 d9 d6 vpsubusw %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 ef d6 vpxor %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 5c d6 vsubpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 5c d6 vsubps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 57 d6 vxorpd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 57 d6 vxorps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 00 vcmpeqpd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 01 vcmpltpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 02 vcmplepd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 03 vcmpunordpd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 04 vcmpneqpd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 05 vcmpnltpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 06 vcmpnlepd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 07 vcmpordpd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 08 vcmpeq_uqpd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 09 vcmpngepd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 0a vcmpngtpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 0b vcmpfalsepd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 0c vcmpneq_oqpd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 0d vcmpgepd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 0e vcmpgtpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 0f vcmptruepd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 10 vcmpeq_ospd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 11 vcmplt_oqpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 12 vcmple_oqpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 13 vcmpunord_spd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 14 vcmpneq_uspd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 15 vcmpnlt_uqpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 16 vcmpnle_uqpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 17 vcmpord_spd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 18 vcmpeq_uspd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 19 vcmpnge_uqpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 1a vcmpngt_uqpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 1b vcmpfalse_ospd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 1c vcmpneq_ospd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 1d vcmpge_oqpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 1e vcmpgt_oqpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 89 c2 d6 1f vcmptrue_uspd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 00 vcmpeqps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 01 vcmpltps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 02 vcmpleps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 03 vcmpunordps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 04 vcmpneqps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 05 vcmpnltps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 06 vcmpnleps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 07 vcmpordps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 08 vcmpeq_uqps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 09 vcmpngeps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 0a vcmpngtps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 0b vcmpfalseps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 0c vcmpneq_oqps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 0d vcmpgeps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 0e vcmpgtps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 0f vcmptrueps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 10 vcmpeq_osps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 11 vcmplt_oqps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 12 vcmple_oqps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 13 vcmpunord_sps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 14 vcmpneq_usps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 15 vcmpnlt_uqps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 16 vcmpnle_uqps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 17 vcmpord_sps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 18 vcmpeq_usps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 19 vcmpnge_uqps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 1a vcmpngt_uqps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 1b vcmpfalse_osps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 1c vcmpneq_osps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 1d vcmpge_oqps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 1e vcmpgt_oqps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 88 c2 d6 1f vcmptrue_usps %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 49 c2 d6 07 vcmpordpd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 48 c2 d6 07 vcmpordps %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 79 2f f6 vcomisd %xmm14,%xmm6
[ ]*[a-f0-9]+: c4 c1 79 2e f6 vucomisd %xmm14,%xmm6
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 07 vcmpordsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b 58 d6 vaddsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b 5e d6 vdivsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b 5f d6 vmaxsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b 5d d6 vminsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b 59 d6 vmulsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b 51 d6 vsqrtsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b 5c d6 vsubsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 00 vcmpeqsd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 01 vcmpltsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 02 vcmplesd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 03 vcmpunordsd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 04 vcmpneqsd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 05 vcmpnltsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 06 vcmpnlesd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 07 vcmpordsd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 08 vcmpeq_uqsd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 09 vcmpngesd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 0a vcmpngtsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 0b vcmpfalsesd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 0c vcmpneq_oqsd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 0d vcmpgesd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 0e vcmpgtsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 0f vcmptruesd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 10 vcmpeq_ossd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 11 vcmplt_oqsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 12 vcmple_oqsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 13 vcmpunord_ssd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 14 vcmpneq_ussd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 15 vcmpnlt_uqsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 16 vcmpnle_uqsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 17 vcmpord_ssd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 18 vcmpeq_ussd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 19 vcmpnge_uqsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 1a vcmpngt_uqsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 1b vcmpfalse_ossd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 1c vcmpneq_ossd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 1d vcmpge_oqsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4b c2 d6 1e vcmpgt_oqsd %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8b c2 d6 1f vcmptrue_ussd %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a 58 d6 vaddss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a 5e d6 vdivss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a 5f d6 vmaxss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a 5d d6 vminss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a 59 d6 vmulss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a 53 d6 vrcpss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a 52 d6 vrsqrtss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a 51 d6 vsqrtss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a 5c d6 vsubss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 00 vcmpeqss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 01 vcmpltss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 02 vcmpless %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 03 vcmpunordss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 04 vcmpneqss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 05 vcmpnltss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 06 vcmpnless %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 07 vcmpordss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 08 vcmpeq_uqss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 09 vcmpngess %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 0a vcmpngtss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 0b vcmpfalsess %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 0c vcmpneq_oqss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 0d vcmpgess %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 0e vcmpgtss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 0f vcmptruess %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 10 vcmpeq_osss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 11 vcmplt_oqss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 12 vcmple_oqss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 13 vcmpunord_sss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 14 vcmpneq_usss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 15 vcmpnlt_uqss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 16 vcmpnle_uqss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 17 vcmpord_sss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 18 vcmpeq_usss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 19 vcmpnge_uqss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 1a vcmpngt_uqss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 1b vcmpfalse_osss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 1c vcmpneq_osss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 1d vcmpge_oqss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 1e vcmpgt_oqss %xmm14,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 8a c2 d6 1f vcmptrue_usss %xmm6,%xmm14,%xmm2
[ ]*[a-f0-9]+: c4 c1 78 2f f6 vcomiss %xmm14,%xmm6
[ ]*[a-f0-9]+: c4 c1 78 2e f6 vucomiss %xmm14,%xmm6
[ ]*[a-f0-9]+: c4 c1 4a c2 d6 07 vcmpordss %xmm14,%xmm6,%xmm2
#pass

393
gas/testsuite/gas/i386/x86-64-avx-swap-2.s Normal file
View File

@ -0,0 +1,393 @@
# Check 64bit AVX/AVX2 instructions w/ source swapping
.text
_start:
# Tests for op ymm/mem256, ymm, ymm
vaddpd %ymm14,%ymm6,%ymm2
vaddps %ymm14,%ymm6,%ymm2
vaddsubpd %ymm14,%ymm6,%ymm2
vaddsubps %ymm14,%ymm6,%ymm2
vandnpd %ymm14,%ymm6,%ymm2
vandnps %ymm14,%ymm6,%ymm2
vandpd %ymm14,%ymm6,%ymm2
vandps %ymm14,%ymm6,%ymm2
vdivpd %ymm14,%ymm6,%ymm2
vdivps %ymm14,%ymm6,%ymm2
vhaddpd %ymm14,%ymm6,%ymm2
vhaddps %ymm14,%ymm6,%ymm2
vhsubpd %ymm14,%ymm6,%ymm2
vhsubps %ymm14,%ymm6,%ymm2
vmaxpd %ymm14,%ymm6,%ymm2
vmaxps %ymm14,%ymm6,%ymm2
vminpd %ymm14,%ymm6,%ymm2
vminps %ymm14,%ymm6,%ymm2
vmulpd %ymm14,%ymm6,%ymm2
vmulps %ymm14,%ymm6,%ymm2
vorpd %ymm14,%ymm6,%ymm2
vorps %ymm14,%ymm6,%ymm2
vpaddb %ymm14,%ymm6,%ymm2
vpaddw %ymm14,%ymm6,%ymm2
vpaddd %ymm14,%ymm6,%ymm2
vpaddq %ymm14,%ymm6,%ymm2
vpaddsb %ymm14,%ymm6,%ymm2
vpaddsw %ymm14,%ymm6,%ymm2
vpaddusb %ymm14,%ymm6,%ymm2
vpaddusw %ymm14,%ymm6,%ymm2
vpand %ymm14,%ymm6,%ymm2
vpandn %ymm14,%ymm6,%ymm2
vpavgb %ymm14,%ymm6,%ymm2
vpavgw %ymm14,%ymm6,%ymm2
vpcmpeqb %ymm14,%ymm6,%ymm2
vpcmpeqw %ymm14,%ymm6,%ymm2
vpcmpeqd %ymm14,%ymm6,%ymm2
vpcmpeqq %ymm14,%ymm6,%ymm2
vpcmpgtb %ymm14,%ymm6,%ymm2
vpcmpgtw %ymm14,%ymm6,%ymm2
vpcmpgtd %ymm14,%ymm6,%ymm2
vpcmpgtq %ymm14,%ymm6,%ymm2
vpmaddwd %ymm14,%ymm6,%ymm2
vpmaxsb %ymm14,%ymm6,%ymm2
vpmaxsw %ymm14,%ymm6,%ymm2
vpmaxsd %ymm14,%ymm6,%ymm2
vpmaxub %ymm14,%ymm6,%ymm2
vpmaxuw %ymm14,%ymm6,%ymm2
vpmaxud %ymm14,%ymm6,%ymm2
vpminsb %ymm14,%ymm6,%ymm2
vpminsw %ymm14,%ymm6,%ymm2
vpminsd %ymm14,%ymm6,%ymm2
vpminub %ymm14,%ymm6,%ymm2
vpminuw %ymm14,%ymm6,%ymm2
vpminud %ymm14,%ymm6,%ymm2
vpmulhuw %ymm14,%ymm6,%ymm2
vpmulhw %ymm14,%ymm6,%ymm2
vpmullw %ymm14,%ymm6,%ymm2
vpmulld %ymm14,%ymm6,%ymm2
vpmuludq %ymm14,%ymm6,%ymm2
vpmuldq %ymm14,%ymm6,%ymm2
vpor %ymm14,%ymm6,%ymm2
vpsadbw %ymm14,%ymm6,%ymm2
vpsubb %ymm14,%ymm6,%ymm2
vpsubw %ymm14,%ymm6,%ymm2
vpsubd %ymm14,%ymm6,%ymm2
vpsubq %ymm14,%ymm6,%ymm2
vpsubsb %ymm14,%ymm6,%ymm2
vpsubsw %ymm14,%ymm6,%ymm2
vpsubusb %ymm14,%ymm6,%ymm2
vpsubusw %ymm14,%ymm6,%ymm2
vpxor %ymm14,%ymm6,%ymm2
vsubpd %ymm14,%ymm6,%ymm2
vsubps %ymm14,%ymm6,%ymm2
vxorpd %ymm14,%ymm6,%ymm2
vxorps %ymm14,%ymm6,%ymm2
vcmpeqpd %ymm14,%ymm6,%ymm2
vcmpltpd %ymm14,%ymm6,%ymm2
vcmplepd %ymm14,%ymm6,%ymm2
vcmpunordpd %ymm14,%ymm6,%ymm2
vcmpneqpd %ymm14,%ymm6,%ymm2
vcmpnltpd %ymm14,%ymm6,%ymm2
vcmpnlepd %ymm14,%ymm6,%ymm2
vcmpordpd %ymm14,%ymm6,%ymm2
vcmpeq_uqpd %ymm14,%ymm6,%ymm2
vcmpngepd %ymm14,%ymm6,%ymm2
vcmpngtpd %ymm14,%ymm6,%ymm2
vcmpfalsepd %ymm14,%ymm6,%ymm2
vcmpneq_oqpd %ymm14,%ymm6,%ymm2
vcmpgepd %ymm14,%ymm6,%ymm2
vcmpgtpd %ymm14,%ymm6,%ymm2
vcmptruepd %ymm14,%ymm6,%ymm2
vcmpeq_ospd %ymm14,%ymm6,%ymm2
vcmplt_oqpd %ymm14,%ymm6,%ymm2
vcmple_oqpd %ymm14,%ymm6,%ymm2
vcmpunord_spd %ymm14,%ymm6,%ymm2
vcmpneq_uspd %ymm14,%ymm6,%ymm2
vcmpnlt_uqpd %ymm14,%ymm6,%ymm2
vcmpnle_uqpd %ymm14,%ymm6,%ymm2
vcmpord_spd %ymm14,%ymm6,%ymm2
vcmpeq_uspd %ymm14,%ymm6,%ymm2
vcmpnge_uqpd %ymm14,%ymm6,%ymm2
vcmpngt_uqpd %ymm14,%ymm6,%ymm2
vcmpfalse_ospd %ymm14,%ymm6,%ymm2
vcmpneq_ospd %ymm14,%ymm6,%ymm2
vcmpge_oqpd %ymm14,%ymm6,%ymm2
vcmpgt_oqpd %ymm14,%ymm6,%ymm2
vcmptrue_uspd %ymm14,%ymm6,%ymm2
vcmpeqps %ymm14,%ymm6,%ymm2
vcmpltps %ymm14,%ymm6,%ymm2
vcmpleps %ymm14,%ymm6,%ymm2
vcmpunordps %ymm14,%ymm6,%ymm2
vcmpneqps %ymm14,%ymm6,%ymm2
vcmpnltps %ymm14,%ymm6,%ymm2
vcmpnleps %ymm14,%ymm6,%ymm2
vcmpordps %ymm14,%ymm6,%ymm2
vcmpeq_uqps %ymm14,%ymm6,%ymm2
vcmpngeps %ymm14,%ymm6,%ymm2
vcmpngtps %ymm14,%ymm6,%ymm2
vcmpfalseps %ymm14,%ymm6,%ymm2
vcmpneq_oqps %ymm14,%ymm6,%ymm2
vcmpgeps %ymm14,%ymm6,%ymm2
vcmpgtps %ymm14,%ymm6,%ymm2
vcmptrueps %ymm14,%ymm6,%ymm2
vcmpeq_osps %ymm14,%ymm6,%ymm2
vcmplt_oqps %ymm14,%ymm6,%ymm2
vcmple_oqps %ymm14,%ymm6,%ymm2
vcmpunord_sps %ymm14,%ymm6,%ymm2
vcmpneq_usps %ymm14,%ymm6,%ymm2
vcmpnlt_uqps %ymm14,%ymm6,%ymm2
vcmpnle_uqps %ymm14,%ymm6,%ymm2
vcmpord_sps %ymm14,%ymm6,%ymm2
vcmpeq_usps %ymm14,%ymm6,%ymm2
vcmpnge_uqps %ymm14,%ymm6,%ymm2
vcmpngt_uqps %ymm14,%ymm6,%ymm2
vcmpfalse_osps %ymm14,%ymm6,%ymm2
vcmpneq_osps %ymm14,%ymm6,%ymm2
vcmpge_oqps %ymm14,%ymm6,%ymm2
vcmpgt_oqps %ymm14,%ymm6,%ymm2
vcmptrue_usps %ymm14,%ymm6,%ymm2
# Tests for op imm8, ymm/mem256, ymm, ymm
vcmppd $7,%ymm14,%ymm6,%ymm2
vcmpps $7,%ymm14,%ymm6,%ymm2
# Tests for op xmm/mem128, xmm, xmm
vaddpd %xmm14,%xmm6,%xmm2
vaddps %xmm14,%xmm6,%xmm2
vaddsubpd %xmm14,%xmm6,%xmm2
vaddsubps %xmm14,%xmm6,%xmm2
vandnpd %xmm14,%xmm6,%xmm2
vandnps %xmm14,%xmm6,%xmm2
vandpd %xmm14,%xmm6,%xmm2
vandps %xmm14,%xmm6,%xmm2
vdivpd %xmm14,%xmm6,%xmm2
vdivps %xmm14,%xmm6,%xmm2
vhaddpd %xmm14,%xmm6,%xmm2
vhaddps %xmm14,%xmm6,%xmm2
vhsubpd %xmm14,%xmm6,%xmm2
vhsubps %xmm14,%xmm6,%xmm2
vmaxpd %xmm14,%xmm6,%xmm2
vmaxps %xmm14,%xmm6,%xmm2
vminpd %xmm14,%xmm6,%xmm2
vminps %xmm14,%xmm6,%xmm2
vmulpd %xmm14,%xmm6,%xmm2
vmulps %xmm14,%xmm6,%xmm2
vorpd %xmm14,%xmm6,%xmm2
vorps %xmm14,%xmm6,%xmm2
vpaddb %xmm14,%xmm6,%xmm2
vpaddw %xmm14,%xmm6,%xmm2
vpaddd %xmm14,%xmm6,%xmm2
vpaddq %xmm14,%xmm6,%xmm2
vpaddsb %xmm14,%xmm6,%xmm2
vpaddsw %xmm14,%xmm6,%xmm2
vpaddusb %xmm14,%xmm6,%xmm2
vpaddusw %xmm14,%xmm6,%xmm2
vpand %xmm14,%xmm6,%xmm2
vpandn %xmm14,%xmm6,%xmm2
vpavgb %xmm14,%xmm6,%xmm2
vpavgw %xmm14,%xmm6,%xmm2
vpcmpeqb %xmm14,%xmm6,%xmm2
vpcmpeqw %xmm14,%xmm6,%xmm2
vpcmpeqd %xmm14,%xmm6,%xmm2
vpcmpeqq %xmm14,%xmm6,%xmm2
vpcmpgtb %xmm14,%xmm6,%xmm2
vpcmpgtw %xmm14,%xmm6,%xmm2
vpcmpgtd %xmm14,%xmm6,%xmm2
vpcmpgtq %xmm14,%xmm6,%xmm2
vpmaddwd %xmm14,%xmm6,%xmm2
vpmaxsb %xmm14,%xmm6,%xmm2
vpmaxsw %xmm14,%xmm6,%xmm2
vpmaxsd %xmm14,%xmm6,%xmm2
vpmaxub %xmm14,%xmm6,%xmm2
vpmaxuw %xmm14,%xmm6,%xmm2
vpmaxud %xmm14,%xmm6,%xmm2
vpminsb %xmm14,%xmm6,%xmm2
vpminsw %xmm14,%xmm6,%xmm2
vpminsd %xmm14,%xmm6,%xmm2
vpminub %xmm14,%xmm6,%xmm2
vpminuw %xmm14,%xmm6,%xmm2
vpminud %xmm14,%xmm6,%xmm2
vpmulhuw %xmm14,%xmm6,%xmm2
vpmulhw %xmm14,%xmm6,%xmm2
vpmullw %xmm14,%xmm6,%xmm2
vpmulld %xmm14,%xmm6,%xmm2
vpmuludq %xmm14,%xmm6,%xmm2
vpmuldq %xmm14,%xmm6,%xmm2
vpor %xmm14,%xmm6,%xmm2
vpsadbw %xmm14,%xmm6,%xmm2
vpsubb %xmm14,%xmm6,%xmm2
vpsubw %xmm14,%xmm6,%xmm2
vpsubd %xmm14,%xmm6,%xmm2
vpsubq %xmm14,%xmm6,%xmm2
vpsubsb %xmm14,%xmm6,%xmm2
vpsubsw %xmm14,%xmm6,%xmm2
vpsubusb %xmm14,%xmm6,%xmm2
vpsubusw %xmm14,%xmm6,%xmm2
vpxor %xmm14,%xmm6,%xmm2
vsubpd %xmm14,%xmm6,%xmm2
vsubps %xmm14,%xmm6,%xmm2
vxorpd %xmm14,%xmm6,%xmm2
vxorps %xmm14,%xmm6,%xmm2
vcmpeqpd %xmm14,%xmm6,%xmm2
vcmpltpd %xmm14,%xmm6,%xmm2
vcmplepd %xmm14,%xmm6,%xmm2
vcmpunordpd %xmm14,%xmm6,%xmm2
vcmpneqpd %xmm14,%xmm6,%xmm2
vcmpnltpd %xmm14,%xmm6,%xmm2
vcmpnlepd %xmm14,%xmm6,%xmm2
vcmpordpd %xmm14,%xmm6,%xmm2
vcmpeq_uqpd %xmm14,%xmm6,%xmm2
vcmpngepd %xmm14,%xmm6,%xmm2
vcmpngtpd %xmm14,%xmm6,%xmm2
vcmpfalsepd %xmm14,%xmm6,%xmm2
vcmpneq_oqpd %xmm14,%xmm6,%xmm2
vcmpgepd %xmm14,%xmm6,%xmm2
vcmpgtpd %xmm14,%xmm6,%xmm2
vcmptruepd %xmm14,%xmm6,%xmm2
vcmpeq_ospd %xmm14,%xmm6,%xmm2
vcmplt_oqpd %xmm14,%xmm6,%xmm2
vcmple_oqpd %xmm14,%xmm6,%xmm2
vcmpunord_spd %xmm14,%xmm6,%xmm2
vcmpneq_uspd %xmm14,%xmm6,%xmm2
vcmpnlt_uqpd %xmm14,%xmm6,%xmm2
vcmpnle_uqpd %xmm14,%xmm6,%xmm2
vcmpord_spd %xmm14,%xmm6,%xmm2
vcmpeq_uspd %xmm14,%xmm6,%xmm2
vcmpnge_uqpd %xmm14,%xmm6,%xmm2
vcmpngt_uqpd %xmm14,%xmm6,%xmm2
vcmpfalse_ospd %xmm14,%xmm6,%xmm2
vcmpneq_ospd %xmm14,%xmm6,%xmm2
vcmpge_oqpd %xmm14,%xmm6,%xmm2
vcmpgt_oqpd %xmm14,%xmm6,%xmm2
vcmptrue_uspd %xmm14,%xmm6,%xmm2
vcmpeqps %xmm14,%xmm6,%xmm2
vcmpltps %xmm14,%xmm6,%xmm2
vcmpleps %xmm14,%xmm6,%xmm2
vcmpunordps %xmm14,%xmm6,%xmm2
vcmpneqps %xmm14,%xmm6,%xmm2
vcmpnltps %xmm14,%xmm6,%xmm2
vcmpnleps %xmm14,%xmm6,%xmm2
vcmpordps %xmm14,%xmm6,%xmm2
vcmpeq_uqps %xmm14,%xmm6,%xmm2
vcmpngeps %xmm14,%xmm6,%xmm2
vcmpngtps %xmm14,%xmm6,%xmm2
vcmpfalseps %xmm14,%xmm6,%xmm2
vcmpneq_oqps %xmm14,%xmm6,%xmm2
vcmpgeps %xmm14,%xmm6,%xmm2
vcmpgtps %xmm14,%xmm6,%xmm2
vcmptrueps %xmm14,%xmm6,%xmm2
vcmpeq_osps %xmm14,%xmm6,%xmm2
vcmplt_oqps %xmm14,%xmm6,%xmm2
vcmple_oqps %xmm14,%xmm6,%xmm2
vcmpunord_sps %xmm14,%xmm6,%xmm2
vcmpneq_usps %xmm14,%xmm6,%xmm2
vcmpnlt_uqps %xmm14,%xmm6,%xmm2
vcmpnle_uqps %xmm14,%xmm6,%xmm2
vcmpord_sps %xmm14,%xmm6,%xmm2
vcmpeq_usps %xmm14,%xmm6,%xmm2
vcmpnge_uqps %xmm14,%xmm6,%xmm2
vcmpngt_uqps %xmm14,%xmm6,%xmm2
vcmpfalse_osps %xmm14,%xmm6,%xmm2
vcmpneq_osps %xmm14,%xmm6,%xmm2
vcmpge_oqps %xmm14,%xmm6,%xmm2
vcmpgt_oqps %xmm14,%xmm6,%xmm2
vcmptrue_usps %xmm14,%xmm6,%xmm2
# Tests for op imm8, xmm/mem128, xmm, xmm
vcmppd $7,%xmm14,%xmm6,%xmm2
vcmpps $7,%xmm14,%xmm6,%xmm2
# Tests for op xmm/mem64, xmm
vcomisd %xmm14,%xmm6
vucomisd %xmm14,%xmm6
# Tests for op imm8, xmm/mem64, xmm, xmm
vcmpsd $7,%xmm14,%xmm6,%xmm2
# Tests for op xmm/mem64, xmm, xmm
vaddsd %xmm14,%xmm6,%xmm2
vdivsd %xmm14,%xmm6,%xmm2
vmaxsd %xmm14,%xmm6,%xmm2
vminsd %xmm14,%xmm6,%xmm2
vmulsd %xmm14,%xmm6,%xmm2
vsqrtsd %xmm14,%xmm6,%xmm2
vsubsd %xmm14,%xmm6,%xmm2
vcmpeqsd %xmm14,%xmm6,%xmm2
vcmpltsd %xmm14,%xmm6,%xmm2
vcmplesd %xmm14,%xmm6,%xmm2
vcmpunordsd %xmm14,%xmm6,%xmm2
vcmpneqsd %xmm14,%xmm6,%xmm2
vcmpnltsd %xmm14,%xmm6,%xmm2
vcmpnlesd %xmm14,%xmm6,%xmm2
vcmpordsd %xmm14,%xmm6,%xmm2
vcmpeq_uqsd %xmm14,%xmm6,%xmm2
vcmpngesd %xmm14,%xmm6,%xmm2
vcmpngtsd %xmm14,%xmm6,%xmm2
vcmpfalsesd %xmm14,%xmm6,%xmm2
vcmpneq_oqsd %xmm14,%xmm6,%xmm2
vcmpgesd %xmm14,%xmm6,%xmm2
vcmpgtsd %xmm14,%xmm6,%xmm2
vcmptruesd %xmm14,%xmm6,%xmm2
vcmpeq_ossd %xmm14,%xmm6,%xmm2
vcmplt_oqsd %xmm14,%xmm6,%xmm2
vcmple_oqsd %xmm14,%xmm6,%xmm2
vcmpunord_ssd %xmm14,%xmm6,%xmm2
vcmpneq_ussd %xmm14,%xmm6,%xmm2
vcmpnlt_uqsd %xmm14,%xmm6,%xmm2
vcmpnle_uqsd %xmm14,%xmm6,%xmm2
vcmpord_ssd %xmm14,%xmm6,%xmm2
vcmpeq_ussd %xmm14,%xmm6,%xmm2
vcmpnge_uqsd %xmm14,%xmm6,%xmm2
vcmpngt_uqsd %xmm14,%xmm6,%xmm2
vcmpfalse_ossd %xmm14,%xmm6,%xmm2
vcmpneq_ossd %xmm14,%xmm6,%xmm2
vcmpge_oqsd %xmm14,%xmm6,%xmm2
vcmpgt_oqsd %xmm14,%xmm6,%xmm2
vcmptrue_ussd %xmm14,%xmm6,%xmm2
# Tests for op xmm/mem32, xmm, xmm
vaddss %xmm14,%xmm6,%xmm2
vdivss %xmm14,%xmm6,%xmm2
vmaxss %xmm14,%xmm6,%xmm2
vminss %xmm14,%xmm6,%xmm2
vmulss %xmm14,%xmm6,%xmm2
vrcpss %xmm14,%xmm6,%xmm2
vrsqrtss %xmm14,%xmm6,%xmm2
vsqrtss %xmm14,%xmm6,%xmm2
vsubss %xmm14,%xmm6,%xmm2
vcmpeqss %xmm14,%xmm6,%xmm2
vcmpltss %xmm14,%xmm6,%xmm2
vcmpless %xmm14,%xmm6,%xmm2
vcmpunordss %xmm14,%xmm6,%xmm2
vcmpneqss %xmm14,%xmm6,%xmm2
vcmpnltss %xmm14,%xmm6,%xmm2
vcmpnless %xmm14,%xmm6,%xmm2
vcmpordss %xmm14,%xmm6,%xmm2
vcmpeq_uqss %xmm14,%xmm6,%xmm2
vcmpngess %xmm14,%xmm6,%xmm2
vcmpngtss %xmm14,%xmm6,%xmm2
vcmpfalsess %xmm14,%xmm6,%xmm2
vcmpneq_oqss %xmm14,%xmm6,%xmm2
vcmpgess %xmm14,%xmm6,%xmm2
vcmpgtss %xmm14,%xmm6,%xmm2
vcmptruess %xmm14,%xmm6,%xmm2
vcmpeq_osss %xmm14,%xmm6,%xmm2
vcmplt_oqss %xmm14,%xmm6,%xmm2
vcmple_oqss %xmm14,%xmm6,%xmm2
vcmpunord_sss %xmm14,%xmm6,%xmm2
vcmpneq_usss %xmm14,%xmm6,%xmm2
vcmpnlt_uqss %xmm14,%xmm6,%xmm2
vcmpnle_uqss %xmm14,%xmm6,%xmm2
vcmpord_sss %xmm14,%xmm6,%xmm2
vcmpeq_usss %xmm14,%xmm6,%xmm2
vcmpnge_uqss %xmm14,%xmm6,%xmm2
vcmpngt_uqss %xmm14,%xmm6,%xmm2
vcmpfalse_osss %xmm14,%xmm6,%xmm2
vcmpneq_osss %xmm14,%xmm6,%xmm2
vcmpge_oqss %xmm14,%xmm6,%xmm2
vcmpgt_oqss %xmm14,%xmm6,%xmm2
vcmptrue_usss %xmm14,%xmm6,%xmm2
# Tests for op xmm/mem32, xmm
vcomiss %xmm14,%xmm6
vucomiss %xmm14,%xmm6
# Tests for op imm8, xmm/mem32, xmm, xmm
vcmpss $7,%xmm14,%xmm6,%xmm2

8
gas/testsuite/gas/i386/x86-64-optimize-2.d
View File

@ -156,19 +156,19 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%rax\),%zmm2
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpand %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpor %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpand %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpor %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3

8
gas/testsuite/gas/i386/x86-64-optimize-2b.d
View File

@ -156,19 +156,19 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%rax\),%zmm2
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpand %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpor %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpand %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpor %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3

8
gas/testsuite/gas/i386/x86-64-optimize-3.d
View File

@ -116,19 +116,19 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7e 89 6f d1 vmovdqu32 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 fe 89 6f d1 vmovdqu64 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpand %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpor %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpand %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpor %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3

8
gas/testsuite/gas/i386/x86-64-optimize-5.d
View File

@ -156,19 +156,19 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%rax\),%zmm2
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpand %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpor %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpand %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpor %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3

8
gas/testsuite/gas/i386/x86-64-optimize-6.d
View File

@ -156,19 +156,19 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%rax\),%zmm2
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpand %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpor %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpand %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpor %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3

93
gas/testsuite/gas/i386/x86-64-sse2avx.d
View File

@ -75,20 +75,26 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd %xmm4,\(%rcx\)
[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps %xmm4,\(%rcx\)
[ ]*[a-f0-9]+: c5 c9 58 f4 vaddpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 58 f6 vaddpd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 58 31 vaddpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 58 f4 vaddps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 48 58 f6 vaddps %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 58 31 vaddps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 d0 f4 vaddsubpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 d0 31 vaddsubpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb d0 f4 vaddsubps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb d0 31 vaddsubps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 55 f4 vandnpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 55 f6 vandnpd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 55 31 vandnpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 55 f4 vandnps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 48 55 f6 vandnps %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 55 31 vandnps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 54 f4 vandpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 54 f6 vandpd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 54 31 vandpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 54 f4 vandps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 88 54 f6 vandps %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c8 54 31 vandps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 5e f4 vdivpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 5e 31 vdivpd \(%rcx\),%xmm6,%xmm6
@ -103,20 +109,28 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cb 7d f4 vhsubps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 7d 31 vhsubps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 5f f4 vmaxpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 5f f6 vmaxpd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 5f 31 vmaxpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 5f f4 vmaxps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 48 5f f6 vmaxps %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 5f 31 vmaxps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 5d f4 vminpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 5d f6 vminpd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 5d 31 vminpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 5d f4 vminps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 48 5d f6 vminps %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 5d 31 vminps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 59 f4 vmulpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 59 f6 vmulpd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 59 31 vmulpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 59 f4 vmulps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 48 59 f6 vmulps %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 59 31 vmulps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 56 f4 vorpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 56 f6 vorpd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 56 31 vorpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 56 f4 vorps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 88 56 f6 vorps %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c8 56 31 vorps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 63 f4 vpacksswb %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 63 31 vpacksswb \(%rcx\),%xmm6,%xmm6
@ -127,28 +141,40 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e2 49 2b f4 vpackusdw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 2b 31 vpackusdw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 fc f4 vpaddb %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 fc f6 vpaddb %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 fc 31 vpaddb \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 fd f4 vpaddw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 fd f6 vpaddw %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 fd 31 vpaddw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 fe f4 vpaddd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 fe f6 vpaddd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 fe 31 vpaddd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 d4 f4 vpaddq %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 d4 f6 vpaddq %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 d4 31 vpaddq \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 ec f4 vpaddsb %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 ec f6 vpaddsb %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 ec 31 vpaddsb \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 ed f4 vpaddsw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 ed f6 vpaddsw %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 ed 31 vpaddsw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 dc f4 vpaddusb %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 dc f6 vpaddusb %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 dc 31 vpaddusb \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 dd f4 vpaddusw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 dd f6 vpaddusw %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 dd 31 vpaddusw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 db f4 vpand %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 db f6 vpand %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 db 31 vpand \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 df f4 vpandn %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 df f6 vpandn %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 df 31 vpandn \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 e0 f4 vpavgb %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 e0 f6 vpavgb %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 e0 31 vpavgb \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 e3 f4 vpavgw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 e3 f6 vpavgw %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 e3 31 vpavgw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 44 f4 00 vpclmullqlqdq %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 44 31 00 vpclmullqlqdq \(%rcx\),%xmm6,%xmm6
@ -159,18 +185,24 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e3 49 44 f4 11 vpclmulhqhqdq %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 44 31 11 vpclmulhqhqdq \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 74 f4 vpcmpeqb %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 74 f6 vpcmpeqb %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 74 31 vpcmpeqb \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 75 f4 vpcmpeqw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 75 f6 vpcmpeqw %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 75 31 vpcmpeqw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 76 f4 vpcmpeqd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 76 f6 vpcmpeqd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 76 31 vpcmpeqd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 29 f4 vpcmpeqq %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 29 31 vpcmpeqq \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 64 f4 vpcmpgtb %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 64 f6 vpcmpgtb %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 64 31 vpcmpgtb \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 65 f4 vpcmpgtw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 65 f6 vpcmpgtw %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 65 31 vpcmpgtw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 66 f4 vpcmpgtd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 66 f6 vpcmpgtd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 66 31 vpcmpgtd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 37 f4 vpcmpgtq %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 37 31 vpcmpgtq \(%rcx\),%xmm6,%xmm6
@ -187,16 +219,19 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e2 49 07 f4 vphsubsw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 07 31 vphsubsw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 f5 f4 vpmaddwd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 f5 f6 vpmaddwd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 f5 31 vpmaddwd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 04 f4 vpmaddubsw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 04 31 vpmaddubsw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 3c f4 vpmaxsb %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 3c 31 vpmaxsb \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 ee f4 vpmaxsw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 ee f6 vpmaxsw %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 ee 31 vpmaxsw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 3d f4 vpmaxsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 3d 31 vpmaxsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 de f4 vpmaxub %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 de f6 vpmaxub %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 de 31 vpmaxub \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 3e f4 vpmaxuw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 3e 31 vpmaxuw \(%rcx\),%xmm6,%xmm6
@ -205,30 +240,37 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e2 49 38 f4 vpminsb %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 38 31 vpminsb \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 ea f4 vpminsw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 ea f6 vpminsw %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 ea 31 vpminsw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 39 f4 vpminsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 39 31 vpminsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 da f4 vpminub %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 da f6 vpminub %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 da 31 vpminub \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 3a f4 vpminuw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 3a 31 vpminuw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 3b f4 vpminud %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 3b 31 vpminud \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 e4 f4 vpmulhuw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 e4 f6 vpmulhuw %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 e4 31 vpmulhuw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 0b f4 vpmulhrsw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 0b 31 vpmulhrsw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 e5 f4 vpmulhw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 e5 f6 vpmulhw %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 e5 31 vpmulhw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 d5 f4 vpmullw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 d5 f6 vpmullw %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 d5 31 vpmullw \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 40 f4 vpmulld %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 40 31 vpmulld \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 f4 f4 vpmuludq %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 f4 f6 vpmuludq %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 f4 31 vpmuludq \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 28 f4 vpmuldq %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 28 31 vpmuldq \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 eb f4 vpor %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 eb f6 vpor %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 eb 31 vpor \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 f6 f4 vpsadbw %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 f6 31 vpsadbw \(%rcx\),%xmm6,%xmm6
@ -289,6 +331,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c9 6c f4 vpunpcklqdq %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 6c 31 vpunpcklqdq \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 ef f4 vpxor %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 ef f6 vpxor %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 ef 31 vpxor \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 5c f4 vsubpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 5c 31 vsubpd \(%rcx\),%xmm6,%xmm6
@ -303,8 +346,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 14 f4 vunpcklps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 14 31 vunpcklps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 57 f4 vxorpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 57 f6 vxorpd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 57 31 vxorpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 57 f4 vxorps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 88 57 f6 vxorps %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c8 57 31 vxorps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 dc f4 vaesenc %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 dc 31 vaesenc \(%rcx\),%xmm6,%xmm6
@ -315,36 +360,52 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e2 49 df f4 vaesdeclast %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e2 49 df 31 vaesdeclast \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 f4 00 vcmpeqpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 c2 f6 00 vcmpeqpd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 31 00 vcmpeqpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 f4 00 vcmpeqps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 88 c2 f6 00 vcmpeqps %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 31 00 vcmpeqps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 f4 01 vcmpltpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 c2 f6 01 vcmpltpd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 31 01 vcmpltpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 f4 01 vcmpltps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 48 c2 f6 01 vcmpltps %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 31 01 vcmpltps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 f4 02 vcmplepd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 c2 f6 02 vcmplepd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 31 02 vcmplepd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 f4 02 vcmpleps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 48 c2 f6 02 vcmpleps %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 31 02 vcmpleps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 f4 03 vcmpunordpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 c2 f6 03 vcmpunordpd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 31 03 vcmpunordpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 f4 03 vcmpunordps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 88 c2 f6 03 vcmpunordps %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 31 03 vcmpunordps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 f4 04 vcmpneqpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 c2 f6 04 vcmpneqpd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 31 04 vcmpneqpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 f4 04 vcmpneqps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 88 c2 f6 04 vcmpneqps %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 31 04 vcmpneqps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 f4 05 vcmpnltpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 c2 f6 05 vcmpnltpd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 31 05 vcmpnltpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 f4 05 vcmpnltps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 48 c2 f6 05 vcmpnltps %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 31 05 vcmpnltps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 f4 06 vcmpnlepd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 c2 f6 06 vcmpnlepd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 31 06 vcmpnlepd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 f4 06 vcmpnleps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 48 c2 f6 06 vcmpnleps %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 31 06 vcmpnleps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 f4 07 vcmpordpd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 89 c2 f6 07 vcmpordpd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 31 07 vcmpordpd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 f4 07 vcmpordps %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 88 c2 f6 07 vcmpordps %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 31 07 vcmpordps \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 79 df f4 64 vaeskeygenassist \$0x64,%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist \$0x64,\(%rcx\),%xmm6
@ -375,8 +436,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e3 49 0c f4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 0c 31 64 vblendps \$0x64,\(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 f4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 49 c2 f6 64 vcmppd \$0x64,%xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c9 c2 31 64 vcmppd \$0x64,\(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 f4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 48 c2 f6 64 vcmpps \$0x64,%xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 c8 c2 31 64 vcmpps \$0x64,\(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 41 f4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 41 31 64 vdppd \$0x64,\(%rcx\),%xmm6,%xmm6
@ -407,6 +470,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e3 49 4c f4 00 vpblendvb %xmm0,%xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 4c 31 00 vpblendvb %xmm0,\(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 c1 79 2f f6 vcomisd %xmm14,%xmm6
[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd \(%rcx\),%xmm4
@ -427,6 +491,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 c1 79 2e f6 vucomisd %xmm14,%xmm6
[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd %xmm4,\(%rcx\)
@ -461,52 +526,69 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 d9 16 21 vmovhpd \(%rcx\),%xmm4,%xmm4
[ ]*[a-f0-9]+: c5 d8 16 21 vmovhps \(%rcx\),%xmm4,%xmm4
[ ]*[a-f0-9]+: c5 cb c2 f4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4b c2 f6 64 vcmpsd \$0x64,%xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 31 64 vcmpsd \$0x64,\(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 0b f4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 0b 31 64 vroundsd \$0x64,\(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 58 f4 vaddsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4b 58 f6 vaddsd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 58 31 vaddsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 5a f4 vcvtsd2ss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 5a 31 vcvtsd2ss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 5e f4 vdivsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 5e 31 vdivsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 5f f4 vmaxsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4b 5f f6 vmaxsd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 5f 31 vmaxsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 5d f4 vminsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4b 5d f6 vminsd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 5d 31 vminsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 59 f4 vmulsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4b 59 f6 vmulsd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 59 31 vmulsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 51 f4 vsqrtsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 51 31 vsqrtsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 5c f4 vsubsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb 5c 31 vsubsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 f4 00 vcmpeqsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 8b c2 f6 00 vcmpeqsd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 31 00 vcmpeqsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 f4 01 vcmpltsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4b c2 f6 01 vcmpltsd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 31 01 vcmpltsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 f4 02 vcmplesd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4b c2 f6 02 vcmplesd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 31 02 vcmplesd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 f4 03 vcmpunordsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 8b c2 f6 03 vcmpunordsd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 31 03 vcmpunordsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 f4 04 vcmpneqsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 8b c2 f6 04 vcmpneqsd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 31 04 vcmpneqsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 f4 05 vcmpnltsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4b c2 f6 05 vcmpnltsd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 31 05 vcmpnltsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 f4 06 vcmpnlesd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4b c2 f6 06 vcmpnlesd %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 31 06 vcmpnlesd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 f4 07 vcmpordsd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 8b c2 f6 07 vcmpordsd %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 cb c2 31 07 vcmpordsd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 58 f4 vaddss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4a 58 f6 vaddss %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 58 31 vaddss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 5a f4 vcvtss2sd %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 5a 31 vcvtss2sd \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 5e f4 vdivss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 5e 31 vdivss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 5f f4 vmaxss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4a 5f f6 vmaxss %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 5f 31 vmaxss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 5d f4 vminss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4a 5d f6 vminss %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 5d 31 vminss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 59 f4 vmulss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4a 59 f6 vmulss %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 59 31 vmulss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 53 f4 vrcpss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 53 31 vrcpss \(%rcx\),%xmm6,%xmm6
@ -517,22 +599,31 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 5c f4 vsubss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca 5c 31 vsubss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 f4 00 vcmpeqss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 8a c2 f6 00 vcmpeqss %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 31 00 vcmpeqss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 f4 01 vcmpltss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4a c2 f6 01 vcmpltss %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 31 01 vcmpltss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 f4 02 vcmpless %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4a c2 f6 02 vcmpless %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 31 02 vcmpless \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 f4 03 vcmpunordss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 8a c2 f6 03 vcmpunordss %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 31 03 vcmpunordss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 f4 04 vcmpneqss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 8a c2 f6 04 vcmpneqss %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 31 04 vcmpneqss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 f4 05 vcmpnltss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4a c2 f6 05 vcmpnltss %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 31 05 vcmpnltss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 f4 06 vcmpnless %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4a c2 f6 06 vcmpnless %xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 31 06 vcmpnless \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 f4 07 vcmpordss %xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 8a c2 f6 07 vcmpordss %xmm6,%xmm14,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 31 07 vcmpordss \(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 c1 78 2f f6 vcomiss %xmm14,%xmm6
[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd \(%rcx\),%xmm4
@ -543,6 +634,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 c1 78 2e f6 vucomiss %xmm14,%xmm6
[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 fa 10 21 vmovss \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 fa 11 21 vmovss %xmm4,\(%rcx\)
@ -572,6 +664,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 da 2a e1 vcvtsi2ss %ecx,%xmm4,%xmm4
[ ]*[a-f0-9]+: c5 da 2a 21 vcvtsi2ssl \(%rcx\),%xmm4,%xmm4
[ ]*[a-f0-9]+: c5 ca c2 f4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 c1 4a c2 f6 64 vcmpss \$0x64,%xmm14,%xmm6,%xmm6
[ ]*[a-f0-9]+: c5 ca c2 31 64 vcmpss \$0x64,\(%rcx\),%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 21 f4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm6
[ ]*[a-f0-9]+: c4 e3 49 21 31 64 vinsertps \$0x64,\(%rcx\),%xmm6,%xmm6

93
gas/testsuite/gas/i386/x86-64-sse2avx.s
View File

@ -82,20 +82,26 @@ _start:
# Tests for op xmm/mem128, xmm[, xmm]
addpd %xmm4,%xmm6
addpd %xmm14,%xmm6
addpd (%rcx),%xmm6
addps %xmm4,%xmm6
addps %xmm14,%xmm6
addps (%rcx),%xmm6
addsubpd %xmm4,%xmm6
addsubpd (%rcx),%xmm6
addsubps %xmm4,%xmm6
addsubps (%rcx),%xmm6
andnpd %xmm4,%xmm6
andnpd %xmm14,%xmm6
andnpd (%rcx),%xmm6
andnps %xmm4,%xmm6
andnps %xmm14,%xmm6
andnps (%rcx),%xmm6
andpd %xmm4,%xmm6
andpd %xmm14,%xmm6
andpd (%rcx),%xmm6
andps %xmm4,%xmm6
andps %xmm14,%xmm6
andps (%rcx),%xmm6
divpd %xmm4,%xmm6
divpd (%rcx),%xmm6
@ -110,20 +116,28 @@ _start:
hsubps %xmm4,%xmm6
hsubps (%rcx),%xmm6
maxpd %xmm4,%xmm6
maxpd %xmm14,%xmm6
maxpd (%rcx),%xmm6
maxps %xmm4,%xmm6
maxps %xmm14,%xmm6
maxps (%rcx),%xmm6
minpd %xmm4,%xmm6
minpd %xmm14,%xmm6
minpd (%rcx),%xmm6
minps %xmm4,%xmm6
minps %xmm14,%xmm6
minps (%rcx),%xmm6
mulpd %xmm4,%xmm6
mulpd %xmm14,%xmm6
mulpd (%rcx),%xmm6
mulps %xmm4,%xmm6
mulps %xmm14,%xmm6
mulps (%rcx),%xmm6
orpd %xmm4,%xmm6
orpd %xmm14,%xmm6
orpd (%rcx),%xmm6
orps %xmm4,%xmm6
orps %xmm14,%xmm6
orps (%rcx),%xmm6
packsswb %xmm4,%xmm6
packsswb (%rcx),%xmm6
@ -134,28 +148,40 @@ _start:
packusdw %xmm4,%xmm6
packusdw (%rcx),%xmm6
paddb %xmm4,%xmm6
paddb %xmm14,%xmm6
paddb (%rcx),%xmm6
paddw %xmm4,%xmm6
paddw %xmm14,%xmm6
paddw (%rcx),%xmm6
paddd %xmm4,%xmm6
paddd %xmm14,%xmm6
paddd (%rcx),%xmm6
paddq %xmm4,%xmm6
paddq %xmm14,%xmm6
paddq (%rcx),%xmm6
paddsb %xmm4,%xmm6
paddsb %xmm14,%xmm6
paddsb (%rcx),%xmm6
paddsw %xmm4,%xmm6
paddsw %xmm14,%xmm6
paddsw (%rcx),%xmm6
paddusb %xmm4,%xmm6
paddusb %xmm14,%xmm6
paddusb (%rcx),%xmm6
paddusw %xmm4,%xmm6
paddusw %xmm14,%xmm6
paddusw (%rcx),%xmm6
pand %xmm4,%xmm6
pand %xmm14,%xmm6
pand (%rcx),%xmm6
pandn %xmm4,%xmm6
pandn %xmm14,%xmm6
pandn (%rcx),%xmm6
pavgb %xmm4,%xmm6
pavgb %xmm14,%xmm6
pavgb (%rcx),%xmm6
pavgw %xmm4,%xmm6
pavgw %xmm14,%xmm6
pavgw (%rcx),%xmm6
pclmullqlqdq %xmm4,%xmm6
pclmullqlqdq (%rcx),%xmm6
@ -166,18 +192,24 @@ _start:
pclmulhqhqdq %xmm4,%xmm6
pclmulhqhqdq (%rcx),%xmm6
pcmpeqb %xmm4,%xmm6
pcmpeqb %xmm14,%xmm6
pcmpeqb (%rcx),%xmm6
pcmpeqw %xmm4,%xmm6
pcmpeqw %xmm14,%xmm6
pcmpeqw (%rcx),%xmm6
pcmpeqd %xmm4,%xmm6
pcmpeqd %xmm14,%xmm6
pcmpeqd (%rcx),%xmm6
pcmpeqq %xmm4,%xmm6
pcmpeqq (%rcx),%xmm6
pcmpgtb %xmm4,%xmm6
pcmpgtb %xmm14,%xmm6
pcmpgtb (%rcx),%xmm6
pcmpgtw %xmm4,%xmm6
pcmpgtw %xmm14,%xmm6
pcmpgtw (%rcx),%xmm6
pcmpgtd %xmm4,%xmm6
pcmpgtd %xmm14,%xmm6
pcmpgtd (%rcx),%xmm6
pcmpgtq %xmm4,%xmm6
pcmpgtq (%rcx),%xmm6
@ -194,16 +226,19 @@ _start:
phsubsw %xmm4,%xmm6
phsubsw (%rcx),%xmm6
pmaddwd %xmm4,%xmm6
pmaddwd %xmm14,%xmm6
pmaddwd (%rcx),%xmm6
pmaddubsw %xmm4,%xmm6
pmaddubsw (%rcx),%xmm6
pmaxsb %xmm4,%xmm6
pmaxsb (%rcx),%xmm6
pmaxsw %xmm4,%xmm6
pmaxsw %xmm14,%xmm6
pmaxsw (%rcx),%xmm6
pmaxsd %xmm4,%xmm6
pmaxsd (%rcx),%xmm6
pmaxub %xmm4,%xmm6
pmaxub %xmm14,%xmm6
pmaxub (%rcx),%xmm6
pmaxuw %xmm4,%xmm6
pmaxuw (%rcx),%xmm6
@ -212,30 +247,37 @@ _start:
pminsb %xmm4,%xmm6
pminsb (%rcx),%xmm6
pminsw %xmm4,%xmm6
pminsw %xmm14,%xmm6
pminsw (%rcx),%xmm6
pminsd %xmm4,%xmm6
pminsd (%rcx),%xmm6
pminub %xmm4,%xmm6
pminub %xmm14,%xmm6
pminub (%rcx),%xmm6
pminuw %xmm4,%xmm6
pminuw (%rcx),%xmm6
pminud %xmm4,%xmm6
pminud (%rcx),%xmm6
pmulhuw %xmm4,%xmm6
pmulhuw %xmm14,%xmm6
pmulhuw (%rcx),%xmm6
pmulhrsw %xmm4,%xmm6
pmulhrsw (%rcx),%xmm6
pmulhw %xmm4,%xmm6
pmulhw %xmm14,%xmm6
pmulhw (%rcx),%xmm6
pmullw %xmm4,%xmm6
pmullw %xmm14,%xmm6
pmullw (%rcx),%xmm6
pmulld %xmm4,%xmm6
pmulld (%rcx),%xmm6
pmuludq %xmm4,%xmm6
pmuludq %xmm14,%xmm6
pmuludq (%rcx),%xmm6
pmuldq %xmm4,%xmm6
pmuldq (%rcx),%xmm6
por %xmm4,%xmm6
por %xmm14,%xmm6
por (%rcx),%xmm6
psadbw %xmm4,%xmm6
psadbw (%rcx),%xmm6
@ -296,6 +338,7 @@ _start:
punpcklqdq %xmm4,%xmm6
punpcklqdq (%rcx),%xmm6
pxor %xmm4,%xmm6
pxor %xmm14,%xmm6
pxor (%rcx),%xmm6
subpd %xmm4,%xmm6
subpd (%rcx),%xmm6
@ -310,8 +353,10 @@ _start:
unpcklps %xmm4,%xmm6
unpcklps (%rcx),%xmm6
xorpd %xmm4,%xmm6
xorpd %xmm14,%xmm6
xorpd (%rcx),%xmm6
xorps %xmm4,%xmm6
xorps %xmm14,%xmm6
xorps (%rcx),%xmm6
aesenc %xmm4,%xmm6
aesenc (%rcx),%xmm6
@ -322,36 +367,52 @@ _start:
aesdeclast %xmm4,%xmm6
aesdeclast (%rcx),%xmm6
cmpeqpd %xmm4,%xmm6
cmpeqpd %xmm14,%xmm6
cmpeqpd (%rcx),%xmm6
cmpeqps %xmm4,%xmm6
cmpeqps %xmm14,%xmm6
cmpeqps (%rcx),%xmm6
cmpltpd %xmm4,%xmm6
cmpltpd %xmm14,%xmm6
cmpltpd (%rcx),%xmm6
cmpltps %xmm4,%xmm6
cmpltps %xmm14,%xmm6
cmpltps (%rcx),%xmm6
cmplepd %xmm4,%xmm6
cmplepd %xmm14,%xmm6
cmplepd (%rcx),%xmm6
cmpleps %xmm4,%xmm6
cmpleps %xmm14,%xmm6
cmpleps (%rcx),%xmm6
cmpunordpd %xmm4,%xmm6
cmpunordpd %xmm14,%xmm6
cmpunordpd (%rcx),%xmm6
cmpunordps %xmm4,%xmm6
cmpunordps %xmm14,%xmm6
cmpunordps (%rcx),%xmm6
cmpneqpd %xmm4,%xmm6
cmpneqpd %xmm14,%xmm6
cmpneqpd (%rcx),%xmm6
cmpneqps %xmm4,%xmm6
cmpneqps %xmm14,%xmm6
cmpneqps (%rcx),%xmm6
cmpnltpd %xmm4,%xmm6
cmpnltpd %xmm14,%xmm6
cmpnltpd (%rcx),%xmm6
cmpnltps %xmm4,%xmm6
cmpnltps %xmm14,%xmm6
cmpnltps (%rcx),%xmm6
cmpnlepd %xmm4,%xmm6
cmpnlepd %xmm14,%xmm6
cmpnlepd (%rcx),%xmm6
cmpnleps %xmm4,%xmm6
cmpnleps %xmm14,%xmm6
cmpnleps (%rcx),%xmm6
cmpordpd %xmm4,%xmm6
cmpordpd %xmm14,%xmm6
cmpordpd (%rcx),%xmm6
cmpordps %xmm4,%xmm6
cmpordps %xmm14,%xmm6
cmpordps (%rcx),%xmm6
# Tests for op imm8, xmm/mem128, xmm
@ -386,8 +447,10 @@ _start:
blendps $100,%xmm4,%xmm6
blendps $100,(%rcx),%xmm6
cmppd $100,%xmm4,%xmm6
cmppd $100,%xmm14,%xmm6
cmppd $100,(%rcx),%xmm6
cmpps $100,%xmm4,%xmm6
cmpps $100,%xmm14,%xmm6
cmpps $100,(%rcx),%xmm6
dppd $100,%xmm4,%xmm6
dppd $100,(%rcx),%xmm6
@ -422,6 +485,7 @@ _start:
# Tests for op xmm/mem64, xmm
comisd %xmm4,%xmm6
comisd %xmm14,%xmm6
comisd (%rcx),%xmm4
cvtdq2pd %xmm4,%xmm6
cvtdq2pd (%rcx),%xmm4
@ -442,6 +506,7 @@ _start:
pmovzxdq %xmm4,%xmm6
pmovzxdq (%rcx),%xmm4
ucomisd %xmm4,%xmm6
ucomisd %xmm14,%xmm6
ucomisd (%rcx),%xmm4
# Tests for op mem64, xmm
@ -497,56 +562,73 @@ _start:
# Tests for op imm8, xmm/mem64, xmm[, xmm]
cmpsd $100,%xmm4,%xmm6
cmpsd $100,%xmm14,%xmm6
cmpsd $100,(%rcx),%xmm6
roundsd $100,%xmm4,%xmm6
roundsd $100,(%rcx),%xmm6
# Tests for op xmm/mem64, xmm[, xmm]
addsd %xmm4,%xmm6
addsd %xmm14,%xmm6
addsd (%rcx),%xmm6
cvtsd2ss %xmm4,%xmm6
cvtsd2ss (%rcx),%xmm6
divsd %xmm4,%xmm6
divsd (%rcx),%xmm6
maxsd %xmm4,%xmm6
maxsd %xmm14,%xmm6
maxsd (%rcx),%xmm6
minsd %xmm4,%xmm6
minsd %xmm14,%xmm6
minsd (%rcx),%xmm6
mulsd %xmm4,%xmm6
mulsd %xmm14,%xmm6
mulsd (%rcx),%xmm6
sqrtsd %xmm4,%xmm6
sqrtsd (%rcx),%xmm6
subsd %xmm4,%xmm6
subsd (%rcx),%xmm6
cmpeqsd %xmm4,%xmm6
cmpeqsd %xmm14,%xmm6
cmpeqsd (%rcx),%xmm6
cmpltsd %xmm4,%xmm6
cmpltsd %xmm14,%xmm6
cmpltsd (%rcx),%xmm6
cmplesd %xmm4,%xmm6
cmplesd %xmm14,%xmm6
cmplesd (%rcx),%xmm6
cmpunordsd %xmm4,%xmm6
cmpunordsd %xmm14,%xmm6
cmpunordsd (%rcx),%xmm6
cmpneqsd %xmm4,%xmm6
cmpneqsd %xmm14,%xmm6
cmpneqsd (%rcx),%xmm6
cmpnltsd %xmm4,%xmm6
cmpnltsd %xmm14,%xmm6
cmpnltsd (%rcx),%xmm6
cmpnlesd %xmm4,%xmm6
cmpnlesd %xmm14,%xmm6
cmpnlesd (%rcx),%xmm6
cmpordsd %xmm4,%xmm6
cmpordsd %xmm14,%xmm6
cmpordsd (%rcx),%xmm6
# Tests for op xmm/mem32, xmm[, xmm]
addss %xmm4,%xmm6
addss %xmm14,%xmm6
addss (%rcx),%xmm6
cvtss2sd %xmm4,%xmm6
cvtss2sd (%rcx),%xmm6
divss %xmm4,%xmm6
divss (%rcx),%xmm6
maxss %xmm4,%xmm6
maxss %xmm14,%xmm6
maxss (%rcx),%xmm6
minss %xmm4,%xmm6
minss %xmm14,%xmm6
minss (%rcx),%xmm6
mulss %xmm4,%xmm6
mulss %xmm14,%xmm6
mulss (%rcx),%xmm6
rcpss %xmm4,%xmm6
rcpss (%rcx),%xmm6
@ -557,24 +639,33 @@ _start:
subss %xmm4,%xmm6
subss (%rcx),%xmm6
cmpeqss %xmm4,%xmm6
cmpeqss %xmm14,%xmm6
cmpeqss (%rcx),%xmm6
cmpltss %xmm4,%xmm6
cmpltss %xmm14,%xmm6
cmpltss (%rcx),%xmm6
cmpless %xmm4,%xmm6
cmpless %xmm14,%xmm6
cmpless (%rcx),%xmm6
cmpunordss %xmm4,%xmm6
cmpunordss %xmm14,%xmm6
cmpunordss (%rcx),%xmm6
cmpneqss %xmm4,%xmm6
cmpneqss %xmm14,%xmm6
cmpneqss (%rcx),%xmm6
cmpnltss %xmm4,%xmm6
cmpnltss %xmm14,%xmm6
cmpnltss (%rcx),%xmm6
cmpnless %xmm4,%xmm6
cmpnless %xmm14,%xmm6
cmpnless (%rcx),%xmm6
cmpordss %xmm4,%xmm6
cmpordss %xmm14,%xmm6
cmpordss (%rcx),%xmm6
# Tests for op xmm/mem32, xmm
comiss %xmm4,%xmm6
comiss %xmm14,%xmm6
comiss (%rcx),%xmm4
pmovsxbd %xmm4,%xmm6
pmovsxbd (%rcx),%xmm4
@ -585,6 +676,7 @@ _start:
pmovzxwq %xmm4,%xmm6
pmovzxwq (%rcx),%xmm4
ucomiss %xmm4,%xmm6
ucomiss %xmm14,%xmm6
ucomiss (%rcx),%xmm4
# Tests for op mem32, xmm
@ -634,6 +726,7 @@ _start:
# Tests for op imm8, xmm/mem32, xmm[, xmm]
cmpss $100,%xmm4,%xmm6
cmpss $100,%xmm14,%xmm6
cmpss $100,(%rcx),%xmm6
insertps $100,%xmm4,%xmm6
insertps $100,(%rcx),%xmm6

32
opcodes/ChangeLog
View File

@ -1,3 +1,35 @@
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (C): New.
(paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
flavors.
* i386-tbl.h: Re-generate.
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (and, or): Add Optimize to forms allowing two

339
opcodes/i386-opc.tbl
View File

@ -40,6 +40,11 @@
#define EVexLIG EVex=EVEXLIG
#define EVexDYN EVex=EVEXDYN
// The EVEX purpose of StaticRounding appears only together with SAE. Re-use
// the bit to mark commutative VEX encodings where swapping the source
// operands may allow to switch from 3-byte to 2-byte VEX encoding.
#define C StaticRounding
### MARKER ###
// Move instructions.
@ -997,43 +1002,43 @@ packsswb, 2, 0xf63, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No
packuswb, 2, 0x6667, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
packuswb, 2, 0x660f67, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
packuswb, 2, 0xf67, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
paddb, 2, 0x66fc, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddb, 2, 0x66fc, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddb, 2, 0x660ffc, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddb, 2, 0xffc, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
paddw, 2, 0x66fd, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddw, 2, 0x66fd, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddw, 2, 0x660ffd, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddw, 2, 0xffd, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
paddd, 2, 0x66fe, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddd, 2, 0x66fe, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddd, 2, 0x660ffe, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddd, 2, 0xffe, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
paddq, 2, 0x66d4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddq, 2, 0x66d4, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddq, 2, 0x660fd4, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddq, 2, 0xfd4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
paddsb, 2, 0x66ec, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddsb, 2, 0x66ec, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddsb, 2, 0x660fec, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddsb, 2, 0xfec, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
paddsw, 2, 0x66ed, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddsw, 2, 0x66ed, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddsw, 2, 0x660fed, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddsw, 2, 0xfed, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
paddusb, 2, 0x66dc, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddusb, 2, 0x66dc, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddusb, 2, 0x660fdc, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddusb, 2, 0xfdc, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
paddusw, 2, 0x66dd, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddusw, 2, 0x66dd, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddusw, 2, 0x660fdd, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
paddusw, 2, 0xfdd, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pand, 2, 0x66db, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pand, 2, 0x66db, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pand, 2, 0x660fdb, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pand, 2, 0xfdb, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pandn, 2, 0x66df, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pandn, 2, 0x660fdf, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pandn, 2, 0xfdf, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pcmpeqb, 2, 0x6674, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqb, 2, 0x6674, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqb, 2, 0x660f74, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqb, 2, 0xf74, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pcmpeqw, 2, 0x6675, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqw, 2, 0x6675, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqw, 2, 0x660f75, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqw, 2, 0xf75, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pcmpeqd, 2, 0x6676, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqd, 2, 0x6676, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqd, 2, 0x660f76, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqd, 2, 0xf76, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pcmpgtb, 2, 0x6664, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
@ -1045,16 +1050,16 @@ pcmpgtw, 2, 0xf65, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_
pcmpgtd, 2, 0x6666, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpgtd, 2, 0x660f66, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpgtd, 2, 0xf66, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pmaddwd, 2, 0x66f5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmaddwd, 2, 0x66f5, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmaddwd, 2, 0x660ff5, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmaddwd, 2, 0xff5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pmulhw, 2, 0x66e5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmulhw, 2, 0x66e5, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmulhw, 2, 0x660fe5, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmulhw, 2, 0xfe5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pmullw, 2, 0x66d5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmullw, 2, 0x66d5, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmullw, 2, 0x660fd5, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmullw, 2, 0xfd5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
por, 2, 0x66eb, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
por, 2, 0x66eb, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
por, 2, 0x660feb, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
por, 2, 0xfeb, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
psllw, 2, 0x6671, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
@ -1147,7 +1152,7 @@ punpcklwd, 2, 0xf61, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N
punpckldq, 2, 0x6662, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
punpckldq, 2, 0x660f62, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
punpckldq, 2, 0xf62, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX }
pxor, 2, 0x66ef, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pxor, 2, 0x66ef, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pxor, 2, 0x660fef, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pxor, 2, 0xfef, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
@ -1159,11 +1164,11 @@ addss, 2, 0xf358, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|Igno
addss, 2, 0xf30f58, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
andnps, 2, 0x55, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
andnps, 2, 0xf55, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
andps, 2, 0x54, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
andps, 2, 0x54, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
andps, 2, 0xf54, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpeqps, 2, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpeqps, 2, 0xc2, 0x0, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpeqps, 2, 0xfc2, 0x0, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpeqss, 2, 0xf3c2, 0x0, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpeqss, 2, 0xf3c2, 0x0, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpeqss, 2, 0xf30fc2, 0x0, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpleps, 2, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpleps, 2, 0xfc2, 0x2, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
@ -1173,9 +1178,9 @@ cmpltps, 2, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf
cmpltps, 2, 0xfc2, 0x1, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpltss, 2, 0xf3c2, 0x1, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpltss, 2, 0xf30fc2, 0x1, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpneqps, 2, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpneqps, 2, 0xc2, 0x4, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpneqps, 2, 0xfc2, 0x4, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpneqss, 2, 0xf3c2, 0x4, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpneqss, 2, 0xf3c2, 0x4, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpneqss, 2, 0xf30fc2, 0x4, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpnleps, 2, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpnleps, 2, 0xfc2, 0x6, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
@ -1185,13 +1190,13 @@ cmpnltps, 2, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSu
cmpnltps, 2, 0xfc2, 0x5, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpnltss, 2, 0xf3c2, 0x5, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpnltss, 2, 0xf30fc2, 0x5, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpordps, 2, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpordps, 2, 0xc2, 0x7, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpordps, 2, 0xfc2, 0x7, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpordss, 2, 0xf3c2, 0x7, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpordss, 2, 0xf3c2, 0x7, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpordss, 2, 0xf30fc2, 0x7, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpunordps, 2, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpunordps, 2, 0xc2, 0x3, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpunordps, 2, 0xfc2, 0x3, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpunordss, 2, 0xf3c2, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpunordss, 2, 0xf3c2, 0x3, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpunordss, 2, 0xf30fc2, 0x3, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpps, 3, 0xc2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
cmpps, 3, 0xfc2, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
@ -1253,13 +1258,13 @@ mulps, 2, 0x59, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|
mulps, 2, 0xf59, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
mulss, 2, 0xf359, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
mulss, 2, 0xf30f59, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
orps, 2, 0x56, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
orps, 2, 0x56, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
orps, 2, 0xf56, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pavgb, 2, 0xfe0, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pavgb, 2, 0x66e0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pavgb, 2, 0x66e0, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pavgb, 2, 0x660fe0, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pavgw, 2, 0xfe3, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pavgw, 2, 0x66e3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pavgw, 2, 0x66e3, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pavgw, 2, 0x660fe3, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pextrw, 3, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|RegMem }
@ -1274,22 +1279,22 @@ pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|
pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM }
pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, Reg32|Reg64, RegMMX }
pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoAVX, { Imm8, Word|Unspecified|BaseIndex, RegMMX }
pmaxsw, 2, 0x66ee, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmaxsw, 2, 0x66ee, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmaxsw, 2, 0x660fee, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmaxsw, 2, 0xfee, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pmaxub, 2, 0x66de, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmaxub, 2, 0x66de, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmaxub, 2, 0x660fde, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmaxub, 2, 0xfde, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pminsw, 2, 0x66ea, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pminsw, 2, 0x66ea, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pminsw, 2, 0x660fea, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pminsw, 2, 0xfea, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pminub, 2, 0x66da, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pminub, 2, 0x66da, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pminub, 2, 0x660fda, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pminub, 2, 0xfda, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 }
pmovmskb, 2, 0x660fd7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
pmovmskb, 2, 0xfd7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { RegMMX, Reg32|Reg64 }
pmulhuw, 2, 0x66e4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmulhuw, 2, 0x66e4, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmulhuw, 2, 0x660fe4, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmulhuw, 2, 0xfe4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
prefetchnta, 1, 0xf18, 0x0, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Anysize|BaseIndex }
@ -1327,7 +1332,7 @@ unpckhps, 2, 0x15, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bS
unpckhps, 2, 0xf15, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
unpcklps, 2, 0x14, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
unpcklps, 2, 0xf14, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
xorps, 2, 0x57, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
xorps, 2, 0x57, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
xorps, 2, 0xf57, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
// SSE2 instructions.
@ -1338,11 +1343,11 @@ addsd, 2, 0xf258, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|Igno
addsd, 2, 0xf20f58, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
andnpd, 2, 0x6655, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
andnpd, 2, 0x660f55, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
andpd, 2, 0x6654, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
andpd, 2, 0x6654, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
andpd, 2, 0x660f54, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpeqpd, 2, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpeqpd, 2, 0x66c2, 0x0, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpeqpd, 2, 0x660fc2, 0x0, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpeqsd, 2, 0xf2c2, 0x0, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpeqsd, 2, 0xf2c2, 0x0, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpeqsd, 2, 0xf20fc2, 0x0, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmplepd, 2, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmplepd, 2, 0x660fc2, 0x2, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
@ -1352,9 +1357,9 @@ cmpltpd, 2, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bS
cmpltpd, 2, 0x660fc2, 0x1, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpltsd, 2, 0xf2c2, 0x1, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpltsd, 2, 0xf20fc2, 0x1, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpneqpd, 2, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpneqpd, 2, 0x66c2, 0x4, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpneqpd, 2, 0x660fc2, 0x4, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpneqsd, 2, 0xf2c2, 0x4, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpneqsd, 2, 0xf2c2, 0x4, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpneqsd, 2, 0xf20fc2, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpnlepd, 2, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpnlepd, 2, 0x660fc2, 0x6, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
@ -1364,13 +1369,13 @@ cmpnltpd, 2, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_b
cmpnltpd, 2, 0x660fc2, 0x5, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpnltsd, 2, 0xf2c2, 0x5, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpnltsd, 2, 0xf20fc2, 0x5, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpordpd, 2, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpordpd, 2, 0x66c2, 0x7, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpordpd, 2, 0x660fc2, 0x7, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpordsd, 2, 0xf2c2, 0x7, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpordsd, 2, 0xf2c2, 0x7, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpordsd, 2, 0xf20fc2, 0x7, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpunordpd, 2, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpunordpd, 2, 0x66c2, 0x3, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpunordpd, 2, 0x660fc2, 0x3, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
cmpunordsd, 2, 0xf2c2, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpunordsd, 2, 0xf2c2, 0x3, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmpunordsd, 2, 0xf20fc2, 0x3, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cmppd, 3, 0x66c2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
cmppd, 3, 0x660fc2, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
@ -1422,7 +1427,7 @@ mulpd, 2, 0x6659, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSu
mulpd, 2, 0x660f59, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
mulsd, 2, 0xf259, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
mulsd, 2, 0xf20f59, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
orpd, 2, 0x6656, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
orpd, 2, 0x6656, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
orpd, 2, 0x660f56, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
shufpd, 3, 0x66c6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
shufpd, 3, 0x660fc6, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
@ -1440,7 +1445,7 @@ unpckhpd, 2, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_
unpckhpd, 2, 0x660f15, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
unpcklpd, 2, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
unpcklpd, 2, 0x660f14, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
xorpd, 2, 0x6657, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
xorpd, 2, 0x6657, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
xorpd, 2, 0x660f57, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
cvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cvtdq2pd, 2, 0xf30fe6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
@ -1476,7 +1481,7 @@ movdqu, 2, 0xf36f, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wS
movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX }
movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM }
pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmuludq, 2, 0x660ff4, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pmuludq, 2, 0xff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pshufd, 3, 0x6670, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
@ -1818,8 +1823,8 @@ vaddsubpd, 3, 0x66d0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|Ch
vaddsubps, 3, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vandnpd, 3, 0x6655, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vandnps, 3, 0x55, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vandpd, 3, 0x6654, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vandps, 3, 0x54, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vandpd, 3, 0x6654, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vandps, 3, 0x54, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vblendpd, 4, 0x660d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vblendps, 4, 0x660c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vblendvpd, 4, 0x664b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
@ -1827,30 +1832,30 @@ vblendvps, 4, 0x664a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|Ve
vbroadcastf128, 2, 0x661a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
vbroadcastsd, 2, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM }
vbroadcastss, 2, 0x6618, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM }
vcmpeq_ospd, 3, 0x66c2, 0x10, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_osps, 3, 0xc2, 0x10, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_ossd, 3, 0xf2c2, 0x10, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_osss, 3, 0xf3c2, 0x10, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeqpd, 3, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeqps, 3, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeqsd, 3, 0xf2c2, 0x0, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeqss, 3, 0xf3c2, 0x0, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_uqpd, 3, 0x66c2, 0x8, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_uqps, 3, 0xc2, 0x8, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_uqsd, 3, 0xf2c2, 0x8, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_uqss, 3, 0xf3c2, 0x8, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_uspd, 3, 0x66c2, 0x18, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_usps, 3, 0xc2, 0x18, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_ussd, 3, 0xf2c2, 0x18, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_usss, 3, 0xf3c2, 0x18, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpfalse_ospd, 3, 0x66c2, 0x1b, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpfalse_osps, 3, 0xc2, 0x1b, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpfalse_ossd, 3, 0xf2c2, 0x1b, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpfalse_osss, 3, 0xf3c2, 0x1b, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpfalsepd, 3, 0x66c2, 0xb, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpfalseps, 3, 0xc2, 0xb, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpfalsesd, 3, 0xf2c2, 0xb, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpfalsess, 3, 0xf3c2, 0xb, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_ospd, 3, 0x66c2, 0x10, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_osps, 3, 0xc2, 0x10, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_ossd, 3, 0xf2c2, 0x10, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_osss, 3, 0xf3c2, 0x10, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeqpd, 3, 0x66c2, 0x0, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeqps, 3, 0xc2, 0x0, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeqsd, 3, 0xf2c2, 0x0, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeqss, 3, 0xf3c2, 0x0, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_uqpd, 3, 0x66c2, 0x8, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_uqps, 3, 0xc2, 0x8, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_uqsd, 3, 0xf2c2, 0x8, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_uqss, 3, 0xf3c2, 0x8, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_uspd, 3, 0x66c2, 0x18, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_usps, 3, 0xc2, 0x18, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpeq_ussd, 3, 0xf2c2, 0x18, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpeq_usss, 3, 0xf3c2, 0x18, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpfalse_ospd, 3, 0x66c2, 0x1b, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpfalse_osps, 3, 0xc2, 0x1b, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpfalse_ossd, 3, 0xf2c2, 0x1b, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpfalse_osss, 3, 0xf3c2, 0x1b, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpfalsepd, 3, 0x66c2, 0xb, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpfalseps, 3, 0xc2, 0xb, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpfalsesd, 3, 0xf2c2, 0xb, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpfalsess, 3, 0xf3c2, 0xb, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpge_oqpd, 3, 0x66c2, 0x1d, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpge_oqps, 3, 0xc2, 0x1d, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpge_oqsd, 3, 0xf2c2, 0x1d, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@ -1883,22 +1888,22 @@ vcmpltpd, 3, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|Chec
vcmpltps, 3, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpltsd, 3, 0xf2c2, 0x1, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpltss, 3, 0xf3c2, 0x1, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_oqpd, 3, 0x66c2, 0xc, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_oqps, 3, 0xc2, 0xc, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_oqsd, 3, 0xf2c2, 0xc, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_oqss, 3, 0xf3c2, 0xc, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_ospd, 3, 0x66c2, 0x1c, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_osps, 3, 0xc2, 0x1c, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_ossd, 3, 0xf2c2, 0x1c, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_osss, 3, 0xf3c2, 0x1c, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneqpd, 3, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneqps, 3, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneqsd, 3, 0xf2c2, 0x4, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneqss, 3, 0xf3c2, 0x4, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_uspd, 3, 0x66c2, 0x14, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_usps, 3, 0xc2, 0x14, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_ussd, 3, 0xf2c2, 0x14, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_usss, 3, 0xf3c2, 0x14, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_oqpd, 3, 0x66c2, 0xc, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_oqps, 3, 0xc2, 0xc, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_oqsd, 3, 0xf2c2, 0xc, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_oqss, 3, 0xf3c2, 0xc, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_ospd, 3, 0x66c2, 0x1c, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_osps, 3, 0xc2, 0x1c, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_ossd, 3, 0xf2c2, 0x1c, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_osss, 3, 0xf3c2, 0x1c, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneqpd, 3, 0x66c2, 0x4, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneqps, 3, 0xc2, 0x4, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneqsd, 3, 0xf2c2, 0x4, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneqss, 3, 0xf3c2, 0x4, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_uspd, 3, 0x66c2, 0x14, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_usps, 3, 0xc2, 0x14, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpneq_ussd, 3, 0xf2c2, 0x14, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpneq_usss, 3, 0xf3c2, 0x14, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpngepd, 3, 0x66c2, 0x9, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpngeps, 3, 0xc2, 0x9, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpngesd, 3, 0xf2c2, 0x9, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@ -1931,34 +1936,34 @@ vcmpnlt_uqpd, 3, 0x66c2, 0x15, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG
vcmpnlt_uqps, 3, 0xc2, 0x15, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpnlt_uqsd, 3, 0xf2c2, 0x15, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpnlt_uqss, 3, 0xf3c2, 0x15, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpordpd, 3, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpordps, 3, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpordsd, 3, 0xf2c2, 0x7, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpord_spd, 3, 0x66c2, 0x17, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpord_sps, 3, 0xc2, 0x17, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpordss, 3, 0xf3c2, 0x7, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpord_ssd, 3, 0xf2c2, 0x17, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpord_sss, 3, 0xf3c2, 0x17, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpordpd, 3, 0x66c2, 0x7, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpordps, 3, 0xc2, 0x7, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpordsd, 3, 0xf2c2, 0x7, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpord_spd, 3, 0x66c2, 0x17, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpord_sps, 3, 0xc2, 0x17, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpordss, 3, 0xf3c2, 0x7, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpord_ssd, 3, 0xf2c2, 0x17, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpord_sss, 3, 0xf3c2, 0x17, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmppd, 4, 0x66c2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpps, 4, 0xc2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpsd, 4, 0xf2c2, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpss, 4, 0xf3c2, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmptruepd, 3, 0x66c2, 0xf, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmptrueps, 3, 0xc2, 0xf, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmptruesd, 3, 0xf2c2, 0xf, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmptruess, 3, 0xf3c2, 0xf, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmptrue_uspd, 3, 0x66c2, 0x1f, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmptrue_usps, 3, 0xc2, 0x1f, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmptrue_ussd, 3, 0xf2c2, 0x1f, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmptrue_usss, 3, 0xf3c2, 0x1f, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpunordpd, 3, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpunordps, 3, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpunordsd, 3, 0xf2c2, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpunord_spd, 3, 0x66c2, 0x13, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpunord_sps, 3, 0xc2, 0x13, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpunordss, 3, 0xf3c2, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpunord_ssd, 3, 0xf2c2, 0x13, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpunord_sss, 3, 0xf3c2, 0x13, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmptruepd, 3, 0x66c2, 0xf, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmptrueps, 3, 0xc2, 0xf, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmptruesd, 3, 0xf2c2, 0xf, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmptruess, 3, 0xf3c2, 0xf, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmptrue_uspd, 3, 0x66c2, 0x1f, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmptrue_usps, 3, 0xc2, 0x1f, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmptrue_ussd, 3, 0xf2c2, 0x1f, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmptrue_usss, 3, 0xf3c2, 0x1f, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpunordpd, 3, 0x66c2, 0x3, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpunordps, 3, 0xc2, 0x3, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpunordsd, 3, 0xf2c2, 0x3, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpunord_spd, 3, 0x66c2, 0x13, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpunord_sps, 3, 0xc2, 0x13, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpunordss, 3, 0xf3c2, 0x3, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpunord_ssd, 3, 0xf2c2, 0x13, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpunord_sss, 3, 0xf3c2, 0x13, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcomisd, 2, 0x662f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vcomiss, 2, 0x2f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegYMM }
@ -2064,8 +2069,8 @@ vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|Check
vmulps, 3, 0x59, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vmulsd, 3, 0xf259, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vmulss, 3, 0xf359, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vorpd, 3, 0x6656, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vorps, 3, 0x56, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vorpd, 3, 0x6656, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vorps, 3, 0x56, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpabsb, 2, 0x661c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
vpabsd, 2, 0x661e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
vpabsw, 2, 0x661d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
@ -2073,25 +2078,25 @@ vpackssdw, 3, 0x666b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No
vpacksswb, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpackusdw, 3, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpackuswb, 3, 0x6667, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddsb, 3, 0x66ec, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddsw, 3, 0x66ed, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddb, 3, 0x66fc, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddd, 3, 0x66fe, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddq, 3, 0x66d4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddw, 3, 0x66fd, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddusb, 3, 0x66dc, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddusw, 3, 0x66dd, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddsb, 3, 0x66ec, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddsw, 3, 0x66ed, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddb, 3, 0x66fc, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddd, 3, 0x66fe, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddq, 3, 0x66d4, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddw, 3, 0x66fd, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddusb, 3, 0x66dc, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpaddusw, 3, 0x66dd, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpalignr, 4, 0x660f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpand, 3, 0x66db, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpand, 3, 0x66db, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpandn, 3, 0x66df, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpavgb, 3, 0x66e0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpavgw, 3, 0x66e3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpavgb, 3, 0x66e0, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpavgw, 3, 0x66e3, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpblendvb, 4, 0x664c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpblendw, 4, 0x660e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpcmpeqb, 3, 0x6674, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpcmpeqd, 3, 0x6676, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpcmpeqb, 3, 0x6674, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpcmpeqd, 3, 0x6676, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpcmpeqq, 3, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpcmpeqw, 3, 0x6675, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpcmpeqw, 3, 0x6675, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpcmpestri, 3, 0x6661, None, 1, CpuAVX|CpuNo64, Modrm|Vex|VexOpcode=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
vpcmpestri, 3, 0x6661, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpcmpestrm, 3, 0x6660, None, 1, CpuAVX|CpuNo64, Modrm|Vex|VexOpcode=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
@ -2128,17 +2133,17 @@ vpinsrq, 4, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|VexVVVV=
vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
vpmaddubsw, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaddwd, 3, 0x66f5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaddwd, 3, 0x66f5, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaxsb, 3, 0x663c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaxsd, 3, 0x663d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaxsw, 3, 0x66ee, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaxub, 3, 0x66de, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaxsw, 3, 0x66ee, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaxub, 3, 0x66de, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaxud, 3, 0x663f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaxuw, 3, 0x663e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpminsb, 3, 0x6638, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpminsd, 3, 0x6639, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpminsw, 3, 0x66ea, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpminub, 3, 0x66da, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpminsw, 3, 0x66ea, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpminub, 3, 0x66da, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpminud, 3, 0x663b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpminuw, 3, 0x663a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
@ -2156,12 +2161,12 @@ vpmovzxwd, 2, 0x6633, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|IgnoreSize|N
vpmovzxwq, 2, 0x6634, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmuldq, 3, 0x6628, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmulhrsw, 3, 0x660b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmulhuw, 3, 0x66e4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmulhw, 3, 0x66e5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmulhuw, 3, 0x66e4, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmulhw, 3, 0x66e5, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmulld, 3, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmullw, 3, 0x66d5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmuludq, 3, 0x66f4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpor, 3, 0x66eb, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmullw, 3, 0x66d5, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmuludq, 3, 0x66f4, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpor, 3, 0x66eb, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpsadbw, 3, 0x66f6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpshufb, 3, 0x6600, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpshufd, 3, 0x6670, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
@ -2205,7 +2210,7 @@ vpunpcklbw, 3, 0x6660, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|N
vpunpckldq, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpunpcklqdq, 3, 0x666c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpunpcklwd, 3, 0x6661, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpxor, 3, 0x66ef, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpxor, 3, 0x66ef, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vrcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vrcpss, 3, 0xf353, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vroundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
@ -2233,8 +2238,8 @@ vunpckhpd, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|Ch
vunpckhps, 3, 0x15, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vunpcklpd, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vunpcklps, 3, 0x14, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vxorpd, 3, 0x6657, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vxorps, 3, 0x57, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vxorpd, 3, 0x6657, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vxorps, 3, 0x57, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vzeroall, 0, 0x77, None, 1, CpuAVX, Vex=2|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
vzeroupper, 0, 0x77, None, 1, CpuAVX, Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
@ -2249,25 +2254,25 @@ vpackssdw, 3, 0x666b, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG
vpacksswb, 3, 0x6663, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpackusdw, 3, 0x662b, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpackuswb, 3, 0x6667, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddsb, 3, 0x66ec, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddsw, 3, 0x66ed, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddb, 3, 0x66fc, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddd, 3, 0x66fe, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddq, 3, 0x66d4, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddw, 3, 0x66fd, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddusb, 3, 0x66dc, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddusw, 3, 0x66dd, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddsb, 3, 0x66ec, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddsw, 3, 0x66ed, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddb, 3, 0x66fc, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddd, 3, 0x66fe, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddq, 3, 0x66d4, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddw, 3, 0x66fd, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddusb, 3, 0x66dc, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpaddusw, 3, 0x66dd, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpalignr, 4, 0x660f, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpand, 3, 0x66db, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpand, 3, 0x66db, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpandn, 3, 0x66df, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpavgb, 3, 0x66e0, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpavgw, 3, 0x66e3, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpavgb, 3, 0x66e0, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpavgw, 3, 0x66e3, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpblendvb, 4, 0x664c, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexSources=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpblendw, 4, 0x660e, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpcmpeqb, 3, 0x6674, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpcmpeqd, 3, 0x6676, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpcmpeqb, 3, 0x6674, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpcmpeqd, 3, 0x6676, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpcmpeqq, 3, 0x6629, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpcmpeqw, 3, 0x6675, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpcmpeqw, 3, 0x6675, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpcmpgtb, 3, 0x6664, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpcmpgtd, 3, 0x6666, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpcmpgtq, 3, 0x6637, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
@ -2279,17 +2284,17 @@ vphsubd, 3, 0x6606, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|N
vphsubsw, 3, 0x6607, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vphsubw, 3, 0x6605, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaddubsw, 3, 0x6604, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaddwd, 3, 0x66f5, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaddwd, 3, 0x66f5, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaxsb, 3, 0x663c, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaxsd, 3, 0x663d, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaxsw, 3, 0x66ee, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaxub, 3, 0x66de, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaxsw, 3, 0x66ee, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaxub, 3, 0x66de, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaxud, 3, 0x663f, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmaxuw, 3, 0x663e, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpminsb, 3, 0x6638, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpminsd, 3, 0x6639, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpminsw, 3, 0x66ea, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpminub, 3, 0x66da, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpminsw, 3, 0x66ea, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpminub, 3, 0x66da, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpminud, 3, 0x663b, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpminuw, 3, 0x663a, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmovmskb, 2, 0x66d7, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 }
@ -2307,12 +2312,12 @@ vpmovzxwd, 2, 0x6633, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexWIG|No_bSuf|N
vpmovzxwq, 2, 0x6634, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
vpmuldq, 3, 0x6628, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmulhrsw, 3, 0x660b, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmulhuw, 3, 0x66e4, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmulhw, 3, 0x66e5, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmulhuw, 3, 0x66e4, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmulhw, 3, 0x66e5, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmulld, 3, 0x6640, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmullw, 3, 0x66d5, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmuludq, 3, 0x66f4, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpor, 3, 0x66eb, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmullw, 3, 0x66d5, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmuludq, 3, 0x66f4, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpor, 3, 0x66eb, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpsadbw, 3, 0x66f6, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpshufb, 3, 0x6600, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpshufd, 3, 0x6670, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM }
@ -2355,7 +2360,7 @@ vpunpcklbw, 3, 0x6660, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWI
vpunpckldq, 3, 0x6662, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpunpcklqdq, 3, 0x666c, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpunpcklwd, 3, 0x6661, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpxor, 3, 0x66ef, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpxor, 3, 0x66ef, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
// New AVX2 instructions.

334
opcodes/i386-tbl.h
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