MatCat.OpenSource/8sa1-binutils-gdb
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Remove support for the (deprecated) openrisc and or32 configurations and replace

Browse Source 
with support for the new or1k configuration.
This commit is contained in:
Christian Svensson 2014-04-22 15:57:47 +01:00 committed by Nick Clifton
parent a75fef0e5b
commit 73589c9dbd
135 changed files with 12474 additions and 9221 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
bfd/ChangeLog
View File

@ -1,3 +1,24 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* Makefile.am: Remove openrisc and or32 support. Add support for or1k.
* archures.c: Likewise.
* coffcode.h: Likewise.
* config.bfd: Likewise.
* configure.in: Likewise.
* reloc.c: Likewise.
* targets.c: Likewise.
* cpu-or1k.c: New file.
* elf32-or1k.c: New file.
* coff-or32.c: Delete.
* cpu-openrisc.c: Delete.
* cpu-or32.c: Delete.
* elf32-openrisc.c: Delete.
* elf32-or32.c: Delete.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
2014-04-22 Yuanhui Zhang <asmwarrior@gmail.com>
PR ld/16821

14
bfd/Makefile.am
View File

@ -139,8 +139,7 @@ ALL_MACHINES = \
cpu-nds32.lo \
cpu-nios2.lo \
cpu-ns32k.lo \
cpu-openrisc.lo \
cpu-or32.lo \
cpu-or1k.lo \
cpu-pdp11.lo \
cpu-pj.lo \
cpu-plugin.lo \
@ -224,8 +223,7 @@ ALL_MACHINES_CFILES = \
cpu-nds32.c \
cpu-ns32k.c \
cpu-nios2.c \
cpu-openrisc.c \
cpu-or32.c \
cpu-or1k.c \
cpu-pdp11.c \
cpu-pj.c \
cpu-plugin.c \
@ -284,7 +282,6 @@ BFD32_BACKENDS = \
coff-m68k.lo \
coff-m88k.lo \
coff-mips.lo \
coff-or32.lo \
coff-rs6000.lo \
coff-sh.lo \
coff-sparc.lo \
@ -353,8 +350,7 @@ BFD32_BACKENDS = \
elf32-mt.lo \
elf32-nds32.lo \
elf32-nios2.lo \
elf32-openrisc.lo \
elf32-or32.lo \
elf32-or1k.lo \
elf32-pj.lo \
elf32-ppc.lo \
elf32-rl78.lo \
@ -473,7 +469,6 @@ BFD32_BACKENDS_CFILES = \
coff-m68k.c \
coff-m88k.c \
coff-mips.c \
coff-or32.c \
coff-rs6000.c \
coff-sh.c \
coff-sparc.c \
@ -542,8 +537,7 @@ BFD32_BACKENDS_CFILES = \
elf32-mt.c \
elf32-nds32.c \
elf32-nios2.c \
elf32-openrisc.c \
elf32-or32.c \
elf32-or1k.c \
elf32-pj.c \
elf32-ppc.c \
elf32-rl78.c \

21
bfd/Makefile.in
View File

@ -440,8 +440,7 @@ ALL_MACHINES = \
cpu-nds32.lo \
cpu-nios2.lo \
cpu-ns32k.lo \
cpu-openrisc.lo \
cpu-or32.lo \
cpu-or1k.lo \
cpu-pdp11.lo \
cpu-pj.lo \
cpu-plugin.lo \
@ -525,8 +524,7 @@ ALL_MACHINES_CFILES = \
cpu-nds32.c \
cpu-ns32k.c \
cpu-nios2.c \
cpu-openrisc.c \
cpu-or32.c \
cpu-or1k.c \
cpu-pdp11.c \
cpu-pj.c \
cpu-plugin.c \
@ -586,7 +584,6 @@ BFD32_BACKENDS = \
coff-m68k.lo \
coff-m88k.lo \
coff-mips.lo \
coff-or32.lo \
coff-rs6000.lo \
coff-sh.lo \
coff-sparc.lo \
@ -655,8 +652,7 @@ BFD32_BACKENDS = \
elf32-mt.lo \
elf32-nds32.lo \
elf32-nios2.lo \
elf32-openrisc.lo \
elf32-or32.lo \
elf32-or1k.lo \
elf32-pj.lo \
elf32-ppc.lo \
elf32-rl78.lo \
@ -775,7 +771,6 @@ BFD32_BACKENDS_CFILES = \
coff-m68k.c \
coff-m88k.c \
coff-mips.c \
coff-or32.c \
coff-rs6000.c \
coff-sh.c \
coff-sparc.c \
@ -844,8 +839,7 @@ BFD32_BACKENDS_CFILES = \
elf32-mt.c \
elf32-nds32.c \
elf32-nios2.c \
elf32-openrisc.c \
elf32-or32.c \
elf32-or1k.c \
elf32-pj.c \
elf32-ppc.c \
elf32-rl78.c \
@ -1287,7 +1281,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-m68k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-m88k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-mips.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-or32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-rs6000.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-sh.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-sparc.Plo@am__quote@
@ -1359,8 +1352,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-nds32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-nios2.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ns32k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-openrisc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-or32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-or1k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-pdp11.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-pj.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-plugin.Plo@am__quote@
@ -1449,8 +1441,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-mt.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-nds32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-nios2.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-openrisc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or1k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-pj.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ppc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rl78.Plo@am__quote@

11
bfd/archures.c
View File

@ -121,7 +121,9 @@ DESCRIPTION
.#define bfd_mach_i960_jx 7
.#define bfd_mach_i960_hx 8
.
. bfd_arch_or32, {* OpenRISC 32 *}
. bfd_arch_or1k, {* OpenRISC 1000 *}
.#define bfd_mach_or1k 1
.#define bfd_mach_or1knd 2
.
. bfd_arch_sparc, {* SPARC *}
.#define bfd_mach_sparc 1
@ -433,7 +435,6 @@ DESCRIPTION
. bfd_arch_score, {* Sunplus score *}
.#define bfd_mach_score3 3
.#define bfd_mach_score7 7
. bfd_arch_openrisc, {* OpenRISC *}
. bfd_arch_mmix, {* Donald Knuth's educational processor. *}
. bfd_arch_xstormy16,
.#define bfd_mach_xstormy16 1
@ -583,8 +584,7 @@ extern const bfd_arch_info_type bfd_mt_arch;
extern const bfd_arch_info_type bfd_nds32_arch;
extern const bfd_arch_info_type bfd_nios2_arch;
extern const bfd_arch_info_type bfd_ns32k_arch;
extern const bfd_arch_info_type bfd_openrisc_arch;
extern const bfd_arch_info_type bfd_or32_arch;
extern const bfd_arch_info_type bfd_or1k_arch;
extern const bfd_arch_info_type bfd_pdp11_arch;
extern const bfd_arch_info_type bfd_pj_arch;
extern const bfd_arch_info_type bfd_plugin_arch;
@ -673,8 +673,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_nds32_arch,
&bfd_nios2_arch,
&bfd_ns32k_arch,
&bfd_openrisc_arch,
&bfd_or32_arch,
&bfd_or1k_arch,
&bfd_pdp11_arch,
&bfd_powerpc_arch,
&bfd_rs6000_arch,

33
bfd/bfd-in2.h
View File

@ -1906,7 +1906,9 @@ enum bfd_architecture
#define bfd_mach_i960_jx 7
#define bfd_mach_i960_hx 8
bfd_arch_or32, /* OpenRISC 32 */
bfd_arch_or1k, /* OpenRISC 1000 */
#define bfd_mach_or1k 1
#define bfd_mach_or1knd 2
bfd_arch_sparc, /* SPARC */
#define bfd_mach_sparc 1
@ -2218,7 +2220,6 @@ enum bfd_architecture
bfd_arch_score, /* Sunplus score */
#define bfd_mach_score3 3
#define bfd_mach_score7 7
bfd_arch_openrisc, /* OpenRISC */
bfd_arch_mmix, /* Donald Knuth's educational processor. */
bfd_arch_xstormy16,
#define bfd_mach_xstormy16 1
@ -5133,9 +5134,31 @@ a matching LO8XG part. */
BFD_RELOC_860_HIGOT,
BFD_RELOC_860_HIGOTOFF,
/* OpenRISC Relocations. */
BFD_RELOC_OPENRISC_ABS_26,
BFD_RELOC_OPENRISC_REL_26,
/* OpenRISC 1000 Relocations. */
BFD_RELOC_OR1K_REL_26,
BFD_RELOC_OR1K_GOTPC_HI16,
BFD_RELOC_OR1K_GOTPC_LO16,
BFD_RELOC_OR1K_GOT16,
BFD_RELOC_OR1K_PLT26,
BFD_RELOC_OR1K_GOTOFF_HI16,
BFD_RELOC_OR1K_GOTOFF_LO16,
BFD_RELOC_OR1K_COPY,
BFD_RELOC_OR1K_GLOB_DAT,
BFD_RELOC_OR1K_JMP_SLOT,
BFD_RELOC_OR1K_RELATIVE,
BFD_RELOC_OR1K_TLS_GD_HI16,
BFD_RELOC_OR1K_TLS_GD_LO16,
BFD_RELOC_OR1K_TLS_LDM_HI16,
BFD_RELOC_OR1K_TLS_LDM_LO16,
BFD_RELOC_OR1K_TLS_LDO_HI16,
BFD_RELOC_OR1K_TLS_LDO_LO16,
BFD_RELOC_OR1K_TLS_IE_HI16,
BFD_RELOC_OR1K_TLS_IE_LO16,
BFD_RELOC_OR1K_TLS_LE_HI16,
BFD_RELOC_OR1K_TLS_LE_LO16,
BFD_RELOC_OR1K_TLS_TPOFF,
BFD_RELOC_OR1K_TLS_DTPOFF,
BFD_RELOC_OR1K_TLS_DTPMOD,
/* H8 elf Relocations. */
BFD_RELOC_H8_DIR16A8,

628
bfd/coff-or32.c
View File

@ -1,628 +0,0 @@
/* BFD back-end for OpenRISC 1000 COFF binaries.
Copyright (C) 2002-2014 Free Software Foundation, Inc.
Contributed by Ivan Guzvinec <ivang@opencores.org>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#define OR32 1
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "coff/or32.h"
#include "coff/internal.h"
#include "libcoff.h"
static bfd_reloc_status_type or32_reloc
(bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (2)
#define INSERT_HWORD(WORD,HWORD) \
(((WORD) & 0xffff0000) | ((HWORD)& 0x0000ffff))
#define EXTRACT_HWORD(WORD) \
((WORD) & 0x0000ffff)
#define SIGN_EXTEND_HWORD(HWORD) \
((HWORD) & 0x8000 ? (HWORD)|(~0xffffL) : (HWORD))
#define INSERT_JUMPTARG(WORD,JT) \
(((WORD) & 0xfc000000) | ((JT)& 0x03ffffff))
#define EXTRACT_JUMPTARG(WORD) \
((WORD) & 0x03ffffff)
#define SIGN_EXTEND_JUMPTARG(JT) \
((JT) & 0x04000000 ? (JT)|(~0x03ffffffL) : (JT))
/* Provided the symbol, returns the value reffed. */
static long
get_symbol_value (asymbol *symbol)
{
long relocation = 0;
if (bfd_is_com_section (symbol->section))
relocation = 0;
else
relocation = symbol->value +
symbol->section->output_section->vma +
symbol->section->output_offset;
return relocation;
}
/* This function is in charge of performing all the or32 relocations. */
static bfd_reloc_status_type
or32_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol_in,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message)
{
/* The consth relocation comes in two parts, we have to remember
the state between calls, in these variables. */
static bfd_boolean part1_consth_active = FALSE;
static unsigned long part1_consth_value;
unsigned long insn;
unsigned long sym_value;
unsigned long unsigned_value;
unsigned short r_type;
long signed_value;
unsigned long addr = reloc_entry->address ; /*+ input_section->vma*/
bfd_byte *hit_data =addr + (bfd_byte *)(data);
r_type = reloc_entry->howto->type;
if (output_bfd)
{
/* Partial linking - do nothing. */
reloc_entry->address += input_section->output_offset;
return bfd_reloc_ok;
}
if (symbol_in != NULL
&& bfd_is_und_section (symbol_in->section))
{
/* Keep the state machine happy in case we're called again. */
if (r_type == R_IHIHALF)
{
part1_consth_active = TRUE;
part1_consth_value = 0;
}
return bfd_reloc_undefined;
}
if ((part1_consth_active) && (r_type != R_IHCONST))
{
part1_consth_active = FALSE;
*error_message = (char *) "Missing IHCONST";
return bfd_reloc_dangerous;
}
sym_value = get_symbol_value (symbol_in);
switch (r_type)
{
case R_IREL:
insn = bfd_get_32(abfd, hit_data);
/* Take the value in the field and sign extend it. */
signed_value = EXTRACT_JUMPTARG (insn);
signed_value = SIGN_EXTEND_JUMPTARG (signed_value);
signed_value <<= 2;
/* See the note on the R_IREL reloc in coff_or32_relocate_section. */
if (signed_value == - (long) reloc_entry->address)
signed_value = 0;
signed_value += sym_value + reloc_entry->addend;
/* Relative jmp/call, so subtract from the value the
address of the place we're coming from. */
signed_value -= (reloc_entry->address
+ input_section->output_section->vma
+ input_section->output_offset);
if (signed_value > 0x7ffffff || signed_value < -0x8000000)
return bfd_reloc_overflow;
signed_value >>= 2;
insn = INSERT_JUMPTARG (insn, signed_value);
bfd_put_32 (abfd, insn, hit_data);
break;
case R_ILOHALF:
insn = bfd_get_32 (abfd, hit_data);
unsigned_value = EXTRACT_HWORD (insn);
unsigned_value += sym_value + reloc_entry->addend;
insn = INSERT_HWORD (insn, unsigned_value);
bfd_put_32 (abfd, insn, hit_data);
break;
case R_IHIHALF:
insn = bfd_get_32 (abfd, hit_data);
/* consth, part 1
Just get the symbol value that is referenced. */
part1_consth_active = TRUE;
part1_consth_value = sym_value + reloc_entry->addend;
/* Don't modify insn until R_IHCONST. */
break;
case R_IHCONST:
insn = bfd_get_32 (abfd, hit_data);
/* consth, part 2
Now relocate the reference. */
if (! part1_consth_active)
{
*error_message = (char *) "Missing IHIHALF";
return bfd_reloc_dangerous;
}
/* sym_ptr_ptr = r_symndx, in coff_slurp_reloc_table() */
unsigned_value = 0; /*EXTRACT_HWORD(insn) << 16;*/
unsigned_value += reloc_entry->addend; /* r_symndx */
unsigned_value += part1_consth_value;
unsigned_value = unsigned_value >> 16;
insn = INSERT_HWORD (insn, unsigned_value);
part1_consth_active = FALSE;
bfd_put_32 (abfd, insn, hit_data);
break;
case R_BYTE:
insn = bfd_get_8 (abfd, hit_data);
unsigned_value = insn + sym_value + reloc_entry->addend;
if (unsigned_value & 0xffffff00)
return bfd_reloc_overflow;
bfd_put_8 (abfd, unsigned_value, hit_data);
break;
case R_HWORD:
insn = bfd_get_16 (abfd, hit_data);
unsigned_value = insn + sym_value + reloc_entry->addend;
if (unsigned_value & 0xffff0000)
return bfd_reloc_overflow;
bfd_put_16 (abfd, insn, hit_data);
break;
case R_WORD:
insn = bfd_get_32 (abfd, hit_data);
insn += sym_value + reloc_entry->addend;
bfd_put_32 (abfd, insn, hit_data);
break;
default:
*error_message = _("Unrecognized reloc");
return bfd_reloc_dangerous;
}
return bfd_reloc_ok;
}
/* type rightshift
size
bitsize
pc-relative
bitpos
absolute
complain_on_overflow
special_function
relocation name
partial_inplace
src_mask
*/
/* FIXME: I'm not real sure about this table. */
static reloc_howto_type howto_table[] =
{
{ R_ABS, 0, 3, 32, FALSE, 0, complain_overflow_bitfield, or32_reloc, "ABS", TRUE, 0xffffffff,0xffffffff, FALSE },
EMPTY_HOWTO (1),
EMPTY_HOWTO (2),
EMPTY_HOWTO (3),
EMPTY_HOWTO (4),
EMPTY_HOWTO (5),
EMPTY_HOWTO (6),
EMPTY_HOWTO (7),
EMPTY_HOWTO (8),
EMPTY_HOWTO (9),
EMPTY_HOWTO (10),
EMPTY_HOWTO (11),
EMPTY_HOWTO (12),
EMPTY_HOWTO (13),
EMPTY_HOWTO (14),
EMPTY_HOWTO (15),
EMPTY_HOWTO (16),
EMPTY_HOWTO (17),
EMPTY_HOWTO (18),
EMPTY_HOWTO (19),
EMPTY_HOWTO (20),
EMPTY_HOWTO (21),
EMPTY_HOWTO (22),
EMPTY_HOWTO (23),
{ R_IREL, 0, 3, 32, TRUE, 0, complain_overflow_signed, or32_reloc, "IREL", TRUE, 0xffffffff,0xffffffff, FALSE },
{ R_IABS, 0, 3, 32, FALSE, 0, complain_overflow_bitfield, or32_reloc, "IABS", TRUE, 0xffffffff,0xffffffff, FALSE },
{ R_ILOHALF, 0, 3, 16, TRUE, 0, complain_overflow_signed, or32_reloc, "ILOHALF", TRUE, 0x0000ffff,0x0000ffff, FALSE },
{ R_IHIHALF, 0, 3, 16, TRUE, 16,complain_overflow_signed, or32_reloc, "IHIHALF", TRUE, 0xffff0000,0xffff0000, FALSE },
{ R_IHCONST, 0, 3, 16, TRUE, 0, complain_overflow_signed, or32_reloc, "IHCONST", TRUE, 0xffff0000,0xffff0000, FALSE },
{ R_BYTE, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, or32_reloc, "BYTE", TRUE, 0x000000ff,0x000000ff, FALSE },
{ R_HWORD, 0, 1, 16, FALSE, 0, complain_overflow_bitfield, or32_reloc, "HWORD", TRUE, 0x0000ffff,0x0000ffff, FALSE },
{ R_WORD, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, or32_reloc, "WORD", TRUE, 0xffffffff,0xffffffff, FALSE },
};
#define BADMAG(x) OR32BADMAG (x)
#define RELOC_PROCESSING(relent, reloc, symbols, abfd, section) \
reloc_processing (relent, reloc, symbols, abfd, section)
static void
reloc_processing (arelent *relent,
struct internal_reloc *reloc,
asymbol **symbols,
bfd *abfd,
asection *section)
{
static bfd_vma ihihalf_vaddr = (bfd_vma) -1;
relent->address = reloc->r_vaddr;
relent->howto = howto_table + reloc->r_type;
if (reloc->r_type == R_IHCONST)
{
/* The address of an R_IHCONST should always be the address of
the immediately preceding R_IHIHALF. relocs generated by gas
are correct, but relocs generated by High C are different (I
can't figure out what the address means for High C). We can
handle both gas and High C by ignoring the address here, and
simply reusing the address saved for R_IHIHALF. */
if (ihihalf_vaddr == (bfd_vma) -1)
abort ();
relent->address = ihihalf_vaddr;
ihihalf_vaddr = (bfd_vma) -1;
relent->addend = reloc->r_symndx;
relent->sym_ptr_ptr= bfd_abs_section_ptr->symbol_ptr_ptr;
}
else
{
relent->sym_ptr_ptr = symbols + obj_convert (abfd)[reloc->r_symndx];
relent->addend = 0;
relent->address-= section->vma;
if (reloc->r_type == R_IHIHALF)
ihihalf_vaddr = relent->address;
else if (ihihalf_vaddr != (bfd_vma) -1)
abort ();
}
}
/* The reloc processing routine for the optimized COFF linker. */
static bfd_boolean
coff_or32_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
struct bfd_link_info *info,
bfd *input_bfd,
asection *input_section,
bfd_byte *contents,
struct internal_reloc *relocs,
struct internal_syment *syms,
asection **sections)
{
struct internal_reloc *rel;
struct internal_reloc *relend;
bfd_boolean hihalf;
bfd_vma hihalf_val;
/* If we are performing a relocatable link, we don't need to do a
thing. The caller will take care of adjusting the reloc
addresses and symbol indices. */
if (info->relocatable)
return TRUE;
hihalf = FALSE;
hihalf_val = 0;
rel = relocs;
relend = rel + input_section->reloc_count;
for (; rel < relend; rel++)
{
long symndx;
bfd_byte *loc;
struct coff_link_hash_entry *h;
struct internal_syment *sym;
asection *sec;
bfd_vma val;
bfd_boolean overflow;
unsigned long insn;
long signed_value;
unsigned long unsigned_value;
bfd_reloc_status_type rstat;
symndx = rel->r_symndx;
loc = contents + rel->r_vaddr - input_section->vma;
if (symndx == -1 || rel->r_type == R_IHCONST)
h = NULL;
else
h = obj_coff_sym_hashes (input_bfd)[symndx];
sym = NULL;
sec = NULL;
val = 0;
/* An R_IHCONST reloc does not have a symbol. Instead, the
symbol index is an addend. R_IHCONST is always used in
conjunction with R_IHHALF. */
if (rel->r_type != R_IHCONST)
{
if (h == NULL)
{
if (symndx == -1)
sec = bfd_abs_section_ptr;
else
{
sym = syms + symndx;
sec = sections[symndx];
val = (sec->output_section->vma
+ sec->output_offset
+ sym->n_value
- sec->vma);
}
}
else
{
if (h->root.type == bfd_link_hash_defined
|| h->root.type == bfd_link_hash_defweak)
{
sec = h->root.u.def.section;
val = (h->root.u.def.value
+ sec->output_section->vma
+ sec->output_offset);
}
else
{
if (! ((*info->callbacks->undefined_symbol)
(info, h->root.root.string, input_bfd, input_section,
rel->r_vaddr - input_section->vma, TRUE)))
return FALSE;
}
}
if (hihalf)
{
if (! ((*info->callbacks->reloc_dangerous)
(info, "missing IHCONST reloc", input_bfd,
input_section, rel->r_vaddr - input_section->vma)))
return FALSE;
hihalf = FALSE;
}
}
overflow = FALSE;
switch (rel->r_type)
{
default:
bfd_set_error (bfd_error_bad_value);
return FALSE;
case R_IREL:
insn = bfd_get_32 (input_bfd, loc);
/* Extract the addend. */
signed_value = EXTRACT_JUMPTARG (insn);
signed_value = SIGN_EXTEND_JUMPTARG (signed_value);
signed_value <<= 2;
/* Determine the destination of the jump. */
signed_value += val;
/* Make the destination PC relative. */
signed_value -= (input_section->output_section->vma
+ input_section->output_offset
+ (rel->r_vaddr - input_section->vma));
if (signed_value > 0x7ffffff || signed_value < - 0x8000000)
{
overflow = TRUE;
signed_value = 0;
}
/* Put the adjusted value back into the instruction. */
signed_value >>= 2;
insn = INSERT_JUMPTARG(insn, signed_value);
bfd_put_32 (input_bfd, (bfd_vma) insn, loc);
break;
case R_ILOHALF:
insn = bfd_get_32 (input_bfd, loc);
unsigned_value = EXTRACT_HWORD (insn);
unsigned_value += val;
insn = INSERT_HWORD (insn, unsigned_value);
bfd_put_32 (input_bfd, insn, loc);
break;
case R_IHIHALF:
/* Save the value for the R_IHCONST reloc. */
hihalf = TRUE;
hihalf_val = val;
break;
case R_IHCONST:
if (! hihalf)
{
if (! ((*info->callbacks->reloc_dangerous)
(info, "missing IHIHALF reloc", input_bfd,
input_section, rel->r_vaddr - input_section->vma)))
return FALSE;
hihalf_val = 0;
}
insn = bfd_get_32 (input_bfd, loc);
unsigned_value = rel->r_symndx + hihalf_val;
unsigned_value >>= 16;
insn = INSERT_HWORD (insn, unsigned_value);
bfd_put_32 (input_bfd, (bfd_vma) insn, loc);
hihalf = FALSE;
break;
case R_BYTE:
case R_HWORD:
case R_WORD:
rstat = _bfd_relocate_contents (howto_table + rel->r_type,
input_bfd, val, loc);
if (rstat == bfd_reloc_overflow)
overflow = TRUE;
else if (rstat != bfd_reloc_ok)
abort ();
break;
}
if (overflow)
{
const char *name;
char buf[SYMNMLEN + 1];
if (symndx == -1)
name = "*ABS*";
else if (h != NULL)
name = NULL;
else if (sym == NULL)
name = "*unknown*";
else if (sym->_n._n_n._n_zeroes == 0
&& sym->_n._n_n._n_offset != 0)
name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
else
{
strncpy (buf, sym->_n._n_name, SYMNMLEN);
buf[SYMNMLEN] = '\0';
name = buf;
}
if (! ((*info->callbacks->reloc_overflow)
(info, (h ? &h->root : NULL), name,
howto_table[rel->r_type].name, (bfd_vma) 0, input_bfd,
input_section, rel->r_vaddr - input_section->vma)))
return FALSE;
}
}
return TRUE;
}
#define coff_relocate_section coff_or32_relocate_section
/* We don't want to change the symndx of a R_IHCONST reloc, since it
is actually an addend, not a symbol index at all. */
static bfd_boolean
coff_or32_adjust_symndx (bfd *obfd ATTRIBUTE_UNUSED,
struct bfd_link_info *info ATTRIBUTE_UNUSED,
bfd *ibfd ATTRIBUTE_UNUSED,
asection *sec ATTRIBUTE_UNUSED,
struct internal_reloc *irel,
bfd_boolean *adjustedp)
{
if (irel->r_type == R_IHCONST)
*adjustedp = TRUE;
else
*adjustedp = FALSE;
return TRUE;
}
#define coff_adjust_symndx coff_or32_adjust_symndx
#ifndef bfd_pe_print_pdata
#define bfd_pe_print_pdata NULL
#endif
#include "coffcode.h"
const bfd_target or32coff_big_vec =
{
"coff-or32-big", /* Name. */
bfd_target_coff_flavour,
BFD_ENDIAN_BIG, /* Data byte order is big. */
BFD_ENDIAN_BIG, /* Header byte order is big. */
(HAS_RELOC | EXEC_P | /* Object flags. */
HAS_LINENO | HAS_DEBUG |
HAS_SYMS | HAS_LOCALS | WP_TEXT),
(SEC_HAS_CONTENTS | SEC_ALLOC | /* Section flags. */
SEC_LOAD | SEC_RELOC |
SEC_READONLY ),
'_', /* Leading underscore. */
'/', /* ar_pad_char. */
15, /* ar_max_namelen. */
0, /* match priority. */
/* Data. */
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
bfd_getb16, bfd_getb_signed_16, bfd_putb16,
/* Headers. */
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
bfd_getb16, bfd_getb_signed_16, bfd_putb16,
{
_bfd_dummy_target,
coff_object_p,
bfd_generic_archive_p,
_bfd_dummy_target
},
{
bfd_false,
coff_mkobject,
_bfd_generic_mkarchive,
bfd_false
},
{
bfd_false,
coff_write_object_contents,
_bfd_write_archive_contents,
bfd_false
},
BFD_JUMP_TABLE_GENERIC (coff),
BFD_JUMP_TABLE_COPY (coff),
BFD_JUMP_TABLE_CORE (_bfd_nocore),
BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
BFD_JUMP_TABLE_SYMBOLS (coff),
BFD_JUMP_TABLE_RELOCS (coff),
BFD_JUMP_TABLE_WRITE (coff),
BFD_JUMP_TABLE_LINK (coff),
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
/* Alternative_target. */
#ifdef TARGET_LITTLE_SYM
& TARGET_LITTLE_SYM,
#else
NULL,
#endif
COFF_SWAP_TABLE
};

20
bfd/coffcode.h
View File

@ -2096,12 +2096,6 @@ coff_set_arch_mach_hook (bfd *abfd, void * filehdr)
machine = 0;
switch (internal_f->f_magic)
{
#ifdef OR32_MAGIC_BIG
case OR32_MAGIC_BIG:
case OR32_MAGIC_LITTLE:
arch = bfd_arch_or32;
break;
#endif
#ifdef PPCMAGIC
case PPCMAGIC:
arch = bfd_arch_powerpc;
@ -3068,15 +3062,6 @@ coff_set_flags (bfd * abfd,
return TRUE;
#endif
#ifdef OR32_MAGIC_BIG
case bfd_arch_or32:
if (bfd_big_endian (abfd))
* magicp = OR32_MAGIC_BIG;
else
* magicp = OR32_MAGIC_LITTLE;
return TRUE;
#endif
default: /* Unknown architecture. */
/* Fall through to "return FALSE" below, to avoid
"statement never reached" errors on the one below. */
@ -4158,11 +4143,6 @@ coff_write_object_contents (bfd * abfd)
internal_a.magic = MIPS_PE_MAGIC;
#endif
#ifdef OR32
#define __A_MAGIC_SET__
internal_a.magic = NMAGIC; /* Assume separate i/d. */
#endif
#ifndef __A_MAGIC_SET__
#include "Your aouthdr magic number is not being set!"
#else

46
bfd/config.bfd
View File

@ -48,6 +48,11 @@ targ_underscore=no
# Catch obsolete configurations.
case $targ in
openrisc-*-* | or32-*-*)
echo "*** Configuration $targ is obsolete." >&2
echo "*** Use or1k-*-elf or or1k-*-linux as the target instead" >&2
exit 1
;;
null)
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration $targ is obsolete." >&2
@ -59,24 +64,24 @@ case $targ in
esac
case $targ in
m68*-apple-aux* | \
m68*-apollo-* | \
m68*-bull-sysv* | \
m68*-*-rtemscoff* | \
maxq-*-coff | \
i960-*-rtems* | \
or32-*-rtems* | \
m68*-*-lynxos* | \
sparc-*-lynxos* | \
vax-*-vms* | \
arm-*-oabi | \
a29k-* | \
hppa*-*-rtems* | \
*-go32-rtems* | \
a29k-* | \
arm-*-oabi | \
hppa*-*-rtems* | \
i960-*-rtems* | \
i[3-7]86*-*-rtemscoff* | \
m68*-*-lynxos* | \
m68*-*-rtemscoff* | \
m68*-apollo-* | \
m68*-apple-aux* | \
m68*-bull-sysv* | \
maxq-*-coff | \
mips*el-*-rtems* | \
or1k-*-rtems* | \
powerpcle-*-rtems* | \
sparc*-*-rtemsaout* | \
sparc-*-lynxos* | \
vax-*-vms* | \
null)
echo "*** Configuration $targ is obsolete." >&2
echo "*** Support has been REMOVED." >&2
@ -111,7 +116,7 @@ microblaze*) targ_archs=bfd_microblaze_arch ;;
mips*) targ_archs=bfd_mips_arch ;;
nds32*) targ_archs=bfd_nds32_arch ;;
nios2*) targ_archs=bfd_nios2_arch ;;
or32*) targ_archs=bfd_or32_arch ;;
or1k*|or1knd*) targ_archs=bfd_or1k_arch ;;
pdp11*) targ_archs=bfd_pdp11_arch ;;
pj*) targ_archs="bfd_pj_arch bfd_i386_arch";;
powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
@ -1165,17 +1170,12 @@ case "${targ}" in
targ_selvecs=bfd_elf32_bignios2_vec
;;
openrisc-*-elf)
targ_defvec=bfd_elf32_openrisc_vec
or1k-*-elf | or1k-*-linux*)
targ_defvec=bfd_elf32_or1k_vec
;;
or32-*-coff)
targ_defvec=or32coff_big_vec
targ_underscore=yes
;;
or32-*-elf)
targ_defvec=bfd_elf32_or32_big_vec
or1knd-*-elf | or1knd-*-linux*)
targ_defvec=bfd_elf32_or1k_vec
;;
pdp11-*-*)

4
bfd/configure vendored
View File

@ -15322,8 +15322,7 @@ do
bfd_elf32_nds32le_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
bfd_elf32_nds32belin_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
bfd_elf32_nds32lelin_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
bfd_elf32_openrisc_vec) tb="$tb elf32-openrisc.lo elf32.lo $elf" ;;
bfd_elf32_or32_big_vec) tb="$tb elf32-or32.lo elf32.lo $elf" ;;
bfd_elf32_or1k_vec) tb="$tb elf32-or1k.lo elf32.lo $elf" ;;
bfd_elf32_pj_vec) tb="$tb elf32-pj.lo elf32.lo $elf";;
bfd_elf32_pjl_vec) tb="$tb elf32-pj.lo elf32.lo $elf";;
bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
@ -15495,7 +15494,6 @@ do
nlm32_i386_vec) tb="$tb nlm32-i386.lo nlm32.lo nlm.lo" ;;
nlm32_powerpc_vec) tb="$tb nlm32-ppc.lo nlm32.lo nlm.lo" ;;
nlm32_sparc_vec) tb="$tb nlm32-sparc.lo nlm32.lo nlm.lo" ;;
or32coff_big_vec) tb="$tb coff-or32.lo cofflink.lo" ;;
pc532machaout_vec) tb="$tb pc532-mach.lo aout-ns32k.lo" ;;
pc532netbsd_vec) tb="$tb ns32knetbsd.lo aout-ns32k.lo" ;;
pef_vec) tb="$tb pef.lo" ;;

9
bfd/configure.in
View File

@ -578,6 +578,11 @@ changequote([,])dnl
SHARED_LDFLAGS="-no-undefined"
SHARED_LIBADD="-L`pwd`/../libiberty -liberty -L`pwd`/../intl -lintl -lcygwin -lkernel32"
;;
# Hack to build or1k-src on OSX
or1k*-*-darwin*)
SHARED_LIBADD="-L`pwd`/../libiberty/pic -L`pwd`/../intl -liberty -lintl"
;;
esac
if test -n "$SHARED_LIBADD"; then
@ -801,8 +806,7 @@ do
bfd_elf32_nds32le_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
bfd_elf32_nds32belin_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
bfd_elf32_nds32lelin_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
bfd_elf32_openrisc_vec) tb="$tb elf32-openrisc.lo elf32.lo $elf" ;;
bfd_elf32_or32_big_vec) tb="$tb elf32-or32.lo elf32.lo $elf" ;;
bfd_elf32_or1k_vec) tb="$tb elf32-or1k.lo elf32.lo $elf" ;;
bfd_elf32_pj_vec) tb="$tb elf32-pj.lo elf32.lo $elf";;
bfd_elf32_pjl_vec) tb="$tb elf32-pj.lo elf32.lo $elf";;
bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
@ -974,7 +978,6 @@ do
nlm32_i386_vec) tb="$tb nlm32-i386.lo nlm32.lo nlm.lo" ;;
nlm32_powerpc_vec) tb="$tb nlm32-ppc.lo nlm32.lo nlm.lo" ;;
nlm32_sparc_vec) tb="$tb nlm32-sparc.lo nlm32.lo nlm.lo" ;;
or32coff_big_vec) tb="$tb coff-or32.lo cofflink.lo" ;;
pc532machaout_vec) tb="$tb pc532-mach.lo aout-ns32k.lo" ;;
pc532netbsd_vec) tb="$tb ns32knetbsd.lo aout-ns32k.lo" ;;
pef_vec) tb="$tb pef.lo" ;;

44
bfd/cpu-openrisc.c
View File

@ -1,44 +0,0 @@
/* BFD support for the OpenRISC architecture.
Copyright (C) 2001-2014 Free Software Foundation, Inc.
Contributed by Johan Rydberg, jrydberg@opencores.org
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
{ \
BITS_WORD, /* bits in a word */ \
BITS_ADDR, /* bits in an address */ \
8, /* 8 bits in a byte */ \
bfd_arch_openrisc, \
NUMBER, \
"openrisc", \
PRINT, \
2, \
DEFAULT, \
bfd_default_compatible, \
bfd_default_scan, \
bfd_arch_default_fill, \
NEXT, \
}
const bfd_arch_info_type bfd_openrisc_arch =
N (32, 32, 0, "openrisc", TRUE, 0);

41
bfd/cpu-or32.c → bfd/cpu-or1k.c
View File

@ -1,6 +1,6 @@
/* BFD support for the OpenRISC 1000 architecture.
Copyright (C) 2002-2014 Free Software Foundation, Inc.
Contributed by Ivan Guzvinec <ivang@opencores.org>
Copyright 2002-2014 Free Software Foundation, Inc.
Contributed for OR32 by Ivan Guzvinec <ivang@opencores.org>
This file is part of BFD, the Binary File Descriptor library.
@ -15,28 +15,45 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
along with this program; if not, see <http://www.gnu.org/licenses/>. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
const bfd_arch_info_type bfd_or32_arch =
const bfd_arch_info_type bfd_or1k_arch;
const bfd_arch_info_type bfd_or1knd_arch;
const bfd_arch_info_type bfd_or1k_arch =
{
32, /* 32 bits in a word. */
32, /* 32 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_or32,
0, /* Only 1 machine. */
"or32",
"or32",
bfd_arch_or1k,
bfd_mach_or1k,
"or1k",
"or1k",
4,
TRUE, /* The one and only. */
TRUE,
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
0,
&bfd_or1knd_arch,
};
const bfd_arch_info_type bfd_or1knd_arch =
{
32, /* 32 bits in a word. */
32, /* 32 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_or1k,
bfd_mach_or1knd,
"or1knd",
"or1knd",
4,
FALSE,
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
NULL,
};

1
bfd/elf-bfd.h
View File

@ -421,6 +421,7 @@ enum elf_target_id
MN10300_ELF_DATA,
NDS32_ELF_DATA,
NIOS2_ELF_DATA,
OR1K_ELF_DATA,
PPC32_ELF_DATA,
PPC64_ELF_DATA,
S390_ELF_DATA,

569
bfd/elf32-openrisc.c
View File

@ -1,569 +0,0 @@
/* OpenRISC-specific support for 32-bit ELF.
Copyright (C) 2001-2014 Free Software Foundation, Inc.
Contributed by Johan Rydberg, jrydberg@opencores.org
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "elf-bfd.h"
#include "elf/openrisc.h"
#include "libiberty.h"
static reloc_howto_type openrisc_elf_howto_table[] =
{
/* This reloc does nothing. */
HOWTO (R_OPENRISC_NONE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_OPENRISC_NONE", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* A PC relative 26 bit relocation, right shifted by 2. */
HOWTO (R_OPENRISC_INSN_REL_26, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
26, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_OPENRISC_INSN_REL_26", /* name */
FALSE, /* partial_inplace */
0x00000000, /* src_mask */
0x03ffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A absolute 26 bit relocation, right shifted by 2. */
HOWTO (R_OPENRISC_INSN_ABS_26, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
26, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_OPENRISC_INSN_ABS_26", /* name */
FALSE, /* partial_inplace */
0x00000000, /* src_mask */
0x03ffffff, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (R_OPENRISC_LO_16_IN_INSN, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_OPENRISC_LO_16_IN_INSN", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (R_OPENRISC_HI_16_IN_INSN, /* type */
16, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_OPENRISC_HI_16_IN_INSN", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* An 8 bit absolute relocation. */
HOWTO (R_OPENRISC_8, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_OPENRISC_8", /* name */
TRUE, /* partial_inplace */
0x0000, /* src_mask */
0x00ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 16 bit absolute relocation. */
HOWTO (R_OPENRISC_16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_OPENRISC_16", /* name */
TRUE, /* partial_inplace */
0x00000000, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 32 bit absolute relocation. */
HOWTO (R_OPENRISC_32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_OPENRISC_32", /* name */
TRUE, /* partial_inplace */
0x00000000, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable hierarchy. */
HOWTO (R_OPENRISC_GNU_VTINHERIT, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
NULL, /* special_function */
"R_OPENRISC_GNU_VTINHERIT", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable member usage. */
HOWTO (R_OPENRISC_GNU_VTENTRY, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
_bfd_elf_rel_vtable_reloc_fn, /* special_function */
"R_OPENRISC_GNU_VTENTRY", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
};
/* Map BFD reloc types to OpenRISC ELF reloc types. */
struct openrisc_reloc_map
{
bfd_reloc_code_real_type bfd_reloc_val;
unsigned int openrisc_reloc_val;
};
static const struct openrisc_reloc_map openrisc_reloc_map[] =
{
{ BFD_RELOC_NONE, R_OPENRISC_NONE },
{ BFD_RELOC_32, R_OPENRISC_32 },
{ BFD_RELOC_16, R_OPENRISC_16 },
{ BFD_RELOC_8, R_OPENRISC_8 },
{ BFD_RELOC_OPENRISC_REL_26, R_OPENRISC_INSN_REL_26 },
{ BFD_RELOC_OPENRISC_ABS_26, R_OPENRISC_INSN_ABS_26 },
{ BFD_RELOC_HI16, R_OPENRISC_HI_16_IN_INSN },
{ BFD_RELOC_LO16, R_OPENRISC_LO_16_IN_INSN },
{ BFD_RELOC_VTABLE_INHERIT, R_OPENRISC_GNU_VTINHERIT },
{ BFD_RELOC_VTABLE_ENTRY, R_OPENRISC_GNU_VTENTRY }
};
static reloc_howto_type *
openrisc_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
for (i = ARRAY_SIZE (openrisc_reloc_map); --i;)
if (openrisc_reloc_map[i].bfd_reloc_val == code)
return & openrisc_elf_howto_table[openrisc_reloc_map[i].
openrisc_reloc_val];
return NULL;
}
static reloc_howto_type *
openrisc_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
const char *r_name)
{
unsigned int i;
for (i = 0;
i < (sizeof (openrisc_elf_howto_table)
/ sizeof (openrisc_elf_howto_table[0]));
i++)
if (openrisc_elf_howto_table[i].name != NULL
&& strcasecmp (openrisc_elf_howto_table[i].name, r_name) == 0)
return &openrisc_elf_howto_table[i];
return NULL;
}
/* Set the howto pointer for an OpenRISC ELF reloc. */
static void
openrisc_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
arelent * cache_ptr,
Elf_Internal_Rela * dst)
{
unsigned int r_type;
r_type = ELF32_R_TYPE (dst->r_info);
BFD_ASSERT (r_type < (unsigned int) R_OPENRISC_max);
cache_ptr->howto = & openrisc_elf_howto_table[r_type];
}
/* Perform a single relocation. By default we use the standard BFD
routines, but a few relocs, we have to do them ourselves. */
static bfd_reloc_status_type
openrisc_final_link_relocate (reloc_howto_type *howto,
bfd *input_bfd,
asection *input_section,
bfd_byte *contents,
Elf_Internal_Rela *rel,
bfd_vma relocation)
{
bfd_reloc_status_type r = bfd_reloc_ok;
switch (howto->type)
{
case R_OPENRISC_LO_16_IN_INSN:
relocation &= 0xffff;
r = _bfd_final_link_relocate (howto, input_bfd, input_section,
contents, rel->r_offset,
relocation, rel->r_addend);
break;
default:
r = _bfd_final_link_relocate (howto, input_bfd, input_section,
contents, rel->r_offset,
relocation, rel->r_addend);
}
return r;
}
/* Relocate an OpenRISC ELF section.
The RELOCATE_SECTION function is called by the new ELF backend linker
to handle the relocations for a section.
The relocs are always passed as Rela structures; if the section
actually uses Rel structures, the r_addend field will always be
zero.
This function is responsible for adjusting the section contents as
necessary, and (if using Rela relocs and generating a relocatable
output file) adjusting the reloc addend as necessary.
This function does not have to worry about setting the reloc
address or the reloc symbol index.
LOCAL_SYMS is a pointer to the swapped in local symbols.
LOCAL_SECTIONS is an array giving the section in the input file
corresponding to the st_shndx field of each local symbol.
The global hash table entry for the global symbols can be found
via elf_sym_hashes (input_bfd).
When generating relocatable output, this function must handle
STB_LOCAL/STT_SECTION symbols specially. The output symbol is
going to be the section symbol corresponding to the output
section, which means that the addend must be adjusted
accordingly. */
static bfd_boolean
openrisc_elf_relocate_section (bfd *output_bfd,
struct bfd_link_info *info,
bfd *input_bfd,
asection *input_section,
bfd_byte *contents,
Elf_Internal_Rela *relocs,
Elf_Internal_Sym *local_syms,
asection **local_sections)
{
Elf_Internal_Shdr *symtab_hdr;
struct elf_link_hash_entry **sym_hashes;
Elf_Internal_Rela *rel;
Elf_Internal_Rela *relend;
symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
sym_hashes = elf_sym_hashes (input_bfd);
relend = relocs + input_section->reloc_count;
for (rel = relocs; rel < relend; rel++)
{
reloc_howto_type *howto;
unsigned long r_symndx;
Elf_Internal_Sym *sym;
asection *sec;
struct elf_link_hash_entry *h;
bfd_vma relocation;
bfd_reloc_status_type r;
const char *name = NULL;
int r_type;
r_type = ELF32_R_TYPE (rel->r_info);
r_symndx = ELF32_R_SYM (rel->r_info);
if (r_type == R_OPENRISC_GNU_VTINHERIT
|| r_type == R_OPENRISC_GNU_VTENTRY)
continue;
if ((unsigned int) r_type >
(sizeof openrisc_elf_howto_table / sizeof (reloc_howto_type)))
abort ();
howto = openrisc_elf_howto_table + ELF32_R_TYPE (rel->r_info);
h = NULL;
sym = NULL;
sec = NULL;
if (r_symndx < symtab_hdr->sh_info)
{
sym = local_syms + r_symndx;
sec = local_sections[r_symndx];
relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
name = bfd_elf_string_from_elf_section
(input_bfd, symtab_hdr->sh_link, sym->st_name);
name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name;
}
else
{
bfd_boolean unresolved_reloc, warned, ignored;
RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
r_symndx, symtab_hdr, sym_hashes,
h, sec, relocation,
unresolved_reloc, warned, ignored);
}
if (sec != NULL && discarded_section (sec))
RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
rel, 1, relend, howto, 0, contents);
if (info->relocatable)
continue;
r = openrisc_final_link_relocate (howto, input_bfd, input_section,
contents, rel, relocation);
if (r != bfd_reloc_ok)
{
const char *msg = NULL;
switch (r)
{
case bfd_reloc_overflow:
r = info->callbacks->reloc_overflow
(info, (h ? &h->root : NULL), name, howto->name,
(bfd_vma) 0, input_bfd, input_section, rel->r_offset);
break;
case bfd_reloc_undefined:
r = info->callbacks->undefined_symbol
(info, name, input_bfd, input_section, rel->r_offset, TRUE);
break;
case bfd_reloc_outofrange:
msg = _("internal error: out of range error");
break;
case bfd_reloc_notsupported:
msg = _("internal error: unsupported relocation error");
break;
case bfd_reloc_dangerous:
msg = _("internal error: dangerous relocation");
break;
default:
msg = _("internal error: unknown error");
break;
}
if (msg)
r = info->callbacks->warning
(info, msg, name, input_bfd, input_section, rel->r_offset);
if (!r)
return FALSE;
}
}
return TRUE;
}
/* Return the section that should be marked against GC for a given
relocation. */
static asection *
openrisc_elf_gc_mark_hook (asection *sec,
struct bfd_link_info *info,
Elf_Internal_Rela *rel,
struct elf_link_hash_entry *h,
Elf_Internal_Sym *sym)
{
if (h != NULL)
switch (ELF32_R_TYPE (rel->r_info))
{
case R_OPENRISC_GNU_VTINHERIT:
case R_OPENRISC_GNU_VTENTRY:
return NULL;
}
return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
}
/* Look through the relocs for a section during the first phase.
Since we don't do .gots or .plts, we just need to consider the
virtual table relocs for gc. */
static bfd_boolean
openrisc_elf_check_relocs (bfd *abfd,
struct bfd_link_info *info,
asection *sec,
const Elf_Internal_Rela *relocs)
{
Elf_Internal_Shdr *symtab_hdr;
struct elf_link_hash_entry **sym_hashes;
const Elf_Internal_Rela *rel;
const Elf_Internal_Rela *rel_end;
if (info->relocatable)
return TRUE;
symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
sym_hashes = elf_sym_hashes (abfd);
rel_end = relocs + sec->reloc_count;
for (rel = relocs; rel < rel_end; rel++)
{
struct elf_link_hash_entry *h;
unsigned long r_symndx;
r_symndx = ELF32_R_SYM (rel->r_info);
if (r_symndx < symtab_hdr->sh_info)
h = NULL;
else
{
h = sym_hashes[r_symndx - symtab_hdr->sh_info];
while (h->root.type == bfd_link_hash_indirect
|| h->root.type == bfd_link_hash_warning)
h = (struct elf_link_hash_entry *) h->root.u.i.link;
/* PR15323, ref flags aren't set for references in the same
object. */
h->root.non_ir_ref = 1;
}
switch (ELF32_R_TYPE (rel->r_info))
{
/* This relocation describes the C++ object vtable hierarchy.
Reconstruct it for later use during GC. */
case R_OPENRISC_GNU_VTINHERIT:
if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
return FALSE;
break;
/* This relocation describes which C++ vtable entries are actually
used. Record for later use during GC. */
case R_OPENRISC_GNU_VTENTRY:
BFD_ASSERT (h != NULL);
if (h != NULL
&& !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))
return FALSE;
break;
}
}
return TRUE;
}
/* Set the right machine number. */
static bfd_boolean
openrisc_elf_object_p (bfd *abfd)
{
bfd_default_set_arch_mach (abfd, bfd_arch_openrisc, 0);
return TRUE;
}
/* Store the machine number in the flags field. */
static void
openrisc_elf_final_write_processing (bfd *abfd,
bfd_boolean linker ATTRIBUTE_UNUSED)
{
unsigned long val;
switch (bfd_get_mach (abfd))
{
default:
val = 0;
break;
}
elf_elfheader (abfd)->e_flags &= ~0xf;
elf_elfheader (abfd)->e_flags |= val;
}
#define ELF_ARCH bfd_arch_openrisc
#define ELF_MACHINE_CODE EM_OPENRISC
#define ELF_MACHINE_ALT1 EM_OPENRISC_OLD
#define ELF_MAXPAGESIZE 0x1000
#define TARGET_BIG_SYM bfd_elf32_openrisc_vec
#define TARGET_BIG_NAME "elf32-openrisc"
#define elf_info_to_howto_rel NULL
#define elf_info_to_howto openrisc_info_to_howto_rela
#define elf_backend_relocate_section openrisc_elf_relocate_section
#define elf_backend_gc_mark_hook openrisc_elf_gc_mark_hook
#define elf_backend_check_relocs openrisc_elf_check_relocs
#define elf_backend_can_gc_sections 1
#define elf_backend_rela_normal 1
#define bfd_elf32_bfd_reloc_type_lookup openrisc_reloc_type_lookup
#define bfd_elf32_bfd_reloc_name_lookup openrisc_reloc_name_lookup
#define elf_backend_object_p openrisc_elf_object_p
#define elf_backend_final_write_processing openrisc_elf_final_write_processing
#include "elf32-target.h"

2872
bfd/elf32-or1k.c Normal file
View File

File diff suppressed because it is too large Load Diff

514
bfd/elf32-or32.c
View File

@ -1,514 +0,0 @@
/* OR32-specific support for 32-bit ELF
Copyright (C) 2002-2014 Free Software Foundation, Inc.
Contributed by Ivan Guzvinec <ivang@opencores.org>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "elf-bfd.h"
#include "elf/or32.h"
#include "libiberty.h"
/* Try to minimize the amount of space occupied by relocation tables
on the ROM (not that the ROM won't be swamped by other ELF overhead). */
#define USE_REL 1
/* Set the right machine number for an OR32 ELF file. */
static bfd_boolean
or32_elf_object_p (bfd *abfd)
{
(void) bfd_default_set_arch_mach (abfd, bfd_arch_or32, 0);
return TRUE;
}
/* The final processing done just before writing out an OR32 ELF object file.
This gets the OR32 architecture right based on the machine number. */
static void
or32_elf_final_write_processing (bfd *abfd,
bfd_boolean linker ATTRIBUTE_UNUSED)
{
elf_elfheader (abfd)->e_flags &=~ EF_OR32_MACH;
}
static bfd_reloc_status_type
or32_elf_32_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
if (output_bfd != NULL)
{
unsigned long insn;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_32 (abfd, (bfd_byte *) data + addr);
insn += symbol->section->output_section->vma;
insn += symbol->section->output_offset;
insn += symbol->value;
bfd_put_32 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
static bfd_reloc_status_type
or32_elf_16_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
if (output_bfd != NULL)
{
unsigned short insn;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_16 (abfd, (bfd_byte *) data + addr);
insn += symbol->section->output_section->vma;
insn += symbol->section->output_offset;
insn += symbol->value;
bfd_put_16 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
static bfd_reloc_status_type
or32_elf_8_reloc (bfd *abfd ATTRIBUTE_UNUSED,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
if (output_bfd != NULL)
{
unsigned char insn;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_8 (abfd, (bfd_byte *) data + addr);
insn += symbol->section->output_section->vma;
insn += symbol->section->output_offset;
insn += symbol->value;
bfd_put_8 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
/* Do a R_OR32_CONSTH relocation. This has to be done in combination
with a R_OR32_CONST reloc, because there is a carry from the LO16 to
the HI16. Here we just save the information we need; we do the
actual relocation when we see the LO16. OR32 ELF requires that the
LO16 immediately follow the HI16. As a GNU extension, we permit an
arbitrary number of HI16 relocs to be associated with a single LO16
reloc. This extension permits gcc to output the HI and LO relocs
itself. This code is copied from the elf32-mips.c. */
struct or32_consth
{
struct or32_consth *next;
bfd_byte *addr;
bfd_vma addend;
};
/* FIXME: This should not be a static variable. */
static struct or32_consth *or32_consth_list;
static bfd_reloc_status_type
or32_elf_consth_reloc (bfd *abfd ATTRIBUTE_UNUSED,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
bfd_reloc_status_type ret;
bfd_vma relocation;
struct or32_consth *n;
ret = bfd_reloc_ok;
if (bfd_is_und_section (symbol->section)
&& output_bfd == NULL)
ret = bfd_reloc_undefined;
if (bfd_is_com_section (symbol->section))
relocation = 0;
else
relocation = symbol->value;
relocation += symbol->section->output_section->vma;
relocation += symbol->section->output_offset;
relocation += reloc_entry->addend;
if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
return bfd_reloc_outofrange;
/* Save the information, and let LO16 do the actual relocation. */
n = bfd_malloc (sizeof *n);
if (n == NULL)
return bfd_reloc_outofrange;
n->addr = (bfd_byte *) data + reloc_entry->address;
n->addend = relocation;
n->next = or32_consth_list;
or32_consth_list = n;
if (output_bfd != NULL)
reloc_entry->address += input_section->output_offset;
return ret;
}
/* Do a R_OR32_CONST relocation. This is a straightforward 16 bit
inplace relocation; this function exists in order to do the
R_OR32_CONSTH relocation described above. */
static bfd_reloc_status_type
or32_elf_const_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message)
{
if (or32_consth_list != NULL)
{
struct or32_consth *l;
l = or32_consth_list;
while (l != NULL)
{
unsigned long insn;
unsigned long val;
unsigned long vallo;
struct or32_consth *next;
/* Do the HI16 relocation. Note that we actually don't need
to know anything about the LO16 itself, except where to
find the low 16 bits of the addend needed by the LO16. */
insn = bfd_get_32 (abfd, l->addr);
vallo = (bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address)
& 0xffff);
val = ((insn & 0xffff) << 16) + vallo;
val += l->addend;
insn = (insn &~ 0xffff) | ((val >> 16) & 0xffff);
bfd_put_32 (abfd, insn, l->addr);
next = l->next;
free (l);
l = next;
}
or32_consth_list = NULL;
}
if (output_bfd != NULL)
{
unsigned long insn, tmp;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_32 (abfd, (bfd_byte *) data + addr);
tmp = insn & 0x0000ffff;
tmp += symbol->section->output_section->vma;
tmp += symbol->section->output_offset;
tmp += symbol->value;
insn = (insn & 0xffff0000) | (tmp & 0x0000ffff);
bfd_put_32 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
/* Now do the LO16 reloc in the usual way. */
return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
input_section, output_bfd, error_message);
}
static bfd_reloc_status_type
or32_elf_jumptarg_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol ATTRIBUTE_UNUSED,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
if (output_bfd != NULL)
{
unsigned long insn, tmp;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_32 (abfd, (bfd_byte *) data + addr);
tmp = insn | 0xfc000000;
tmp -= (input_section->output_offset >> 2);
insn = (insn & 0xfc000000) | (tmp & 0x03ffffff);
bfd_put_32 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
static reloc_howto_type elf_or32_howto_table[] =
{
/* This reloc does nothing. */
HOWTO (R_OR32_NONE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_OR32_NONE", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* A standard 32 bit relocation. */
HOWTO (R_OR32_32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
or32_elf_32_reloc, /* special_function */
"R_OR32_32", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A standard 16 bit relocation. */
HOWTO (R_OR32_16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
or32_elf_16_reloc, /* special_function */
"R_OR32_16", /* name */
FALSE, /* partial_inplace */
0x0000ffff, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A standard 8 bit relocation. */
HOWTO (R_OR32_8, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
or32_elf_8_reloc, /* special_function */
"R_OR32_8", /* name */
FALSE, /* partial_inplace */
0x000000ff, /* src_mask */
0x000000ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A standard low 16 bit relocation. */
HOWTO (R_OR32_CONST, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
or32_elf_const_reloc, /* special_function */
"R_OR32_CONST", /* name */
FALSE, /* partial_inplace */
0x0000ffff, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A standard high 16 bit relocation. */
HOWTO (R_OR32_CONSTH, /* type */
16, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
or32_elf_consth_reloc, /* special_function */
"R_OR32_CONSTH", /* name */
FALSE, /* partial_inplace */
0xffff0000, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A standard branch relocation. */
HOWTO (R_OR32_JUMPTARG, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
28, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
or32_elf_jumptarg_reloc,/* special_function */
"R_OR32_JUMPTARG", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x03ffffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* GNU extension to record C++ vtable hierarchy. */
HOWTO (R_OR32_GNU_VTINHERIT, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
NULL, /* special_function */
"R_OR32_GNU_VTINHERIT", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable member usage. */
HOWTO (R_OR32_GNU_VTENTRY, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
_bfd_elf_rel_vtable_reloc_fn, /* special_function */
"R_OR32_GNU_VTENTRY", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
};
/* Map BFD reloc types to OR32 ELF reloc types. */
struct or32_reloc_map
{
bfd_reloc_code_real_type bfd_reloc_val;
unsigned char elf_reloc_val;
};
static const struct or32_reloc_map or32_reloc_map[] =
{
{ BFD_RELOC_NONE, R_OR32_NONE },
{ BFD_RELOC_32, R_OR32_32 },
{ BFD_RELOC_16, R_OR32_16 },
{ BFD_RELOC_8, R_OR32_8 },
{ BFD_RELOC_LO16, R_OR32_CONST },
{ BFD_RELOC_HI16, R_OR32_CONSTH },
{ BFD_RELOC_32_GOT_PCREL, R_OR32_JUMPTARG },
{ BFD_RELOC_VTABLE_INHERIT, R_OR32_GNU_VTINHERIT },
{ BFD_RELOC_VTABLE_ENTRY, R_OR32_GNU_VTENTRY },
};
static reloc_howto_type *
bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
for (i = ARRAY_SIZE (or32_reloc_map); i--;)
if (or32_reloc_map[i].bfd_reloc_val == code)
return &elf_or32_howto_table[or32_reloc_map[i].elf_reloc_val];
return NULL;
}
static reloc_howto_type *
bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
const char *r_name)
{
unsigned int i;
for (i = 0;
i < sizeof (elf_or32_howto_table) / sizeof (elf_or32_howto_table[0]);
i++)
if (elf_or32_howto_table[i].name != NULL
&& strcasecmp (elf_or32_howto_table[i].name, r_name) == 0)
return &elf_or32_howto_table[i];
return NULL;
}
/* Set the howto pointer for an OR32 ELF reloc. */
static void
or32_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
unsigned int r_type;
r_type = ELF32_R_TYPE (dst->r_info);
BFD_ASSERT (r_type < (unsigned int) R_OR32_max);
cache_ptr->howto = &elf_or32_howto_table[r_type];
}
#define TARGET_LITTLE_SYM bfd_elf32_or32_little_vec
#define TARGET_LITTLE_NAME "elf32-littleor32"
#define TARGET_BIG_SYM bfd_elf32_or32_big_vec
#define TARGET_BIG_NAME "elf32-or32"
#define ELF_ARCH bfd_arch_or32
#define ELF_MACHINE_CODE EM_OR32
#define ELF_MAXPAGESIZE 0x1000
#define elf_info_to_howto 0
#define elf_info_to_howto_rel or32_info_to_howto_rel
#define elf_backend_object_p or32_elf_object_p
#define elf_backend_final_write_processing \
or32_elf_final_write_processing
#include "elf32-target.h"

26
bfd/libbfd.h
View File

@ -2450,8 +2450,30 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_860_HIGH",
"BFD_RELOC_860_HIGOT",
"BFD_RELOC_860_HIGOTOFF",
"BFD_RELOC_OPENRISC_ABS_26",
"BFD_RELOC_OPENRISC_REL_26",
"BFD_RELOC_OR1K_REL_26",
"BFD_RELOC_OR1K_GOTPC_HI16",
"BFD_RELOC_OR1K_GOTPC_LO16",
"BFD_RELOC_OR1K_GOT16",
"BFD_RELOC_OR1K_PLT26",
"BFD_RELOC_OR1K_GOTOFF_HI16",
"BFD_RELOC_OR1K_GOTOFF_LO16",
"BFD_RELOC_OR1K_COPY",
"BFD_RELOC_OR1K_GLOB_DAT",
"BFD_RELOC_OR1K_JMP_SLOT",
"BFD_RELOC_OR1K_RELATIVE",
"BFD_RELOC_OR1K_TLS_GD_HI16",
"BFD_RELOC_OR1K_TLS_GD_LO16",
"BFD_RELOC_OR1K_TLS_LDM_HI16",
"BFD_RELOC_OR1K_TLS_LDM_LO16",
"BFD_RELOC_OR1K_TLS_LDO_HI16",
"BFD_RELOC_OR1K_TLS_LDO_LO16",
"BFD_RELOC_OR1K_TLS_IE_HI16",
"BFD_RELOC_OR1K_TLS_IE_LO16",
"BFD_RELOC_OR1K_TLS_LE_HI16",
"BFD_RELOC_OR1K_TLS_LE_LO16",
"BFD_RELOC_OR1K_TLS_TPOFF",
"BFD_RELOC_OR1K_TLS_DTPOFF",
"BFD_RELOC_OR1K_TLS_DTPMOD",
"BFD_RELOC_H8_DIR16A8",
"BFD_RELOC_H8_DIR16R8",
"BFD_RELOC_H8_DIR24A8",

50
bfd/reloc.c
View File

@ -5881,11 +5881,55 @@ ENUMDOC
Intel i860 Relocations.
ENUM
BFD_RELOC_OPENRISC_ABS_26
BFD_RELOC_OR1K_REL_26
ENUMX
BFD_RELOC_OPENRISC_REL_26
BFD_RELOC_OR1K_GOTPC_HI16
ENUMX
BFD_RELOC_OR1K_GOTPC_LO16
ENUMX
BFD_RELOC_OR1K_GOT16
ENUMX
BFD_RELOC_OR1K_PLT26
ENUMX
BFD_RELOC_OR1K_GOTOFF_HI16
ENUMX
BFD_RELOC_OR1K_GOTOFF_LO16
ENUMX
BFD_RELOC_OR1K_COPY
ENUMX
BFD_RELOC_OR1K_GLOB_DAT
ENUMX
BFD_RELOC_OR1K_JMP_SLOT
ENUMX
BFD_RELOC_OR1K_RELATIVE
ENUMX
BFD_RELOC_OR1K_TLS_GD_HI16
ENUMX
BFD_RELOC_OR1K_TLS_GD_LO16
ENUMX
BFD_RELOC_OR1K_TLS_LDM_HI16
ENUMX
BFD_RELOC_OR1K_TLS_LDM_LO16
ENUMX
BFD_RELOC_OR1K_TLS_LDO_HI16
ENUMX
BFD_RELOC_OR1K_TLS_LDO_LO16
ENUMX
BFD_RELOC_OR1K_TLS_IE_HI16
ENUMX
BFD_RELOC_OR1K_TLS_IE_LO16
ENUMX
BFD_RELOC_OR1K_TLS_LE_HI16
ENUMX
BFD_RELOC_OR1K_TLS_LE_LO16
ENUMX
BFD_RELOC_OR1K_TLS_TPOFF
ENUMX
BFD_RELOC_OR1K_TLS_DTPOFF
ENUMX
BFD_RELOC_OR1K_TLS_DTPMOD
ENUMDOC
OpenRISC Relocations.
OpenRISC 1000 Relocations.
ENUM
BFD_RELOC_H8_DIR16A8

9
bfd/targets.c
View File

@ -677,8 +677,7 @@ extern const bfd_target bfd_elf32_nds32be_vec;
extern const bfd_target bfd_elf32_nds32le_vec;
extern const bfd_target bfd_elf32_nds32belin_vec;
extern const bfd_target bfd_elf32_nds32lelin_vec;
extern const bfd_target bfd_elf32_openrisc_vec;
extern const bfd_target bfd_elf32_or32_big_vec;
extern const bfd_target bfd_elf32_or1k_vec;
extern const bfd_target bfd_elf32_pj_vec;
extern const bfd_target bfd_elf32_pjl_vec;
extern const bfd_target bfd_elf32_powerpc_vec;
@ -844,7 +843,6 @@ extern const bfd_target nlm32_i386_vec;
extern const bfd_target nlm32_powerpc_vec;
extern const bfd_target nlm32_sparc_vec;
extern const bfd_target oasys_vec;
extern const bfd_target or32coff_big_vec;
extern const bfd_target pc532machaout_vec;
extern const bfd_target pc532netbsd_vec;
extern const bfd_target pdp11_aout_vec;
@ -1070,8 +1068,7 @@ static const bfd_target * const _bfd_target_vector[] =
&bfd_elf32_nds32le_vec,
&bfd_elf32_nds32belin_vec,
&bfd_elf32_nds32lelin_vec,
&bfd_elf32_openrisc_vec,
&bfd_elf32_or32_big_vec,
&bfd_elf32_or1k_vec,
&bfd_elf32_pj_vec,
&bfd_elf32_pjl_vec,
&bfd_elf32_powerpc_vec,
@ -1282,8 +1279,6 @@ static const bfd_target * const _bfd_target_vector[] =
can be annoying target mis-matches. */
&oasys_vec,
#endif
/* Entry for the OpenRISC family. */
&or32coff_big_vec,
&pc532machaout_vec,
&pc532netbsd_vec,

4
binutils/ChangeLog
View File

@ -1,3 +1,7 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* readelf.c: Remove openrisc and or32 support. Add support for or1k.
2014-04-18 Tristan Gingold <gingold@adacore.com>
* od-macho.c (dump_section_map): Adjust as load commands

28
binutils/readelf.c
View File

@ -133,7 +133,7 @@
#include "elf/msp430.h"
#include "elf/nds32.h"
#include "elf/nios2.h"
#include "elf/or32.h"
#include "elf/or1k.h"
#include "elf/pj.h"
#include "elf/ppc.h"
#include "elf/ppc64.h"
@ -580,8 +580,6 @@ guess_is_rela (unsigned int e_machine)
case EM_MIPS:
case EM_MIPS_RS3_LE:
case EM_CYGNUS_M32R:
case EM_OPENRISC:
case EM_OR32:
case EM_SCORE:
case EM_XGATE:
return FALSE;
@ -629,6 +627,7 @@ guess_is_rela (unsigned int e_machine)
case EM_MT:
case EM_NDS32:
case EM_NIOS32:
case EM_OR1K:
case EM_PPC64:
case EM_PPC:
case EM_RL78:
@ -1185,9 +1184,8 @@ dump_relocations (FILE * file,
rtype = elf_h8_reloc_type (type);
break;
case EM_OPENRISC:
case EM_OR32:
rtype = elf_or32_reloc_type (type);
case EM_OR1K:
rtype = elf_or1k_reloc_type (type);
break;
case EM_PJ:
@ -2014,8 +2012,7 @@ get_machine_name (unsigned e_machine)
case EM_S390: return "IBM S/390";
case EM_SCORE: return "SUNPLUS S+Core";
case EM_XSTORMY16: return "Sanyo XStormy16 CPU core";
case EM_OPENRISC:
case EM_OR32: return "OpenRISC";
case EM_OR1K: return "OpenRISC 1000";
case EM_ARC_A5: return "ARC International ARCompact processor";
case EM_CRX: return "National Semiconductor CRX microprocessor";
case EM_ADAPTEVA_EPIPHANY: return "Adapteva EPIPHANY";
@ -2894,6 +2891,11 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
if (e_flags & EF_SH_FDPIC)
strcat (buf, ", fdpic");
break;
case EM_OR1K:
if (e_flags & EF_OR1K_NODELAY)
strcat (buf, ", no delay");
break;
case EM_SPARCV9:
if (e_flags & EF_SPARC_32PLUS)
@ -10485,9 +10487,8 @@ is_32bit_abs_reloc (unsigned int reloc_type)
return reloc_type == 12; /* R_NIOS2_BFD_RELOC_32. */
case EM_NIOS32:
return reloc_type == 1; /* R_NIOS_32. */
case EM_OPENRISC:
case EM_OR32:
return reloc_type == 1; /* R_OR32_32. */
case EM_OR1K:
return reloc_type == 1; /* R_OR1K_32. */
case EM_PARISC:
return (reloc_type == 1 /* R_PARISC_DIR32. */
|| reloc_type == 41); /* R_PARISC_SECREL32. */
@ -10575,6 +10576,8 @@ is_32bit_pcrel_reloc (unsigned int reloc_type)
return reloc_type == 3; /* R_ARM_REL32 */
case EM_MICROBLAZE:
return reloc_type == 2; /* R_MICROBLAZE_32_PCREL. */
case EM_OR1K:
return reloc_type == 9; /* R_OR1K_32_PCREL. */
case EM_PARISC:
return reloc_type == 9; /* R_PARISC_PCREL32. */
case EM_PPC:
@ -10740,6 +10743,8 @@ is_16bit_abs_reloc (unsigned int reloc_type)
return reloc_type == 13; /* R_NIOS2_BFD_RELOC_16. */
case EM_NIOS32:
return reloc_type == 9; /* R_NIOS_16. */
case EM_OR1K:
return reloc_type == 2; /* R_OR1K_16. */
case EM_TI_C6000:
return reloc_type == 2; /* R_C6000_ABS16. */
case EM_XC16X:
@ -10796,6 +10801,7 @@ is_none_reloc (unsigned int reloc_type)
case EM_C166: /* R_XC16X_NONE. */
case EM_ALTERA_NIOS2: /* R_NIOS2_NONE. */
case EM_NIOS32: /* R_NIOS_NONE. */
case EM_OR1K: /* R_OR1K_NONE. */
return reloc_type == 0;
case EM_AARCH64:
return reloc_type == 0 || reloc_type == 256;

7
binutils/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* binutils-all/objcopy.exp: Remove openrisc and or32 support. Add
support for or1k.
* binutils-all/objdump.exp: Likewise.
* binutils-all/dw2-decodedline-1.S: Likewise.
2014-03-26 Jiong Wang <jiong.wang@arm.com>
* binutils-all/aarch64/aarch64.exp: New test driver for AArch64.

16
binutils/testsuite/binutils-all/dw2-decodedline-1.S Normal file
View File

@ -0,0 +1,16 @@
.file "dw2-decodedline.c"
.file 1 "dw2-decodedline.c"
.file 2 "directory/file1.c"
.text
.globl f1
.type f1, %function
f1:
.loc 2 1 0
l.nop
.size f1, .-f1
.globl main
.type main, %function
main:
.loc 1 2 0
l.nop
.size main, .-main

1
binutils/testsuite/binutils-all/objcopy.exp
View File

@ -84,7 +84,6 @@ proc objcopy_test {testname srcfile} {
setup_xfail "m68*-*-*coff" "m68*-*-hpux*" "m68*-*-lynxos*"
setup_xfail "m68*-*-sysv*" "m68*-apple-aux*"
setup_xfail "m8*-*"
setup_xfail "or32-*-rtems*" "or32-*-coff"
setup_xfail "sh-*-coff*"
setup_xfail "tic80-*-*" "w65-*"

15
binutils/testsuite/binutils-all/objdump.exp
View File

@ -37,8 +37,8 @@ set cpus_expected [list]
lappend cpus_expected aarch64 alpha arc arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k
lappend cpus_expected pj powerpc pyramid romp rs6000 s390 sh sparc
lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k
lappend cpus_expected or1k or1knd pj powerpc pyramid romp rs6000 s390 sh sparc
lappend cpus_expected tahoe tic54x tic80 tilegx tms320c30 tms320c4x tms320c54x
lappend cpus_expected v850 vax we32k x86-64 xscale xtensa z8k z8001 z8002
@ -201,7 +201,7 @@ if { ![is_elf_format] || ![is_zlib_supported] } then {
}
# Test objdump -WL on a file that contains line information for multiple files and search directories.
# Not supported on mcore, moxie and openrisc targets because they do not (yet) support the generation
# Not supported on mcore and moxie targets because they do not (yet) support the generation
# of DWARF2 line debug information.
if { ![is_elf_format]
@ -211,12 +211,15 @@ if { ![is_elf_format]
|| [istarget "ia64*-*-*"]
|| [istarget "mcore-*-*"]
|| [istarget "moxie-*-*"]
|| [istarget "openrisc-*-*"]
|| [istarget "or32-*-*"]
} then {
unsupported "objump decode line"
} else {
if { ![binutils_assemble $srcdir/$subdir/dw2-decodedline.S tmpdir/dw2-decodedline.o] } then {
if { [istarget "or1k*-*-*"] } then {
set decodedline_testsrc $srcdir/$subdir/dw2-decodedline-1.S
} else {
set decodedline_testsrc $srcdir/$subdir/dw2-decodedline.S
}
if { ![binutils_assemble $decodedline_testsrc tmpdir/dw2-decodedline.o] } then {
fail "objdump decoded line"
}

10
cpu/ChangeLog
View File

@ -1,3 +1,13 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* openrisc.cpu: Delete.
* openrisc.opc: Delete.
* or1k.cpu: New file.
* or1k.opc: New file.
* or1kcommon.cpu: New file.
* or1korbis.cpu: New file.
* or1korfpx.cpu: New file.
2013-12-07 Mike Frysinger <vapier@gentoo.org>
* epiphany.opc: Remove +x file mode.

774
cpu/openrisc.cpu
View File

@ -1,774 +0,0 @@
; OpenRISC family. -*- Scheme -*-
; Copyright 2000, 2001, 2011 Free Software Foundation, Inc.
; Contributed by Johan Rydberg, jrydberg@opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
(include "simplify.inc")
; OpenRISC 1000 is an architecture of a family of open source,
; synthesizeable RISC microprocessor cores. It is a 32-bit load
; and store RISC architecture designed with emphasis on speed,
; compact instruction set and scalability. OpenRISC 1000 targets
; wide range of embedded environments.
(define-arch
(name openrisc)
(comment "OpenRISC 1000")
(insn-lsb0? #t)
(machs openrisc or1300)
(isas or32)
)
; Attributes
; An attribute to describe if a model has insn and/or data caches.
(define-attr
(for model)
(type enum)
(name HAS-CACHE)
(comment "if this model has caches")
(values DATA-CACHE INSN-CACHE)
)
; An attribute to describe if an insn can be in the delay slot or not.
(define-attr
(for insn)
(type boolean)
(name NOT-IN-DELAY-SLOT)
(comment "insn can't go in delay slot")
)
; IDOC attribute for instruction documentation.
(define-attr
(for insn)
(type enum)
(name IDOC)
(comment "insn kind for documentation")
(attrs META)
(values
(MEM - () "Memory")
(ALU - () "ALU")
(FPU - () "FPU")
(BR - () "Branch")
(PRIV - () "Priviledged")
(MISC - () "Miscellaneous")
)
)
; Enum for exception vectors.
(define-enum
(name e-exception)
(comment "exception vectors")
(attrs)
(prefix E_)
(values (("RESET") ("BUSERR" -) ("DPF" -) ("IPF" -) ("EXTINT" -) ("ALIGN" -)
("ILLEGAL" -) ("PEINT" -) ("DTLBMISS" -) ("ITLBMISS" -) ("RRANGE" -)
("SYSCALL" -) ("BREAK" -) ("RESERVED" -)))
)
; Instruction set parameters.
(define-isa
; Name of the ISA.
(name or32)
; Base insturction length. The insns is always 32 bits wide.
(base-insn-bitsize 32)
; Address of insn in delay slot
(setup-semantics (set-quiet (reg h-delay-insn) (add pc 4)))
)
; CPU family definitions.
(define-cpu
; CPU names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name openriscbf)
(comment "OpenRISC base family")
(endian big)
(word-bitsize 32)
)
; Generic machine
(define-mach
(name openrisc)
(comment "Generic OpenRISC cpu")
(cpu openriscbf)
(bfd-name "openrisc")
)
; OpenRISC 1300 machine
(define-mach
(name or1300)
(comment "OpenRISC 1300")
(cpu openriscbf)
(bfd-name "openrisc:1300")
)
; Model descriptions
; Generic OpenRISC model
(define-model
(name openrisc-1) (comment "OpenRISC generic model") (attrs)
(mach openrisc)
; Nothing special about this.
(unit u-exec "Execution Unit" () 1 1 () () () ())
)
; OpenRISC 1320
(define-model
(name or1320-1) (comment "OpenRISC 1320 model")
; This model has both instruction and data cache
(attrs (HAS-CACHE INSN-CACHE,DATA-CACHE))
(mach or1300)
; Nothing special about this.
(unit u-exec "Execution Unit" () 1 1 () () () ())
)
; Instruction fields.
; Attributes:
; . PCREL-ADDR pc relative value (for reloc and disassembly purposes)
; . ABS-ADDR absolute address (for reloc and disassembly purposes?)
; . RESERVED bits are not used to decode insn, must be all 0
; Instruction classes.
(dnf f-class "insn class" () 31 2)
(dnf f-sub "sub class" () 29 4)
; Register fields.
(dnf f-r1 "r1" () 25 5)
(dnf f-r2 "r2" () 20 5)
(dnf f-r3 "r3" () 15 5)
; Immediates.
(df f-simm16 "signed imm (16)" () 15 16 INT #f #f)
(dnf f-uimm16 "unsigned imm (16)" () 15 16)
(dnf f-uimm5 "unsigned imm (5)" () 4 5)
(df f-hi16 "high 16" () 15 16 INT #f #f)
(df f-lo16 "low 16" () 15 16 INT #f #f)
; Sub fields
(dnf f-op1 "op1" () 31 2)
(dnf f-op2 "op2" () 29 4)
(dnf f-op3 "op3" () 25 2)
(dnf f-op4 "op4" () 23 3)
(dnf f-op5 "op3" () 25 5)
(dnf f-op6 "op4" () 7 3)
(dnf f-op7 "op5" () 3 4)
(dnf f-i16-1 "uimm16-1" () 10 11)
(dnf f-i16-2 "uimm16-2" () 25 5)
; PC relative, 26-bit (2 shifted to right)
(df f-disp26 "disp26" (PCREL-ADDR) 25 26 INT
((value pc) (sra WI (sub WI value pc) (const 2)))
((value pc) (add WI (sll WI value (const 2)) pc)))
; absolute, 26-bit (2 shifted to right)
(df f-abs26 "abs26" (ABS-ADDR) 25 26 INT
((value pc) (sra WI pc (const 2)))
((value pc) (sll WI value (const 2))))
(define-multi-ifield
(name f-i16nc)
(comment "16 bit signed")
(attrs SIGN-OPT)
(mode HI)
(subfields f-i16-1 f-i16-2)
(insert (sequence ()
(set (ifield f-i16-2) (and (sra (ifield f-i16nc)
(const 11))
(const #x1f)))
(set (ifield f-i16-1) (and (ifield f-i16nc)
(const #x7ff)))))
(extract (sequence ()
(set (ifield f-i16nc) (c-raw-call SI "@arch@_sign_extend_16bit"
(or (sll (ifield f-i16-2)
(const 11))
(ifield f-i16-1))))))
)
; Enums.
; insn-class: bits 31-30
(define-normal-insn-enum insn-class "FIXME" () OP1_ f-class
(.map .str (.iota 4))
)
(define-normal-insn-enum insn-sub "FIXME" () OP2_ f-sub
(.map .str (.iota 16))
)
(define-normal-insn-enum insn-op3 "FIXME" () OP3_ f-op3
(.map .str (.iota 4))
)
(define-normal-insn-enum insn-op4 "FIXME" () OP4_ f-op4
(.map .str (.iota 8))
)
(define-normal-insn-enum insn-op5 "FIXME" () OP5_ f-op5
(.map .str (.iota 32))
)
(define-normal-insn-enum insn-op6 "FIXME" () OP6_ f-op6
(.map .str (.iota 8))
)
(define-normal-insn-enum insn-op7 "FIXME" () OP7_ f-op7
(.map .str (.iota 16))
)
; Hardware pieces.
; These entries list the elements of the raw hardware.
; They're also used to provide tables and other elements of the assembly
; language.
(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
(define-hardware
(name h-gr) (comment "general registers") (attrs PROFILE)
(type register WI (32))
(indices keyword ""
((r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
(r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14)
(r15 15) (r16 16) (r17 17) (r18 18) (r19 19) (r20 20)
(r21 21) (r22 22) (r23 23) (r24 24) (r25 25) (r26 26)
(r27 27) (r28 28) (r29 29) (r30 30) (r31 31) (lr 11)
(sp 1) (fp 2)))
)
(define-hardware
(name h-sr) (comment "special registers")
(type register WI (#x20000))
(get (index) (c-call SI "@arch@_h_sr_get_handler" index))
(set (index newval) (c-call VOID "@arch@_h_sr_set_handler" index newval))
)
(dnh h-hi16 "high 16 bits" () (immediate (INT 16)) () () ())
(dnh h-lo16 "low 16 bits" () (immediate (INT 16)) () () ())
(dsh h-cbit "condition bit" () (register BI))
(dsh h-delay-insn "delay insn addr" () (register SI))
; Instruction operands.
(dnop sr "special register" (SEM-ONLY) h-sr f-nil)
(dnop cbit "condition bit" (SEM-ONLY) h-cbit f-nil)
(dnop simm-16 "16 bit signed immediate" () h-sint f-simm16)
(dnop uimm-16 "16 bit unsigned immediate" () h-uint f-uimm16)
(dnop disp-26 "pc-rel 26 bit" () h-iaddr f-disp26)
(dnop abs-26 "abs 26 bit" () h-iaddr f-abs26)
(dnop uimm-5 "imm5" () h-uint f-uimm5)
(dnop rD "destination register" () h-gr f-r1)
(dnop rA "source register A" () h-gr f-r2)
(dnop rB "source register B" () h-gr f-r3)
(dnop op-f-23 "f-op23" () h-uint f-op4)
(dnop op-f-3 "f-op3" () h-uint f-op5)
; For hi(foo).
(define-operand
(name hi16) (comment "high 16 bit immediate, sign optional")
(attrs SIGN-OPT)
(type h-hi16)
(index f-simm16)
(handlers (parse "hi16"))
)
; For lo(foo)
(define-operand
(name lo16) (comment "low 16 bit immediate, sign optional")
(attrs SIGN-OPT)
(type h-lo16)
(index f-lo16)
(handlers (parse "lo16"))
)
(define-operand
(name ui16nc)
(comment "16 bit immediate, sign optional")
(attrs)
(type h-lo16)
(index f-i16nc)
(handlers (parse "lo16"))
)
; Instructions.
; Branch releated instructions
(dni l-j "jump (absolute iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.j ${abs-26}"
(+ OP1_0 OP2_0 abs-26)
; We execute the delay slot before doin' the real branch
(delay 1 (set pc abs-26))
()
)
(dni l-jal "jump and link (absolute iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.jal ${abs-26}"
(+ OP1_0 OP2_1 abs-26)
; We execute the delay slot before doin' the real branch
; Set LR to (delay insn addr + 4)
(sequence ()
(set (reg h-gr 11) (add (reg h-delay-insn) 4))
(delay 1 (set pc abs-26)))
()
)
(dni l-jr "jump register (absolute iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.jr $rA"
(+ OP1_0 OP2_5 OP3_0 OP4_0 rA uimm-16)
; We execute the delay slot before doin' the real branch
(delay 1 (set pc rA))
()
)
(dni l-jalr "jump register and link (absolute iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.jalr $rA"
(+ OP1_0 OP2_5 OP3_0 OP4_1 rA uimm-16)
; We save the value of rA in a temporary slot before setting
; the link register. This because "l.jalr r11" would cause
; a forever-and-ever loop otherwise.
;
; We execute the delay slot before doin' the real branch
(sequence ((WI tmp-slot))
(set tmp-slot rA)
(set (reg h-gr 11) (add (reg h-delay-insn) 4))
(delay 1 (set pc tmp-slot)))
()
)
(dni l-bal "branch and link (pc relative iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.bal ${disp-26}"
(+ OP1_0 OP2_2 disp-26)
; We execute the delay slot before doin' the real branch
; Set LR to (delay insn addr + 4)
(sequence ()
(set (reg h-gr 11) (add (reg h-delay-insn) 4))
(delay 1 (set pc disp-26)))
()
)
(dni l-bnf "branch if condition bit not set (pc relative iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.bnf ${disp-26}"
(+ OP1_0 OP2_3 disp-26)
; We execute the delay slot before doin' the real branch
(if (eq cbit 0)
(sequence ()
(delay 1 (set pc disp-26))))
()
)
(dni l-bf "branch if condition bit is set (pc relative iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.bf ${disp-26}"
(+ OP1_0 OP2_4 disp-26)
; We execute the delay slot before doin' the real branch
(if (eq cbit 1)
(sequence ()
(delay 1 (set pc disp-26))))
()
)
(dni l-brk "break (exception)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.brk ${uimm-16}"
(+ OP1_0 OP2_5 OP3_3 OP4_0 rA uimm-16)
; FIXME should we do it like this ??
(c-call VOID "@cpu@_cpu_brk" uimm-16)
()
)
(dni l-rfe "return from exception"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.rfe $rA"
(+ OP1_0 OP2_5 OP3_0 OP4_2 rA uimm-16)
(sequence ()
(delay 1 (set pc (c-call SI "@cpu@_cpu_rfe" rA))))
()
)
(dni l-sys "syscall (exception)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.sys ${uimm-16}"
(+ OP1_0 OP2_5 OP3_2 OP4_0 rA uimm-16)
(sequence()
(delay 1 (set pc (c-call SI "@cpu@_except" pc
#xc00 uimm-16))))
()
)
; Misc instructions
(dni l-nop "nop"
()
"l.nop"
(+ OP1_0 OP2_5 OP3_1 OP4_0 rA uimm-16)
(nop)
()
)
(dnmi l-ret "ret" ()
"l.ret"
(emit l-jr (rA 11) (uimm-16 0))
)
(dni l-movhi "movhi"
(DELAY-SLOT)
"l.movhi $rD,$hi16"
(+ OP1_0 OP2_6 hi16 rD rA)
(set rD (sll WI hi16 (const 16)))
()
)
; System releated instructions
(dni l-mfsr "mfsr"
(DELAY-SLOT)
"l.mfsr $rD,$rA"
(+ OP1_0 OP2_7 rD rA uimm-16)
(set rD (c-call SI "@cpu@_cpu_mfsr" rA))
()
)
(dni l-mtsr "mtsr"
(DELAY-SLOT)
"l.mtsr $rA,$rB"
(+ OP1_1 OP2_0 rA rB rD (f-i16-1 0))
(c-call VOID "@cpu@_cpu_mtsr" rA rB)
()
)
; Load instructions
(dni l-lw "load word"
(DELAY-SLOT)
"l.lw $rD,${simm-16}($rA)"
(+ OP1_2 OP2_0 rD rA simm-16)
(set rD (mem SI (add rA simm-16)))
()
)
(dni l-lbz "load byte (zero extend)"
(DELAY-SLOT)
"l.lbz $rD,${simm-16}($rA)"
(+ OP1_2 OP2_1 rD rA simm-16)
(set rD (zext SI (mem QI (add rA simm-16))))
()
)
(dni l-lbs "load byte (sign extend)"
(DELAY-SLOT)
"l.lbs $rD,${simm-16}($rA)"
(+ OP1_2 OP2_2 rD rA simm-16)
(set rD (ext SI (mem QI (add rA simm-16))))
()
)
(dni l-lhz "load halfword (zero extend)"
(DELAY-SLOT)
"l.lhz $rD,${simm-16}($rA)"
(+ OP1_2 OP2_3 rD simm-16 rA)
(set rD (zext SI (mem HI (add rA simm-16))))
()
)
(dni l-lhs "load halfword (sign extend)"
(DELAY-SLOT)
"l.lhs $rD,${simm-16}($rA)"
(+ OP1_2 OP2_4 rD rA simm-16)
(set rD (ext SI (mem HI (add rA simm-16))))
()
)
; Store instructions
;
; We have to use a multi field since the integer is splited over 2 fields
(define-pmacro (store-insn mnemonic op2-op mode-op)
(begin
(dni (.sym l- mnemonic)
(.str "l." mnemonic " imm(reg)/reg")
(DELAY-SLOT)
(.str "l." mnemonic " ${ui16nc}($rA),$rB")
(+ OP1_3 op2-op rB rD ui16nc)
(set (mem mode-op (add rA ui16nc)) rB)
()
)
)
)
(store-insn sw OP2_5 SI)
(store-insn sb OP2_6 QI)
(store-insn sh OP2_7 HI)
; Shift and rotate instructions
; Reserved fields.
(dnf f-f-15-8 "nop" (RESERVED) 15 8)
(dnf f-f-10-3 "nop" (RESERVED) 10 3)
(dnf f-f-4-1 "nop" (RESERVED) 4 1)
(dnf f-f-7-3 "nop" (RESERVED) 7 3)
(define-pmacro (shift-insn mnemonic op4-op)
(begin
(dni (.sym l- mnemonic)
(.str "l." mnemonic " reg/reg/reg")
()
(.str "l." mnemonic " $rD,$rA,$rB")
(+ OP1_3 OP2_8 rD rA rB (f-f-10-3 0) op4-op (f-f-4-1 0) OP7_8)
(set rD (mnemonic rA rB))
()
)
(dni (.sym l- mnemonic "i")
(.str "l." mnemonic " reg/reg/imm")
()
(.str "l." mnemonic "i $rD,$rA,${uimm-5}")
(+ OP1_2 OP2_13 rD rA (f-f-15-8 0) op4-op uimm-5)
(set rD (mnemonic rA uimm-5))
()
)
)
)
(shift-insn sll OP6_0)
(shift-insn srl OP6_1)
(shift-insn sra OP6_2)
(shift-insn ror OP6_4)
; Arethmetic insns
; Reserved fields.
(dnf f-f-10-7 "nop" (RESERVED) 10 7)
(define-pmacro (ar-insn-u mnemonic op2-op op5-op)
(begin
(dni (.sym l- mnemonic)
(.str "l." mnemonic " reg/reg/reg")
()
(.str "l." mnemonic " $rD,$rA,$rB")
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op)
(set rD (mnemonic rA rB))
()
)
(dni (.sym l- mnemonic "i")
(.str "l." mnemonic " reg/reg/lo16")
()
(.str "l." mnemonic "i $rD,$rA,$lo16")
(+ OP1_2 op2-op rD rA lo16)
(set rD (mnemonic rA (and lo16 #xffff)))
()
)
)
)
(define-pmacro (ar-insn-s mnemonic op2-op op5-op)
(begin
(dni (.sym l- mnemonic)
(.str "l." mnemonic " reg/reg/reg")
()
(.str "l." mnemonic " $rD,$rA,$rB")
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op)
(set rD (mnemonic rA rB))
()
)
(dni (.sym l- mnemonic "i")
(.str "l." mnemonic " reg/reg/lo16")
()
(.str "l." mnemonic "i $rD,$rA,$lo16")
(+ OP1_2 op2-op rD rA lo16)
(set rD (mnemonic rA lo16))
()
)
)
)
(ar-insn-s add OP2_5 OP7_0)
;;(ar-op-s addc OP2_5 OP7_0)
(ar-insn-s sub OP2_7 OP7_2)
(ar-insn-u and OP2_8 OP7_3)
(ar-insn-u or OP2_9 OP7_4)
(ar-insn-u xor OP2_10 OP7_5)
(ar-insn-u mul OP2_11 OP7_6)
;;(ar-op-u mac OP2_12 OP7_7)
(dni l-div "divide (signed)"
(DELAY-SLOT)
"l.div $rD,$rA,$rB"
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_9)
(if VOID (eq rB (const 0))
(c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL))
(set rD (div rA rB)))
()
)
(dni l-divu "divide (unsigned)"
(DELAY-SLOT)
"l.divu $rD,$rA,$rB"
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_10)
(if VOID (eq rB (const 0))
(c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL))
(set rD (udiv rA rB)))
()
)
; Compare instructions
; Reserved fields.
(dnf f-f-10-11 "nop" (RESERVED) 10 11)
; Register compare (both signed and unsigned)
(define-pmacro (sf-insn-r op1-op op2-op op3-op op3-op-2 sem-op)
(begin
(dni (.sym l- "sf" (.sym sem-op "s"))
(.str "l." mnemonic " reg/reg")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) "s $rA,$rB")
(+ op1-op op2-op op3-op-2 rA rB (f-f-10-11 0))
(set cbit (sem-op rA rB))
()
)
(dni (.sym l- "sf" (.sym sem-op "u"))
(.str "l." mnemonic " reg/reg")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) "u $rA,$rB")
(+ op1-op op2-op op3-op rA rB (f-f-10-11 0))
(set cbit (sem-op rA rB))
()
)
)
)
; Immediate compare (both signed and unsigned)
(define-pmacro (sf-insn-i op1-op op2-op op3-op op3-op-2 sem-op)
(begin
(dni (.sym l- "sf" (.sym sem-op "si"))
(.str "l." mnemonic "si reg/imm")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) "si $rA,${simm-16}")
(+ op1-op op2-op op3-op-2 rA simm-16)
(set cbit (sem-op rA simm-16))
()
)
(dni (.sym l- "sf" (.sym sem-op "ui"))
(.str "l." mnemonic "ui reg/imm")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) "ui $rA,${uimm-16}")
(+ op1-op op2-op op3-op rA uimm-16)
(set cbit (sem-op rA uimm-16))
()
)
)
)
(define-pmacro (sf-insn op5-op sem-op)
(begin
(dni (.sym l- "sf" sem-op)
(.str "l." mnemonic " reg/reg")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) " $rA,$rB")
(+ OP1_3 OP2_9 op5-op rA rB (f-f-10-11 0))
(set cbit (sem-op rA rB))
()
)
(dni (.sym l- "sf" (.sym sem-op "i"))
(.str "l." mnemonic "i reg/imm")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) "i $rA,${simm-16}")
(+ OP1_2 OP2_14 op5-op rA simm-16)
(set cbit (sem-op rA simm-16))
()
)
)
)
(sf-insn-r OP1_3 OP2_9 OP5_2 OP5_6 gt)
(sf-insn-r OP1_3 OP2_9 OP5_3 OP5_7 ge)
(sf-insn-r OP1_3 OP2_9 OP5_4 OP5_8 lt)
(sf-insn-r OP1_3 OP2_9 OP5_5 OP5_9 le)
(sf-insn-i OP1_2 OP2_14 OP5_2 OP5_6 gt)
(sf-insn-i OP1_2 OP2_14 OP5_3 OP5_7 ge)
(sf-insn-i OP1_2 OP2_14 OP5_4 OP5_8 lt)
(sf-insn-i OP1_2 OP2_14 OP5_5 OP5_9 le)
(sf-insn OP5_0 eq)
(sf-insn OP5_1 ne)

164
cpu/openrisc.opc
View File

@ -1,164 +0,0 @@
/* OpenRISC opcode support. -*- C -*-
Copyright 2000, 2001, 2003, 2005, 2011 Free Software Foundation, Inc.
Contributed by Red Hat Inc;
This file is part of the GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* This file is an addendum to or32.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
to assembly/disassembly where parsing/printing can be quite involved.
Such things aren't really part of the specification of the cpu, per se,
so .cpu files provide the general framework and .opc files handle the
nitty-gritty details as necessary.
Each section is delimited with start and end markers.
<arch>-opc.h additions use: "-- opc.h"
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h" */
/* -- opc.h */
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 64
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
extern long openrisc_sign_extend_16bit (long);
/* -- */
/* -- opc.c */
/* -- */
/* -- asm.c */
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
long
openrisc_sign_extend_16bit (long value)
{
return ((value & 0xffff) ^ 0x8000) - 0x8000;
}
/* Handle hi(). */
static const char *
parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
unsigned long ret;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "hi(", 3) == 0)
{
bfd_vma value;
*strp += 3;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value >>= 16;
ret = value;
}
else
{
if (**strp == '-')
{
long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
ret = value;
}
else
{
unsigned long value;
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
ret = value;
}
}
*valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000;
return errmsg;
}
/* Handle lo(). */
static const char *
parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
unsigned long ret;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "lo(", 3) == 0)
{
bfd_vma value;
*strp += 3;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
ret = value;
}
else
{
if (**strp == '-')
{
long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
ret = value;
}
else
{
unsigned long value;
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
ret = value;
}
}
*valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000;
return errmsg;
}
/* -- */
/* -- ibd.h */
extern long openrisc_sign_extend_16bit (long);
/* -- */

131
cpu/or1k.cpu Normal file
View File

@ -0,0 +1,131 @@
; OpenRISC 1000 architecture. -*- Scheme -*-
; Copyright 2000-2014 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
; Modified by Julius Baxter, juliusbaxter@gmail.com
; Modified by Peter Gavin, pgavin@gmail.com
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, see <http://www.gnu.org/licenses/>
(include "simplify.inc")
; The OpenRISC family is a set of RISC microprocessor architectures with an
; emphasis on scalability and is targetted at embedded use.
; The CPU RTL development is a collaborative open source effort.
; http://opencores.org/or1k
; http://openrisc.net
(define-arch
(name or1k)
(comment "OpenRISC 1000")
(default-alignment aligned)
(insn-lsb0? #t)
(machs or32 or32nd or64 or64nd)
(isas openrisc)
)
; Instruction set parameters.
(define-isa
; Name of the ISA.
(name openrisc)
; Base insturction length. The insns are always 32 bits wide.
(base-insn-bitsize 32)
)
(define-pmacro OR32-MACHS or32,or32nd)
(define-pmacro OR64-MACHS or64,or64nd)
(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
(define-pmacro ORFPX-MACHS or32,or32nd,or64,or64nd)
(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
(define-pmacro ORFPX64-MACHS or64,or64nd)
(define-attr
(for model)
(type boolean)
(name NO-DELAY-SLOT)
(comment "does not have delay slots")
)
(if (keep-mach? (or32 or32nd))
(begin
(define-cpu
(name or1k32bf)
(comment "OpenRISC 1000 32-bit CPU family")
(insn-endian big)
(data-endian big)
(word-bitsize 32)
(file-transform "")
)
(define-mach
(name or32)
(comment "Generic OpenRISC 1000 32-bit CPU")
(cpu or1k32bf)
(bfd-name "or1k")
)
(define-mach
(name or32nd)
(comment "Generic OpenRISC 1000 32-bit CPU")
(cpu or1k32bf)
(bfd-name "or1knd")
)
; OpenRISC 1200 - 32-bit or1k CPU implementation
(define-model
(name or1200) (comment "OpenRISC 1200 model")
(attrs)
(mach or32)
(unit u-exec "Execution Unit" () 1 1 () () () ())
)
; OpenRISC 1200 - 32-bit or1k CPU implementation
(define-model
(name or1200nd) (comment "OpenRISC 1200 model")
(attrs NO-DELAY-SLOT)
(mach or32nd)
(unit u-exec "Execution Unit" () 1 1 () () () ())
)
)
)
(if (keep-mach? (or64 or64nd))
(begin
(define-cpu
(name or1k64bf)
(comment "OpenRISC 1000 64-bit CPU family")
(insn-endian big)
(data-endian big)
(word-bitsize 64)
(file-transform "64")
)
(define-mach
(name or64)
(comment "Generic OpenRISC 1000 64-bit CPU")
(cpu or1k64bf)
(bfd-name "or1k64")
)
(define-mach
(name or64nd)
(comment "Generic OpenRISC 1000 ND 64-bit CPU")
(cpu or1k64bf)
(bfd-name "or1k64nd")
)
)
)
(include "or1kcommon.cpu")
(include "or1korbis.cpu")
(include "or1korfpx.cpu")

421
cpu/or1k.opc Normal file
View File

@ -0,0 +1,421 @@
/* OpenRISC 1000 opcode support. -*- C -*-
Copyright 2000-2014 Free Software Foundation, Inc.
Originally ontributed for OR32 by Red Hat Inc;
This file is part of the GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
/* This file is an addendum to or1k.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
to assembly/disassembly where parsing/printing can be quite involved.
Such things aren't really part of the specification of the cpu, per se,
so .cpu files provide the general framework and .opc files handle the
nitty-gritty details as necessary.
Each section is delimited with start and end markers.
<arch>-opc.h additions use: "-- opc.h"
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h" */
/* -- opc.h */
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
/* -- */
/* -- opc.c */
/* -- */
/* -- asm.c */
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
static const char *
parse_disp26 (CGEN_CPU_DESC cd,
const char ** strp,
int opindex,
int opinfo,
enum cgen_parse_operand_result * resultp,
bfd_vma * valuep)
{
const char *errmsg = NULL;
enum cgen_parse_operand_result result_type;
if (strncasecmp (*strp, "plt(", 4) == 0)
{
bfd_vma value;
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_OR1K_PLT26,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 2) & 0xffff;
*valuep = value;
return errmsg;
}
return cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep);
}
static const char *
parse_simm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
long ret;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "hi(", 3) == 0)
{
bfd_vma value;
*strp += 3;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
& result_type, & value);
if (**strp != ')')
errmsg = MISSING_CLOSING_PARENTHESIS;
++*strp;
ret = value;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
ret >>= 16;
ret &= 0xffff;
ret = (ret ^ 0x8000) - 0x8000;
}
}
else if (strncasecmp (*strp, "lo(", 3) == 0)
{
bfd_vma value;
*strp += 3;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
ret = value;
if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
ret &= 0xffff;
ret = (ret ^ 0x8000) - 0x8000;
}
}
else if (strncasecmp (*strp, "got(", 4) == 0)
{
bfd_vma value;
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_OR1K_GOT16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gotpchi(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_GOTPC_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gotpclo(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_GOTPC_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gotoffhi(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_GOTOFF_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gotofflo(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_GOTOFF_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tlsgdhi(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_GD_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tlsgdlo(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_GD_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tlsldmhi(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LDM_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tlsldmlo(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LDM_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "dtpoffhi(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LDO_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "dtpofflo(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LDO_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gottpoffhi(", 11) == 0)
{
bfd_vma value;
*strp += 11;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_IE_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gottpofflo(", 11) == 0)
{
bfd_vma value;
*strp += 11;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_IE_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tpoffhi(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LE_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tpofflo(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LE_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else
{
long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
ret = value;
}
if (errmsg == NULL)
*valuep = ret;
return errmsg;
}
static const char *
parse_uimm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, unsigned long * valuep)
{
const char *errmsg = parse_simm16(cd, strp, opindex, (long *) valuep);
if (errmsg == NULL)
*valuep &= 0xffff;
return errmsg;
}
/* -- */
/* -- ibd.h */
/* -- */

360
cpu/or1kcommon.cpu Normal file
View File

@ -0,0 +1,360 @@
; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*-
; Copyright 2000-2014 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
; Modified by Julius Baxter, juliusbaxter@gmail.com
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, see <http://www.gnu.org/licenses/>
; Hardware pieces.
; These entries list the elements of the raw hardware.
; They're also used to provide tables and other elements of the assembly
; language.
(define-hardware
(name h-pc)
(comment "program counter")
(attrs PC (MACH ORBIS-MACHS))
(type pc UWI)
)
(define-pmacro REG-INDICES
((r0 0)
(r1 1)
(r2 2)
(r3 3)
(r4 4)
(r5 5)
(r6 6)
(r7 7)
(r8 8)
(r9 9)
(r10 10)
(r11 11)
(r12 12)
(r13 13)
(r14 14)
(r15 15)
(r16 16)
(r17 17)
(r18 18)
(r19 19)
(r20 20)
(r21 21)
(r22 22)
(r23 23)
(r24 24)
(r25 25)
(r26 26)
(r27 27)
(r28 28)
(r29 29)
(r30 30)
(r31 31)
(lr 9)
(sp 1)
(fp 2))
)
(define-hardware
(name h-fsr)
(comment "floating point registers (single, virtual)")
(attrs VIRTUAL (MACH ORFPX32-MACHS))
(type register SF (32))
(indices keyword "" REG-INDICES)
(get (index) (subword SF (trunc SI (reg h-gpr index)) 0))
(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
)
(define-hardware
(name h-fdr) (comment "floating point registers (double, virtual)")
(attrs VIRTUAL (MACH ORFPX64-MACHS))
(type register DF (32))
(indices keyword "" REG-INDICES)
(get (index) (subword DF (trunc DI (reg h-gpr index)) 0))
(set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
)
(define-hardware
(name h-spr) (comment "special purpose registers")
(attrs VIRTUAL (MACH ORBIS-MACHS))
(type register UWI (#x20000))
(get (index) (c-call UWI "@cpu@_h_spr_get_raw" index))
(set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval))
)
(define-pmacro spr-shift 11)
(define-pmacro (spr-address spr-group spr-index)
(or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
(enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
(define-hardware
(name h-gpr) (comment "general registers")
(attrs (MACH ORBIS-MACHS))
(type register UWI (32))
(indices keyword "" REG-INDICES)
(get (index) (reg UWI h-spr (add index (spr-address SYS GPR0))))
(set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
)
(define-normal-enum
except-number
"Exception numbers"
()
EXCEPT-
(("NONE" #x00)
("RESET" #x01)
("BUSERR" #x02)
("DPF" #x03)
("IPF" #x04)
("TICK" #x05)
("ALIGN" #x06)
("ILLEGAL" #x07)
("INT" #x08)
("DTLBMISS" #x09)
("ITLBMISS" #x0a)
("RANGE" #x0b)
("SYSCALL" #x0c)
("FPE" #x0d)
("TRAP" #x0e)
)
)
(define-pmacro (raise-exception exnum)
(c-call VOID "@cpu@_exception" pc exnum))
(define-normal-enum
spr-groups
"special purpose register groups"
()
SPR-GROUP-
(("SYS" #x0)
("DMMU" #x1)
("IMMU" #x2)
("DCACHE" #x3)
("ICACHE" #x4)
("MAC" #x5)
("DEBUG" #x6)
("PERF" #x7)
("POWER" #x8)
("PIC" #x9)
("TICK" #xa)
("FPU" #xb)
)
)
(define-pmacro (spr-reg-info)
(.splice
(SYS VR #x000 "version register")
(SYS UPR #x001 "unit present register")
(SYS CPUCFGR #x002 "cpu configuration register")
(SYS DMMUCFGR #x003 "Data MMU configuration register")
(SYS IMMUCFGR #x004 "Insn MMU configuration register")
(SYS DCCFGR #x005 "Data cache configuration register")
(SYS ICCFGR #x006 "Insn cache configuration register")
(SYS DCFGR #x007 "Debug configuration register")
(SYS PCCFGR #x008 "Performance counters configuration register")
(SYS NPC #x010 "Next program counter")
(SYS SR #x011 "Supervision Regsiter")
(SYS PPC #x012 "Previous program counter")
(SYS FPCSR #x014 "Floating point control status register")
(.unsplice
(.map (.pmacro (n) (.splice SYS (.sym "EPCR" n) (.add n #x20) (.str "Exception PC register " n)))
(.iota #x10)))
(.unsplice
(.map (.pmacro (n) (.splice SYS (.sym "EEAR" n) (.add n #x30) (.str "Exception effective address register " n)))
(.iota #x10)))
(.unsplice
(.map (.pmacro (n) (.splice SYS (.sym "ESR" n) (.add n #x40) (.str "Exception supervision register " n)))
(.iota #x10)))
(.unsplice
(.map (.pmacro (n) (.splice SYS (.sym "GPR" n) (.add n #x400) (.str "General purpose register " n)))
(.iota #x200)))
(MAC MACLO #x001 "Multiply and accumulate result (low)")
(MAC MACHI #x002 "Multiply and accumulate result (high)")
(TICK TTMR #x000 "Tick timer mode register")
)
)
(define-normal-enum
spr-reg-indices
"special purpose register indicies"
()
SPR-INDEX-
(.map (.pmacro (args)
(.apply (.pmacro (group index n comment)
((.sym group "-" index) n))
args)
)
(spr-reg-info)
)
)
(define-pmacro (define-h-spr-reg spr-group spr-index n spr-comment)
(define-hardware
(name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index)))
(comment spr-comment)
(attrs VIRTUAL (MACH ORBIS-MACHS))
(type register UWI)
(get () (reg UWI h-spr (spr-address spr-group spr-index)))
(set (newval) (set (reg UWI h-spr (spr-address spr-group spr-index)) newval))
)
)
(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-reg args)) (spr-reg-info))))
(define-pmacro (spr-field-info)
((SYS VR REV 5 0 "revision field")
(SYS VR CFG 23 16 "configuration template field")
(SYS VR VER 31 24 "version field")
(SYS UPR UP 0 0 "UPR present bit")
(SYS UPR DCP 1 1 "data cache present bit")
(SYS UPR ICP 2 2 "insn cache present bit")
(SYS UPR DMP 3 3 "data MMU present bit")
(SYS UPR MP 4 4 "MAC unit present bit")
(SYS UPR IMP 5 5 "insn MMU present bit")
(SYS UPR DUP 6 6 "debug unit present bit")
(SYS UPR PCUP 7 7 "performance counters unit present bit")
(SYS UPR PICP 8 8 "programmable interrupt controller present bit")
(SYS UPR PMP 9 9 "power management present bit")
(SYS UPR TTP 10 10 "tick timer present bit")
(SYS UPR CUP 31 24 "custom units present field")
(SYS CPUCFGR NSGR 3 0 "number of shadow GPR files field")
(SYS CPUCFGR CGF 4 4 "custom GPR file bit")
(SYS CPUCFGR OB32S 5 5 "ORBIS32 supported bit")
(SYS CPUCFGR OB64S 6 6 "ORBIS64 supported bit")
(SYS CPUCFGR OF32S 7 7 "ORFPX32 supported bit")
(SYS CPUCFGR OF64S 8 8 "ORFPX64 supported bit")
(SYS CPUCFGR OV64S 9 9 "ORVDX64 supported bit")
(SYS CPUCFGR ND 10 10 "no transfer delay bit")
(SYS SR SM 0 0 "supervisor mode bit")
(SYS SR TEE 1 1 "tick timer exception enabled bit")
(SYS SR IEE 2 2 "interrupt exception enabled bit")
(SYS SR DCE 3 3 "data cache enabled bit")
(SYS SR ICE 4 4 "insn cache enabled bit")
(SYS SR DME 5 5 "data MMU enabled bit")
(SYS SR IME 6 6 "insn MMU enabled bit")
(SYS SR LEE 7 7 "little endian enabled bit")
(SYS SR CE 8 8 "CID enable bit")
(SYS SR F 9 9 "flag bit")
(SYS SR CY 10 10 "carry bit")
(SYS SR OV 11 11 "overflow bit")
(SYS SR OVE 12 12 "overflow exception enabled bit")
(SYS SR DSX 13 13 "delay slot exception bit")
(SYS SR EPH 14 14 "exception prefix high bit")
(SYS SR FO 15 15 "fixed one bit")
(SYS SR SUMRA 16 16 "SPRs user mode read access bit")
(SYS SR CID 31 28 "context ID field")
(SYS FPCSR FPEE 0 0 "floating point exceptions enabled bit")
(SYS FPCSR RM 2 1 "floating point rounding mode field")
(SYS FPCSR OVF 3 3 "floating point overflow flag bit")
(SYS FPCSR UNF 4 4 "floating point underflow bit")
(SYS FPCSR SNF 5 5 "floating point SNAN flag bit")
(SYS FPCSR QNF 6 6 "floating point QNAN flag bit")
(SYS FPCSR ZF 7 7 "floating point zero flag bit")
(SYS FPCSR IXF 8 8 "floating point inexact flag bit")
(SYS FPCSR IVF 9 9 "floating point invalid flag bit")
(SYS FPCSR INF 10 10 "floating point infinity flag bit")
(SYS FPCSR DZF 11 11 "floating point divide by zero flag bit")
)
)
(define-normal-enum
spr-field-msbs
"SPR field msb positions"
()
SPR-FIELD-MSB-
(.map (.pmacro (args)
(.apply (.pmacro (group index field msb lsb comment)
((.sym group "-" index "-" field) msb)
)
args
)
)
(spr-field-info)
)
)
(define-normal-enum
spr-field-lsbs
"SPR field lsb positions"
()
SPR-FIELD-SIZE-
(.map (.pmacro (args)
(.apply (.pmacro (group index field msb lsb comment)
((.sym group "-" index "-" field) lsb)
)
args
)
)
(spr-field-info)
)
)
(define-normal-enum
spr-field-masks
"SPR field masks"
()
SPR-FIELD-MASK-
(.map (.pmacro (args)
(.apply (.pmacro (group index field msb lsb comment)
(.splice (.str group "-" index "-" field) (.sll (.inv (.sll (.inv 0) (.add (.sub msb lsb) 1))) lsb))
)
args
)
)
(spr-field-info)
)
)
(define-pmacro (define-h-spr-field spr-group spr-index spr-field spr-field-msb spr-field-lsb spr-field-comment)
(.let ((spr-field-name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index) "-" (.downcase spr-field)))
)
(begin
(define-hardware
(name spr-field-name)
(comment spr-field-comment)
(attrs VIRTUAL (MACH ORBIS-MACHS))
(type register UWI)
(get () (c-call UWI "@cpu@_h_spr_field_get_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb))
(set (value) (c-call VOID "@cpu@_h_spr_field_set_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb value))
)
)
)
)
(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-field args)) (spr-field-info))))
(define-attr
(type boolean)
(for insn)
(name DELAYED-CTI)
(comment "delayed control transfer instruction")
(values #f #t)
(default #f)
)
(define-attr
(for insn)
(type boolean)
(name NOT-IN-DELAY-SLOT)
(comment "instruction cannot be in delay slot")
(values #f #t)
(default #f)
)
(define-attr
(for insn)
(type boolean)
(name FORCED-CTI)
(comment "instruction may forcefully transfer control (e.g., rfe)")
)

1080
cpu/or1korbis.cpu Normal file
View File

File diff suppressed because it is too large Load Diff

222
cpu/or1korfpx.cpu Normal file
View File

@ -0,0 +1,222 @@
; OpenRISC 1000 architecture. -*- Scheme -*-
; Copyright 2000-2014 Free Software Foundation, Inc.
; Contributed by Peter Gavin, pgavin@gmail.com
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, see <http://www.gnu.org/licenses/>
; Initial ORFPX32 instruction set
; I'm not sure how CGEN handles rounding in FP operations, except for
; in conversions to/from integers. So lf.add, lf.sub, lf.mul, and
; lf.div do not round according to the FPCSR RM field.
; NaN, overflow, and underflow are not yet handled either.
(define-normal-insn-enum insn-opcode-float-regreg
"floating point reg/reg insn opcode enums" ()
OPC_FLOAT_REGREG_ f-op-7-8
(("ADD_S" #x00)
("SUB_S" #x01)
("MUL_S" #x02)
("DIV_S" #x03)
("ITOF_S" #x04)
("FTOI_S" #x05)
("REM_S" #x06)
("MADD_S" #x07)
("SFEQ_S" #x08)
("SFNE_S" #x09)
("SFGT_S" #x0a)
("SFGE_S" #x0b)
("SFLT_S" #x0c)
("SFLE_S" #x0d)
("ADD_D" #x10)
("SUB_D" #x11)
("MUL_D" #x12)
("DIV_D" #x13)
("ITOF_D" #x14)
("FTOI_D" #x15)
("REM_D" #x16)
("MADD_D" #x17)
("SFEQ_D" #x18)
("SFNE_D" #x19)
("SFGT_D" #x1a)
("SFGE_D" #x1b)
("SFLT_D" #x1c)
("SFLE_D" #x1d)
("CUST1_S" #xd0)
("CUST1_D" #xe0)
)
)
(dnop rDSF "destination register (single floating point mode)" () h-fsr f-r1)
(dnop rASF "source register A (single floating point mode)" () h-fsr f-r2)
(dnop rBSF "source register B (single floating point mode)" () h-fsr f-r3)
(dnop rDDF "destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
(dnop rADF "source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
(dnop rBDF "source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
(define-pmacro (float-regreg-insn mnemonic)
(begin
(dni (.sym lf- mnemonic -s)
(.str "lf." mnemonic ".s reg/reg/reg")
((MACH ORFPX-MACHS))
(.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF")
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S))
(set SF rDSF (mnemonic SF rASF rBSF))
()
)
(dni (.sym lf- mnemonic -d)
(.str "lf." mnemonic ".d reg/reg/reg")
((MACH ORFPX64-MACHS))
(.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF")
(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
(set DF rDDF (mnemonic DF rADF rBDF))
()
)
)
)
(float-regreg-insn add)
(float-regreg-insn sub)
(float-regreg-insn mul)
(float-regreg-insn div)
(dni lf-rem-s
"lf.rem.s reg/reg/reg"
((MACH ORFPX-MACHS))
"lf.rem.s $rDSF,$rASF,$rBSF"
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S)
(set SF rDSF (rem SF rASF rBSF))
()
)
(dni lf-rem-d
"lf.rem.d reg/reg/reg"
((MACH ORFPX64-MACHS))
"lf.rem.d $rDDF,$rADF,$rBDF"
(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
(set DF rDDF (mod DF rADF rBDF))
()
)
(define-pmacro (get-rounding-mode)
(case INT sys-fpcsr-rm
((0) 1) ; TIES-TO-EVEN -- I'm assuming this is what is meant by "round to nearest"
((1) 3) ; TOWARD-ZERO
((2) 4) ; TOWARD-POSITIVE
(else 5) ; TOWARD-NEGATIVE
)
)
(dni lf-itof-s
"lf.itof.s reg/reg"
((MACH ORFPX-MACHS))
"lf.itof.s $rDSF,$rA"
(+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S)
(set SF rDSF (float SF (get-rounding-mode) (trunc SI rA)))
()
)
(dni lf-itof-d
"lf.itof.d reg/reg"
((MACH ORFPX64-MACHS))
"lf.itof.d $rDSF,$rA"
(+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
(set DF rDDF (float DF (get-rounding-mode) rA))
()
)
(dni lf-ftoi-s
"lf.ftoi.s reg/reg"
((MACH ORFPX-MACHS))
"lf.ftoi.s $rD,$rASF"
(+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S)
(set WI rD (ext WI (fix SI (get-rounding-mode) rASF)))
()
)
(dni lf-ftoi-d
"lf.ftoi.d reg/reg"
((MACH ORFPX64-MACHS))
"lf.ftoi.d $rD,$rADF"
(+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
(set DI rD (fix DI (get-rounding-mode) rADF))
()
)
(define-pmacro (float-setflag-insn mnemonic)
(begin
(dni (.sym lf- mnemonic -s)
(.str "lf.sf" mnemonic ".s reg/reg")
((MACH ORFPX-MACHS))
(.str "lf.sf" mnemonic ".s $rASF,$rBSF")
(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
(set BI sys-sr-f (mnemonic SF rASF rBSF))
()
)
(dni (.sym lf- mnemonic -d)
(.str "lf.sf" mnemonic ".d reg/reg")
((MACH ORFPX64-MACHS))
(.str "lf.sf" mnemonic ".d $rASF,$rBSF")
(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
(set BI sys-sr-f (mnemonic DF rADF rBDF))
()
)
)
)
(float-setflag-insn eq)
(float-setflag-insn ne)
(float-setflag-insn ge)
(float-setflag-insn gt)
(float-setflag-insn lt)
(float-setflag-insn le)
(dni lf-madd-s
"lf.madd.s reg/reg/reg"
((MACH ORFPX-MACHS))
"lf.madd.s $rDSF,$rASF,$rBSF"
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S)
(set SF rDSF (add SF (mul SF rASF rBSF) rDSF))
()
)
(dni lf-madd-d
"lf.madd.d reg/reg/reg"
((MACH ORFPX64-MACHS))
"lf.madd.d $rDDF,$rADF,$rBDF"
(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
(set DF rDDF (add DF (mul DF rADF rBDF) rDDF))
()
)
(define-pmacro (float-cust-insn cust-num)
(begin
(dni (.sym "lf-cust" cust-num "-s")
(.str "lf.cust" cust-num ".s")
((MACH ORFPX-MACHS))
(.str "lf.cust" cust-num ".s $rASF,$rBSF")
(+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S"))
(nop)
()
)
(dni (.sym "lf-cust" cust-num "-d")
(.str "lf.cust" cust-num ".d")
((MACH ORFPX64-MACHS))
(.str "lf.cust" cust-num ".d")
(+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
(nop)
()
)
)
)
(float-cust-insn "1")

4
elfcpp/ChangeLog
View File

@ -1,3 +1,7 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* elfcpp.h: Remove openrisc and or32 support.
2014-04-15 Sasa Stankovic <Sasa.Stankovic@imgtec.com>
* mips.h (R _MIPS16_TLS_GD, R_MIPS16_TLS_LDM, R_MIPS16_TLS_DTPREL_HI16,

4
elfcpp/elfcpp.h
View File

@ -246,7 +246,7 @@ enum EM
EM_MN10300 = 89,
EM_MN10200 = 90,
EM_PJ = 91,
EM_OPENRISC = 92,
EM_OR1K = 92,
EM_ARC_A5 = 93,
EM_XTENSA = 94,
EM_VIDEOCORE = 95,
@ -288,7 +288,7 @@ enum EM
// Old AVR objects used 0x1057 (EM_AVR is correct).
// Old MSP430 objects used 0x1059 (EM_MSP430 is correct).
// Old FR30 objects used 0x3330 (EM_FR30 is correct).
// Old OpenRISC objects used 0x3426 and 0x8472 (EM_OPENRISC is correct).
// Old OpenRISC objects used 0x3426 and 0x8472 (EM_OR1K is correct).
// Old D10V objects used 0x7650 (EM_D10V is correct).
// Old D30V objects used 0x7676 (EM_D30V is correct).
// Old IP2X objects used 0x8217 (EM_IP2K is correct).

16
gas/ChangeLog
View File

@ -1,3 +1,19 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* Makefile.am: Remove openrisc and or32 support. Add support for or1k.
* configure.in: Likewise.
* configure.tgt: Likewise.
* doc/as.texinfo: Likewise.
* config/obj-coff.h: Likewise.
* config/tc-or1k.c: New file.
* config/tc-or1k.h: New file.
* config/tc-openrisc.c: Delete.
* config/tc-openrisc.h: Delete.
* config/tc-or32.c: Delete.
* config/tc-or32.h: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
2014-04-16 Alan Modra <amodra@gmail.com>
* config/tc-tilegx.h (TC_CONS_FIX_NEW): Add RELOC arg.

6
gas/Makefile.am
View File

@ -167,8 +167,7 @@ TARGET_CPU_CFILES = \
config/tc-nds32.c \
config/tc-nios2.c \
config/tc-ns32k.c \
config/tc-openrisc.c \
config/tc-or32.c \
config/tc-or1k.c \
config/tc-pdp11.c \
config/tc-pj.c \
config/tc-ppc.c \
@ -239,8 +238,7 @@ TARGET_CPU_HFILES = \
config/tc-nds32.h \
config/tc-nios2.h \
config/tc-ns32k.h \
config/tc-openrisc.h \
config/tc-or32.h \
config/tc-or1k.h \
config/tc-pdp11.h \
config/tc-pj.h \
config/tc-ppc.h \

43
gas/Makefile.in
View File

@ -436,8 +436,7 @@ TARGET_CPU_CFILES = \
config/tc-nds32.c \
config/tc-nios2.c \
config/tc-ns32k.c \
config/tc-openrisc.c \
config/tc-or32.c \
config/tc-or1k.c \
config/tc-pdp11.c \
config/tc-pj.c \
config/tc-ppc.c \
@ -508,8 +507,7 @@ TARGET_CPU_HFILES = \
config/tc-nds32.h \
config/tc-nios2.h \
config/tc-ns32k.h \
config/tc-openrisc.h \
config/tc-or32.h \
config/tc-or1k.h \
config/tc-pdp11.h \
config/tc-pj.h \
config/tc-ppc.h \
@ -859,8 +857,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-nds32.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-nios2.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ns32k.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-openrisc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-or32.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-or1k.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@
@ -1513,33 +1510,19 @@ tc-ns32k.obj: config/tc-ns32k.c
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ns32k.obj `if test -f 'config/tc-ns32k.c'; then $(CYGPATH_W) 'config/tc-ns32k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ns32k.c'; fi`
tc-openrisc.o: config/tc-openrisc.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-openrisc.o -MD -MP -MF $(DEPDIR)/tc-openrisc.Tpo -c -o tc-openrisc.o `test -f 'config/tc-openrisc.c' || echo '$(srcdir)/'`config/tc-openrisc.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-openrisc.Tpo $(DEPDIR)/tc-openrisc.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-openrisc.c' object='tc-openrisc.o' libtool=no @AMDEPBACKSLASH@
tc-or1k.o: config/tc-or1k.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or1k.o -MD -MP -MF $(DEPDIR)/tc-or1k.Tpo -c -o tc-or1k.o `test -f 'config/tc-or1k.c' || echo '$(srcdir)/'`config/tc-or1k.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or1k.Tpo $(DEPDIR)/tc-or1k.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or1k.c' object='tc-or1k.o' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-openrisc.o `test -f 'config/tc-openrisc.c' || echo '$(srcdir)/'`config/tc-openrisc.c
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or1k.o `test -f 'config/tc-or1k.c' || echo '$(srcdir)/'`config/tc-or1k.c
tc-openrisc.obj: config/tc-openrisc.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-openrisc.obj -MD -MP -MF $(DEPDIR)/tc-openrisc.Tpo -c -o tc-openrisc.obj `if test -f 'config/tc-openrisc.c'; then $(CYGPATH_W) 'config/tc-openrisc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-openrisc.c'; fi`
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-openrisc.Tpo $(DEPDIR)/tc-openrisc.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-openrisc.c' object='tc-openrisc.obj' libtool=no @AMDEPBACKSLASH@
tc-or1k.obj: config/tc-or1k.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or1k.obj -MD -MP -MF $(DEPDIR)/tc-or1k.Tpo -c -o tc-or1k.obj `if test -f 'config/tc-or1k.c'; then $(CYGPATH_W) 'config/tc-or1k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or1k.c'; fi`
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or1k.Tpo $(DEPDIR)/tc-or1k.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or1k.c' object='tc-or1k.obj' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-openrisc.obj `if test -f 'config/tc-openrisc.c'; then $(CYGPATH_W) 'config/tc-openrisc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-openrisc.c'; fi`
tc-or32.o: config/tc-or32.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or32.o -MD -MP -MF $(DEPDIR)/tc-or32.Tpo -c -o tc-or32.o `test -f 'config/tc-or32.c' || echo '$(srcdir)/'`config/tc-or32.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or32.Tpo $(DEPDIR)/tc-or32.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or32.c' object='tc-or32.o' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or32.o `test -f 'config/tc-or32.c' || echo '$(srcdir)/'`config/tc-or32.c
tc-or32.obj: config/tc-or32.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or32.obj -MD -MP -MF $(DEPDIR)/tc-or32.Tpo -c -o tc-or32.obj `if test -f 'config/tc-or32.c'; then $(CYGPATH_W) 'config/tc-or32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or32.c'; fi`
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or32.Tpo $(DEPDIR)/tc-or32.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or32.c' object='tc-or32.obj' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or32.obj `if test -f 'config/tc-or32.c'; then $(CYGPATH_W) 'config/tc-or32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or32.c'; fi`
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or1k.obj `if test -f 'config/tc-or1k.c'; then $(CYGPATH_W) 'config/tc-or1k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or1k.c'; fi`
tc-pdp11.o: config/tc-pdp11.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-pdp11.o -MD -MP -MF $(DEPDIR)/tc-pdp11.Tpo -c -o tc-pdp11.o `test -f 'config/tc-pdp11.c' || echo '$(srcdir)/'`config/tc-pdp11.c

2
gas/NEWS
View File

@ -1,5 +1,7 @@
-*- text -*-
* Replace support for openrisc and or32 with support for or1k.
* Enhanced the ARM port to accept the assembler output from the CodeComposer
Studio tool. Support is enabled via the new command line option -mccs.

5
gas/config/obj-coff.h
View File

@ -75,11 +75,6 @@
#endif
#endif
#ifdef TC_OR32
#include "coff/or32.h"
#define TARGET_FORMAT "coff-or32-big"
#endif
#ifdef TC_I960
#include "coff/i960.h"
#define TARGET_FORMAT "coff-Intel-little"

61
gas/config/tc-openrisc.h
View File

@ -1,61 +0,0 @@
/* tc-openrisc.h -- Header file for tc-openrisc.c.
Copyright (C) 2001-2014 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#define TC_OPENRISC
#define LISTING_HEADER "OpenRISC GAS "
/* The target BFD architecture. */
#define TARGET_ARCH bfd_arch_openrisc
extern unsigned long openrisc_machine;
#define TARGET_MACH (openrisc_machine)
#define TARGET_FORMAT "elf32-openrisc"
#define TARGET_BYTES_BIG_ENDIAN 1
extern const char openrisc_comment_chars [];
#define tc_comment_chars openrisc_comment_chars
/* Permit temporary numeric labels. */
#define LOCAL_LABELS_FB 1
#define DIFF_EXPR_OK 1 /* .-foo gets turned into PC relative relocs */
/* We don't need to handle .word strangely. */
#define WORKING_DOT_WORD
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
#define md_apply_fix gas_cgen_md_apply_fix
extern bfd_boolean openrisc_fix_adjustable (struct fix *);
#define tc_fix_adjustable(FIX) openrisc_fix_adjustable (FIX)
#define tc_gen_reloc gas_cgen_tc_gen_reloc
/* Call md_pcrel_from_section(), not md_pcrel_from(). */
extern long md_pcrel_from_section (struct fix *, segT);
#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
/* For 8 vs 16 vs 32 bit branch selection. */
extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table

268
gas/config/tc-openrisc.c → gas/config/tc-or1k.c
View File

@ -1,6 +1,6 @@
/* tc-openrisc.c -- Assembler for the OpenRISC family.
Copyright (C) 2001-2014 Free Software Foundation, Inc.
Contributed by Johan Rydberg, jrydberg@opencores.org
/* tc-or1k.c -- Assembler for the OpenRISC family.
Copyright 2001-2014 Free Software Foundation.
Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
This file is part of GAS, the GNU Assembler.
@ -15,26 +15,25 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
along with this program; if not, see <http://www.gnu.org/licenses/> */
#include "as.h"
#include "safe-ctype.h"
#include "subsegs.h"
#include "symcat.h"
#include "opcodes/openrisc-desc.h"
#include "opcodes/openrisc-opc.h"
#include "opcodes/or1k-desc.h"
#include "opcodes/or1k-opc.h"
#include "cgen.h"
#include "elf/or1k.h"
#include "dw2gencfi.h"
/* Structure to hold all of the different components describing
an individual instruction. */
typedef struct openrisc_insn openrisc_insn;
struct openrisc_insn
typedef struct
{
const CGEN_INSN * insn;
const CGEN_INSN * orig_insn;
CGEN_FIELDS fields;
const CGEN_INSN * insn;
const CGEN_INSN * orig_insn;
CGEN_FIELDS fields;
#if CGEN_INT_INSN_P
CGEN_INSN_INT buffer [1];
#define INSN_VALUE(buf) (*(buf))
@ -42,13 +41,13 @@ struct openrisc_insn
unsigned char buffer [CGEN_MAX_INSN_SIZE];
#define INSN_VALUE(buf) (buf)
#endif
char * addr;
fragS * frag;
char * addr;
fragS * frag;
int num_fixups;
fixS * fixups [GAS_CGEN_MAX_FIXUPS];
int indices [MAX_OPERAND_INSTANCES];
};
}
or1k_insn;
const char comment_chars[] = "#";
const char line_comment_chars[] = "#";
@ -56,9 +55,8 @@ const char line_separator_chars[] = ";";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
#define OPENRISC_SHORTOPTS "m:"
const char * md_shortopts = OPENRISC_SHORTOPTS;
#define OR1K_SHORTOPTS "m:"
const char * md_shortopts = OR1K_SHORTOPTS;
struct option md_longopts[] =
{
@ -66,7 +64,7 @@ struct option md_longopts[] =
};
size_t md_longopts_size = sizeof (md_longopts);
unsigned long openrisc_machine = 0; /* default */
unsigned long or1k_machine = 0; /* default */
int
md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED)
@ -85,30 +83,38 @@ ignore_pseudo (int val ATTRIBUTE_UNUSED)
discard_rest_of_line ();
}
const char openrisc_comment_chars [] = ";#";
static bfd_boolean nodelay = FALSE;
static void
s_nodelay (int val ATTRIBUTE_UNUSED)
{
nodelay = TRUE;
}
const char or1k_comment_chars [] = ";#";
/* The target specific pseudo-ops which we support. */
const pseudo_typeS md_pseudo_table[] =
{
{ "align", s_align_bytes, 0 },
{ "word", cons, 4 },
{ "proc", ignore_pseudo, 0 },
{ "endproc", ignore_pseudo, 0 },
{ NULL, NULL, 0 }
{ "nodelay", s_nodelay, 0 },
{ NULL, NULL, 0 }
};
void
md_begin (void)
{
/* Initialize the `cgen' interface. */
/* Set the machine number and endian. */
gas_cgen_cpu_desc = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
gas_cgen_cpu_desc = or1k_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
CGEN_CPU_OPEN_ENDIAN,
CGEN_ENDIAN_BIG,
CGEN_CPU_OPEN_END);
openrisc_cgen_init_asm (gas_cgen_cpu_desc);
or1k_cgen_init_asm (gas_cgen_cpu_desc);
/* This is a callback from cgen to gas to parse operands. */
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
@ -118,13 +124,13 @@ void
md_assemble (char * str)
{
static int last_insn_had_delay_slot = 0;
openrisc_insn insn;
or1k_insn insn;
char * errmsg;
/* Initialize GAS's cgen interface for a new instruction. */
gas_cgen_init_parse ();
insn.insn = openrisc_cgen_assemble_insn
insn.insn = or1k_cgen_assemble_insn
(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
if (!insn.insn)
@ -135,10 +141,11 @@ md_assemble (char * str)
/* Doesn't really matter what we pass for RELAX_P here. */
gas_cgen_finish_insn (insn.insn, insn.buffer,
CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
last_insn_had_delay_slot
= CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
(void) last_insn_had_delay_slot;
}
@ -168,10 +175,8 @@ md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
return 0;
}
/* Interface to relax_segment. */
/* FIXME: Look through this. */
/* Interface to relax_segment. */
const relax_typeS md_relax_table[] =
{
@ -185,71 +190,14 @@ const relax_typeS md_relax_table[] =
each list. */
{1, 1, 0, 0},
/* The displacement used by GAS is from the end of the 2 byte insn,
so we subtract 2 from the following. */
/* 16 bit insn, 8 bit disp -> 10 bit range.
This doesn't handle a branch in the right slot at the border:
the "& -4" isn't taken into account. It's not important enough to
complicate things over it, so we subtract an extra 2 (or + 2 in -ve
case). */
{511 - 2 - 2, -512 - 2 + 2, 0, 2 },
/* 32 bit insn, 24 bit disp -> 26 bit range. */
{0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
/* Same thing, but with leading nop for alignment. */
{0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
/* The displacement used by GAS is from the end of the 4 byte insn,
so we subtract 4 from the following. */
{(((1 << 25) - 1) << 2) - 4, -(1 << 25) - 4, 0, 0},
};
/* Return an initial guess of the length by which a fragment must grow to
hold a branch to reach its destination.
Also updates fr_type/fr_subtype as necessary.
Called just before doing relaxation.
Any symbol that is now undefined will not become defined.
The guess for fr_var is ACTUALLY the growth beyond fr_fix.
Whatever we do to grow fr_fix or fr_var contributes to our returned value.
Although it may not be explicit in the frag, pretend fr_var starts with a
0 value. */
int
md_estimate_size_before_relax (fragS * fragP, segT segment)
md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED)
{
/* The only thing we have to handle here are symbols outside of the
current segment. They may be undefined or in a different segment in
which case linker scripts may place them anywhere.
However, we can't finish the fragment here and emit the reloc as insn
alignment requirements may move the insn about. */
if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
{
/* The symbol is undefined in this segment.
Change the relaxation subtype to the max allowable and leave
all further handling to md_convert_frag. */
fragP->fr_subtype = 2;
{
const CGEN_INSN * insn;
int i;
/* Update the recorded insn.
Fortunately we don't have to look very far.
FIXME: Change this to record in the instruction the next higher
relaxable insn to use. */
for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
{
if ((strcmp (CGEN_INSN_MNEMONIC (insn),
CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
== 0)
&& CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED))
break;
}
if (i == 4)
abort ();
fragP->fr_cgen.insn = insn;
return 2;
}
}
return md_relax_table[fragP->fr_subtype].rlx_length;
}
@ -262,13 +210,13 @@ md_estimate_size_before_relax (fragS * fragP, segT segment)
void
md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
segT sec ATTRIBUTE_UNUSED,
fragS * fragP ATTRIBUTE_UNUSED)
segT sec ATTRIBUTE_UNUSED,
fragS * fragP ATTRIBUTE_UNUSED)
{
/* FIXME */
}
/* Functions concerning relocs. */
/* The location from which a PC relative jump should be calculated,
@ -279,12 +227,16 @@ md_pcrel_from_section (fixS * fixP, segT sec)
{
if (fixP->fx_addsy != (symbolS *) NULL
&& (! S_IS_DEFINED (fixP->fx_addsy)
|| S_GET_SEGMENT (fixP->fx_addsy) != sec))
/* The symbol is undefined (or is defined but not in this section).
Let the linker figure it out. */
return 0;
|| (S_GET_SEGMENT (fixP->fx_addsy) != sec)
|| S_IS_EXTERNAL (fixP->fx_addsy)
|| S_IS_WEAK (fixP->fx_addsy)))
{
/* The symbol is undefined (or is defined but not in this section).
Let the linker figure it out. */
return 0;
}
return (fixP->fx_frag->fr_address + fixP->fx_where) & ~1;
return fixP->fx_frag->fr_address + fixP->fx_where;
}
@ -294,40 +246,23 @@ md_pcrel_from_section (fixS * fixP, segT sec)
bfd_reloc_code_real_type
md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED,
const CGEN_OPERAND * operand,
fixS * fixP)
const CGEN_OPERAND * operand,
fixS * fixP)
{
bfd_reloc_code_real_type type;
if (fixP->fx_cgen.opinfo)
return fixP->fx_cgen.opinfo;
switch (operand->type)
{
case OPENRISC_OPERAND_ABS_26:
fixP->fx_pcrel = 0;
type = BFD_RELOC_OPENRISC_ABS_26;
goto emit;
case OPENRISC_OPERAND_DISP_26:
case OR1K_OPERAND_DISP26:
fixP->fx_pcrel = 1;
type = BFD_RELOC_OPENRISC_REL_26;
goto emit;
return BFD_RELOC_OR1K_REL_26;
case OPENRISC_OPERAND_HI16:
type = BFD_RELOC_HI16;
goto emit;
case OPENRISC_OPERAND_LO16:
type = BFD_RELOC_LO16;
goto emit;
emit:
return type;
default : /* avoid -Wall warning */
break;
default: /* avoid -Wall warning */
return BFD_RELOC_NONE;
}
return BFD_RELOC_NONE;
}
/* Write a value out to the object file, using the appropriate endianness. */
void
@ -338,10 +273,9 @@ md_number_to_chars (char * buf, valueT val, int n)
/* Turn a string in input_line_pointer into a floating point constant of type
type, and store the appropriate bytes in *litP. The number of LITTLENUMS
emitted is stored in *sizeP . An error message is returned, or NULL on OK.
*/
emitted is stored in *sizeP . An error message is returned, or NULL on OK. */
/* Equal to MAX_PRECISION in atof-ieee.c */
/* Equal to MAX_PRECISION in atof-ieee.c. */
#define MAX_LITTLENUMS 6
char *
@ -351,12 +285,78 @@ md_atof (int type, char * litP, int * sizeP)
}
bfd_boolean
openrisc_fix_adjustable (fixS * fixP)
or1k_fix_adjustable (fixS * fixP)
{
/* We need the symbol name for the VTABLE entries. */
if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
return FALSE;
return 1;
return TRUE;
}
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
arelent *
tc_gen_reloc (asection *sec, fixS *fx)
{
bfd_reloc_code_real_type code = fx->fx_r_type;
if (fx->fx_addsy != NULL
&& strcmp (S_GET_NAME (fx->fx_addsy), GOT_NAME) == 0
&& (code == BFD_RELOC_OR1K_GOTPC_HI16
|| code == BFD_RELOC_OR1K_GOTPC_LO16))
{
arelent * reloc;
reloc = xmalloc (sizeof (* reloc));
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy);
reloc->address = fx->fx_frag->fr_address + fx->fx_where;
reloc->howto = bfd_reloc_type_lookup (stdoutput, fx->fx_r_type);
reloc->addend = fx->fx_offset;
return reloc;
}
return gas_cgen_tc_gen_reloc (sec, fx);
}
void
or1k_apply_fix (struct fix *f, valueT *t, segT s)
{
gas_cgen_md_apply_fix (f, t, s);
switch (f->fx_r_type)
{
case BFD_RELOC_OR1K_TLS_GD_HI16:
case BFD_RELOC_OR1K_TLS_GD_LO16:
case BFD_RELOC_OR1K_TLS_LDM_HI16:
case BFD_RELOC_OR1K_TLS_LDM_LO16:
case BFD_RELOC_OR1K_TLS_LDO_HI16:
case BFD_RELOC_OR1K_TLS_LDO_LO16:
case BFD_RELOC_OR1K_TLS_IE_HI16:
case BFD_RELOC_OR1K_TLS_IE_LO16:
case BFD_RELOC_OR1K_TLS_LE_HI16:
case BFD_RELOC_OR1K_TLS_LE_LO16:
S_SET_THREAD_LOCAL (f->fx_addsy);
break;
default:
break;
}
}
void
or1k_elf_final_processing (void)
{
if (nodelay)
elf_elfheader (stdoutput)->e_flags |= EF_OR1K_NODELAY;
}
/* Standard calling conventions leave the CFA at SP on entry. */
void
or1k_cfi_frame_initial_instructions (void)
{
cfi_add_CFA_def_cfa_register (1);
}

79
gas/config/tc-or1k.h Normal file
View File

@ -0,0 +1,79 @@
/* tc-or1k.h -- Header file for tc-or1k.c.
Copyright 2001-2014 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/> */
#define TC_OR1K
#define LISTING_HEADER "Or1k GAS "
/* The target BFD architecture. */
#define TARGET_ARCH bfd_arch_or1k
extern unsigned long or1k_machine;
#define TARGET_MACH (or1k_machine)
#define TARGET_FORMAT "elf32-or1k"
#define TARGET_BYTES_BIG_ENDIAN 1
extern const char or1k_comment_chars [];
#define tc_comment_chars or1k_comment_chars
/* Permit temporary numeric labels. */
#define LOCAL_LABELS_FB 1
#define DIFF_EXPR_OK 1 /* .-foo gets turned into PC relative relocs. */
/* We don't need to handle .word strangely. */
#define WORKING_DOT_WORD
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
#define md_apply_fix or1k_apply_fix
extern void or1k_apply_fix (struct fix *, valueT *, segT);
extern bfd_boolean or1k_fix_adjustable (struct fix *);
#define tc_fix_adjustable(FIX) or1k_fix_adjustable (FIX)
/* Call md_pcrel_from_section(), not md_pcrel_from(). */
extern long md_pcrel_from_section (struct fix *, segT);
#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
/* For 8 vs 16 vs 32 bit branch selection. */
extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table
#define GAS_CGEN_PCREL_R_TYPE(r_type) gas_cgen_pcrel_r_type(r_type)
#define elf_tc_final_processing or1k_elf_final_processing
void or1k_elf_final_processing (void);
/* Enable cfi directives. */
#define TARGET_USE_CFIPOP 1
/* Stack grows to lower addresses and wants 4 byte boundary. */
#define DWARF2_CIE_DATA_ALIGNMENT -4
/* Define the column that represents the PC. */
#define DWARF2_DEFAULT_RETURN_COLUMN 9
/* or1k instructions are 4 bytes long. */
#define DWARF2_LINE_MIN_INSN_LENGTH 4
#define tc_cfi_frame_initial_instructions \
or1k_cfi_frame_initial_instructions
extern void or1k_cfi_frame_initial_instructions (void);

966
gas/config/tc-or32.c
View File

@ -1,966 +0,0 @@
/* Assembly backend for the OpenRISC 1000.
Copyright (C) 2002-2014 Free Software Foundation, Inc.
Contributed by Damjan Lampret <lampret@opencores.org>.
Modified bu Johan Rydberg, <johan.rydberg@netinsight.se>.
Based upon a29k port.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
/* tc-a29k.c used as a template. */
#include "as.h"
#include "safe-ctype.h"
#include "opcode/or32.h"
#include "elf/or32.h"
#define DEBUG 0
#ifndef REGISTER_PREFIX
#define REGISTER_PREFIX '%'
#endif
/* Make it easier to clone this machine desc into another one. */
#define machine_opcode or32_opcode
#define machine_opcodes or32_opcodes
#define machine_ip or32_ip
#define machine_it or32_it
/* Handle of the OPCODE hash table. */
static struct hash_control *op_hash = NULL;
struct machine_it
{
char * error;
unsigned long opcode;
struct nlist * nlistp;
expressionS exp;
int pcrel;
int reloc_offset; /* Offset of reloc within insn. */
int reloc;
}
the_insn;
const pseudo_typeS md_pseudo_table[] =
{
{"align", s_align_bytes, 4 },
{"space", s_space, 0 },
{"cputype", s_ignore, 0 },
{"reg", s_lsym, 0 }, /* Register equate, same as equ. */
{"sect", s_ignore, 0 }, /* Creation of coff sections. */
{"proc", s_ignore, 0 }, /* Start of a function. */
{"endproc", s_ignore, 0 }, /* Function end. */
{"word", cons, 4 },
{NULL, 0, 0 },
};
int md_short_jump_size = 4;
int md_long_jump_size = 4;
/* This array holds the chars that always start a comment.
If the pre-processor is disabled, these aren't very useful. */
const char comment_chars[] = "#";
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
.line and .file directives will appear in the pre-processed output. */
/* Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
#NO_APP at the beginning of its output. */
/* Also note that comments like this one will always work. */
const char line_comment_chars[] = "#";
/* We needed an unused char for line separation to work around the
lack of macros, using sed and such. */
const char line_separator_chars[] = ";";
/* Chars that can be used to separate mant from exp in floating point nums. */
const char EXP_CHARS[] = "eE";
/* Chars that mean this number is a floating point constant.
As in 0f12.456
or 0d1.2345e12. */
const char FLT_CHARS[] = "rRsSfFdDxXpP";
/* "l.jalr r9" precalculated opcode. */
static unsigned long jalr_r9_opcode;
static void machine_ip (char *);
/* Set bits in machine opcode according to insn->encoding
description and passed operand. */
static void
encode (const struct machine_opcode *insn,
unsigned long *opcode,
signed long param_val,
char param_ch)
{
int opc_pos = 0;
int param_pos = 0;
char *enc;
#if DEBUG
printf (" encode: opcode=%.8lx param_val=%.8lx abs=%.8lx param_ch=%c\n",
*opcode, param_val, abs (param_val), param_ch);
#endif
for (enc = insn->encoding; *enc != '\0'; enc++)
if (*enc == param_ch)
{
if (enc - 2 >= insn->encoding && (*(enc - 2) == '0') && (*(enc - 1) == 'x'))
continue;
else
param_pos ++;
}
opc_pos = 32;
for (enc = insn->encoding; *enc != '\0';)
{
if ((*enc == '0') && (*(enc + 1) == 'x'))
{
int tmp = strtol (enc, NULL, 16);
opc_pos -= 4;
*opcode |= tmp << opc_pos;
enc += 3;
}
else if ((*enc == '0') || (*enc == '-'))
{
opc_pos--;
enc++;
}
else if (*enc == '1')
{
opc_pos--;
*opcode |= 1 << opc_pos;
enc++;
}
else if (*enc == param_ch)
{
opc_pos--;
param_pos--;
*opcode |= ((param_val >> param_pos) & 0x1) << opc_pos;
enc++;
}
else if (ISALPHA (*enc))
{
opc_pos--;
enc++;
}
else
enc++;
}
#if DEBUG
printf (" opcode=%.8lx\n", *opcode);
#endif
}
/* This function is called once, at assembler startup time. It should
set up all the tables, etc., that the MD part of the assembler will
need. */
void
md_begin (void)
{
const char *retval = NULL;
int lose = 0;
int skipnext = 0;
unsigned int i;
/* Hash up all the opcodes for fast use later. */
op_hash = hash_new ();
for (i = 0; i < or32_num_opcodes; i++)
{
const char *name = machine_opcodes[i].name;
if (skipnext)
{
skipnext = 0;
continue;
}
retval = hash_insert (op_hash, name, (void *) &machine_opcodes[i]);
if (retval != NULL)
{
fprintf (stderr, "internal error: can't hash `%s': %s\n",
machine_opcodes[i].name, retval);
lose = 1;
}
}
if (lose)
as_fatal (_("Broken assembler. No assembly attempted."));
encode (&machine_opcodes[insn_index ("l.jalr")], &jalr_r9_opcode, 9, 'B');
}
/* Returns non zero if instruction is to be used. */
static int
check_invalid_opcode (unsigned long opcode)
{
return opcode == jalr_r9_opcode;
}
/* Assemble a single instruction. Its label has already been handled
by the generic front end. We just parse opcode and operands, and
produce the bytes of data and relocation. */
void
md_assemble (char *str)
{
char *toP;
#if DEBUG
printf ("NEW INSTRUCTION\n");
#endif
know (str);
machine_ip (str);
toP = frag_more (4);
/* Put out the opcode. */
md_number_to_chars (toP, the_insn.opcode, 4);
/* Put out the symbol-dependent stuff. */
if (the_insn.reloc != BFD_RELOC_NONE)
{
fix_new_exp (frag_now,
(toP - frag_now->fr_literal + the_insn.reloc_offset),
4, /* size */
&the_insn.exp,
the_insn.pcrel,
the_insn.reloc);
}
}
/* This is true of the we have issued a "lo(" or "hi"(. */
static int waiting_for_shift = 0;
static int mask_or_shift = 0;
static char *
parse_operand (char *s, expressionS *operandp, int opt)
{
char *save = input_line_pointer;
char *new_pointer;
#if DEBUG
printf (" PROCESS NEW OPERAND(%s) == %c (%d)\n", s, opt ? opt : '!', opt);
#endif
input_line_pointer = s;
if (strncasecmp (s, "HI(", 3) == 0)
{
waiting_for_shift = 1;
mask_or_shift = BFD_RELOC_HI16;
input_line_pointer += 3;
}
else if (strncasecmp (s, "LO(", 3) == 0)
{
mask_or_shift = BFD_RELOC_LO16;
input_line_pointer += 3;
}
else
mask_or_shift = 0;
if ((*s == '(') && (*(s+1) == 'r'))
s++;
if ((*s == 'r') && ISDIGIT (*(s + 1)))
{
operandp->X_add_number = strtol (s + 1, NULL, 10);
operandp->X_op = O_register;
for (; (*s != ',') && (*s != '\0');)
s++;
input_line_pointer = save;
return s;
}
expression (operandp);
if (operandp->X_op == O_absent)
{
if (! opt)
as_bad (_("missing operand"));
else
{
operandp->X_add_number = 0;
operandp->X_op = O_constant;
}
}
new_pointer = input_line_pointer;
input_line_pointer = save;
#if DEBUG
printf (" %s=parse_operand(%s): operandp->X_op = %u\n", new_pointer, s,
operandp->X_op);
#endif
return new_pointer;
}
/* Instruction parsing. Takes a string containing the opcode.
Operands are at input_line_pointer. Output is in the_insn.
Warnings or errors are generated. */
static void
machine_ip (char *str)
{
char *s;
const char *args;
const struct machine_opcode *insn;
unsigned long opcode;
expressionS the_operand;
expressionS *operand = &the_operand;
unsigned int regno;
int reloc = BFD_RELOC_NONE;
#if DEBUG
printf ("machine_ip(%s)\n", str);
#endif
s = str;
for (; ISALNUM (*s) || *s == '.'; ++s)
if (ISUPPER (*s))
*s = TOLOWER (*s);
switch (*s)
{
case '\0':
break;
case ' ': /* FIXME-SOMEDAY more whitespace. */
*s++ = '\0';
break;
default:
as_bad (_("unknown opcode1: `%s'"), str);
return;
}
if ((insn = (struct machine_opcode *) hash_find (op_hash, str)) == NULL)
{
as_bad (_("unknown opcode2 `%s'."), str);
return;
}
opcode = 0;
memset (&the_insn, '\0', sizeof (the_insn));
the_insn.reloc = BFD_RELOC_NONE;
reloc = BFD_RELOC_NONE;
/* Build the opcode, checking as we go to make sure that the
operands match.
If an operand matches, we modify the_insn or opcode appropriately,
and do a "continue". If an operand fails to match, we "break". */
if (insn->args[0] != '\0')
/* Prime the pump. */
s = parse_operand (s, operand, insn->args[0] == 'I');
for (args = insn->args;; ++args)
{
#if DEBUG
printf (" args = %s\n", args);
#endif
switch (*args)
{
case '\0': /* End of args. */
/* We have have 0 args, do the bazoooka! */
if (args == insn->args)
encode (insn, &opcode, 0, 0);
if (*s == '\0')
{
/* We are truly done. */
the_insn.opcode = opcode;
if (check_invalid_opcode (opcode))
as_bad (_("instruction not allowed: %s"), str);
return;
}
as_bad (_("too many operands: %s"), s);
break;
case ',': /* Must match a comma. */
if (*s++ == ',')
{
reloc = BFD_RELOC_NONE;
/* Parse next operand. */
s = parse_operand (s, operand, args[1] == 'I');
#if DEBUG
printf (" ',' case: operand->X_add_number = %d, *args = %s, *s = %s\n",
operand->X_add_number, args, s);
#endif
continue;
}
break;
case '(': /* Must match a (. */
s = parse_operand (s, operand, args[1] == 'I');
continue;
case ')': /* Must match a ). */
continue;
case 'r': /* A general register. */
args++;
if (operand->X_op != O_register)
break; /* Only registers. */
know (operand->X_add_symbol == 0);
know (operand->X_op_symbol == 0);
regno = operand->X_add_number;
encode (insn, &opcode, regno, *args);
#if DEBUG
printf (" r: operand->X_op = %d\n", operand->X_op);
#endif
continue;
default:
/* if (! ISALPHA (*args))
break; */ /* Only immediate values. */
if (mask_or_shift)
{
#if DEBUG
printf ("mask_or_shift = %d\n", mask_or_shift);
#endif
reloc = mask_or_shift;
}
mask_or_shift = 0;
if (strncasecmp (args, "LO(", 3) == 0)
{
#if DEBUG
printf ("reloc_const\n");
#endif
reloc = BFD_RELOC_LO16;
}
else if (strncasecmp (args, "HI(", 3) == 0)
{
#if DEBUG
printf ("reloc_consth\n");
#endif
reloc = BFD_RELOC_HI16;
}
if (*s == '(')
operand->X_op = O_constant;
else if (*s == ')')
s += 1;
#if DEBUG
printf (" default case: operand->X_add_number = %d, *args = %s, *s = %s\n", operand->X_add_number, args, s);
#endif
if (operand->X_op == O_constant)
{
if (reloc == BFD_RELOC_NONE)
{
bfd_vma v, mask;
mask = 0x3ffffff;
v = abs (operand->X_add_number) & ~ mask;
if (v)
as_bad (_("call/jmp target out of range (1)"));
}
if (reloc == BFD_RELOC_HI16)
operand->X_add_number = ((operand->X_add_number >> 16) & 0xffff);
the_insn.pcrel = 0;
encode (insn, &opcode, operand->X_add_number, *args);
/* the_insn.reloc = BFD_RELOC_NONE; */
continue;
}
if (reloc == BFD_RELOC_NONE)
the_insn.reloc = BFD_RELOC_32_GOT_PCREL;
else
the_insn.reloc = reloc;
/* the_insn.reloc = insn->reloc; */
#if DEBUG
printf (" reloc sym=%d\n", the_insn.reloc);
printf (" BFD_RELOC_NONE=%d\n", BFD_RELOC_NONE);
#endif
the_insn.exp = *operand;
/* the_insn.reloc_offset = 1; */
the_insn.pcrel = 1; /* Assume PC-relative jump. */
/* FIXME-SOON, Do we figure out whether abs later, after
know sym val? */
if (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_HI16)
the_insn.pcrel = 0;
encode (insn, &opcode, operand->X_add_number, *args);
continue;
}
/* Types or values of args don't match. */
as_bad (_("invalid operands"));
return;
}
}
char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
}
/* Write out big-endian. */
void
md_number_to_chars (char *buf, valueT val, int n)
{
number_to_chars_bigendian (buf, val, n);
}
void
md_apply_fix (fixS * fixP, valueT * val, segT seg ATTRIBUTE_UNUSED)
{
char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
long t_val;
t_val = (long) *val;
#if DEBUG
printf ("md_apply_fix val:%x\n", t_val);
#endif
fixP->fx_addnumber = t_val; /* Remember value for emit_reloc. */
switch (fixP->fx_r_type)
{
case BFD_RELOC_32: /* XXXXXXXX pattern in a word. */
#if DEBUG
printf ("reloc_const: val=%x\n", t_val);
#endif
buf[0] = t_val >> 24;
buf[1] = t_val >> 16;
buf[2] = t_val >> 8;
buf[3] = t_val;
break;
case BFD_RELOC_16: /* XXXX0000 pattern in a word. */
#if DEBUG
printf ("reloc_const: val=%x\n", t_val);
#endif
buf[0] = t_val >> 8;
buf[1] = t_val;
break;
case BFD_RELOC_8: /* XX000000 pattern in a word. */
#if DEBUG
printf ("reloc_const: val=%x\n", t_val);
#endif
buf[0] = t_val;
break;
case BFD_RELOC_LO16: /* 0000XXXX pattern in a word. */
#if DEBUG
printf ("reloc_const: val=%x\n", t_val);
#endif
buf[2] = t_val >> 8; /* Holds bits 0000XXXX. */
buf[3] = t_val;
break;
case BFD_RELOC_HI16: /* 0000XXXX pattern in a word. */
#if DEBUG
printf ("reloc_consth: val=%x\n", t_val);
#endif
buf[2] = t_val >> 24; /* Holds bits XXXX0000. */
buf[3] = t_val >> 16;
break;
case BFD_RELOC_32_GOT_PCREL: /* 0000XXXX pattern in a word. */
if (!fixP->fx_done)
;
else if (fixP->fx_pcrel)
{
long v = t_val >> 28;
if (v != 0 && v != -1)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("call/jmp target out of range (2)"));
}
else
/* This case was supposed to be handled in machine_ip. */
abort ();
buf[0] |= (t_val >> 26) & 0x03; /* Holds bits 0FFFFFFC of address. */
buf[1] = t_val >> 18;
buf[2] = t_val >> 10;
buf[3] = t_val >> 2;
break;
case BFD_RELOC_VTABLE_INHERIT:
case BFD_RELOC_VTABLE_ENTRY:
fixP->fx_done = 0;
break;
case BFD_RELOC_NONE:
default:
as_bad (_("bad relocation type: 0x%02x"), fixP->fx_r_type);
break;
}
if (fixP->fx_addsy == (symbolS *) NULL)
fixP->fx_done = 1;
}
/* Should never be called for or32. */
void
md_create_short_jump (char * ptr ATTRIBUTE_UNUSED,
addressT from_addr ATTRIBUTE_UNUSED,
addressT to_addr ATTRIBUTE_UNUSED,
fragS * frag ATTRIBUTE_UNUSED,
symbolS * to_symbol ATTRIBUTE_UNUSED)
{
as_fatal ("or32_create_short_jmp\n");
}
/* Should never be called for or32. */
void
md_convert_frag (bfd * headers ATTRIBUTE_UNUSED,
segT seg ATTRIBUTE_UNUSED,
fragS * fragP ATTRIBUTE_UNUSED)
{
as_fatal ("or32_convert_frag\n");
}
/* Should never be called for or32. */
void
md_create_long_jump (char * ptr ATTRIBUTE_UNUSED,
addressT from_addr ATTRIBUTE_UNUSED,
addressT to_addr ATTRIBUTE_UNUSED,
fragS * frag ATTRIBUTE_UNUSED,
symbolS * to_symbol ATTRIBUTE_UNUSED)
{
as_fatal ("or32_create_long_jump\n");
}
/* Should never be called for or32. */
int
md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
segT segtype ATTRIBUTE_UNUSED)
{
as_fatal ("or32_estimate_size_before_relax\n");
return 0;
}
/* Translate internal representation of relocation info to target format.
On sparc/29k: first 4 bytes are normal unsigned long address, next three
bytes are index, most sig. byte first. Byte 7 is broken up with
bit 7 as external, bits 6 & 5 unused, and the lower
five bits as relocation type. Next 4 bytes are long addend. */
/* Thanx and a tip of the hat to Michael Bloom, mb@ttidca.tti.com. */
#ifdef OBJ_AOUT
void
tc_aout_fix_to_chars (char *where,
fixS *fixP,
relax_addressT segment_address_in_file)
{
long r_symbolnum;
#if DEBUG
printf ("tc_aout_fix_to_chars\n");
#endif
know (fixP->fx_r_type < BFD_RELOC_NONE);
know (fixP->fx_addsy != NULL);
md_number_to_chars
(where,
fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4);
r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
? S_GET_TYPE (fixP->fx_addsy)
: fixP->fx_addsy->sy_number);
where[4] = (r_symbolnum >> 16) & 0x0ff;
where[5] = (r_symbolnum >> 8) & 0x0ff;
where[6] = r_symbolnum & 0x0ff;
where[7] = (((!S_IS_DEFINED (fixP->fx_addsy)) << 7) & 0x80) | (0 & 0x60) | (fixP->fx_r_type & 0x1F);
/* Also easy. */
md_number_to_chars (&where[8], fixP->fx_addnumber, 4);
}
#endif /* OBJ_AOUT */
const char *md_shortopts = "";
struct option md_longopts[] =
{
{ NULL, no_argument, NULL, 0 }
};
size_t md_longopts_size = sizeof (md_longopts);
int
md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED)
{
return 0;
}
void
md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
{
}
/* This is called when a line is unrecognized. This is used to handle
definitions of or32 style local labels. */
int
or32_unrecognized_line (int c)
{
int lab;
char *s;
if (c != '$'
|| ! ISDIGIT ((unsigned char) input_line_pointer[0]))
return 0;
s = input_line_pointer;
lab = 0;
while (ISDIGIT ((unsigned char) *s))
{
lab = lab * 10 + *s - '0';
++s;
}
if (*s != ':')
/* Not a label definition. */
return 0;
if (dollar_label_defined (lab))
{
as_bad (_("label \"$%d\" redefined"), lab);
return 0;
}
define_dollar_label (lab);
colon (dollar_label_name (lab, 0));
input_line_pointer = s + 1;
return 1;
}
/* Default the values of symbols known that should be "predefined". We
don't bother to predefine them unless you actually use one, since there
are a lot of them. */
symbolS *
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
{
return NULL;
}
/* Parse an operand that is machine-specific. */
void
md_operand (expressionS *expressionP)
{
#if DEBUG
printf (" md_operand(input_line_pointer = %s)\n", input_line_pointer);
#endif
if (input_line_pointer[0] == REGISTER_PREFIX && input_line_pointer[1] == 'r')
{
/* We have a numeric register expression. No biggy. */
input_line_pointer += 2; /* Skip %r */
(void) expression (expressionP);
if (expressionP->X_op != O_constant
|| expressionP->X_add_number > 255)
as_bad (_("Invalid expression after %%%%\n"));
expressionP->X_op = O_register;
}
else if (input_line_pointer[0] == '&')
{
/* We are taking the 'address' of a register...this one is not
in the manual, but it *is* in traps/fpsymbol.h! What they
seem to want is the register number, as an absolute number. */
input_line_pointer++; /* Skip & */
(void) expression (expressionP);
if (expressionP->X_op != O_register)
as_bad (_("invalid register in & expression"));
else
expressionP->X_op = O_constant;
}
else if (input_line_pointer[0] == '$'
&& ISDIGIT ((unsigned char) input_line_pointer[1]))
{
long lab;
char *name;
symbolS *sym;
/* This is a local label. */
++input_line_pointer;
lab = (long) get_absolute_expression ();
if (dollar_label_defined (lab))
{
name = dollar_label_name (lab, 0);
sym = symbol_find (name);
}
else
{
name = dollar_label_name (lab, 1);
sym = symbol_find_or_make (name);
}
expressionP->X_op = O_symbol;
expressionP->X_add_symbol = sym;
expressionP->X_add_number = 0;
}
else if (input_line_pointer[0] == '$')
{
char *s;
char type;
int fieldnum, fieldlimit;
LITTLENUM_TYPE floatbuf[8];
/* $float(), $doubleN(), or $extendN() convert floating values
to integers. */
s = input_line_pointer;
++s;
fieldnum = 0;
if (strncmp (s, "double", sizeof "double" - 1) == 0)
{
s += sizeof "double" - 1;
type = 'd';
fieldlimit = 2;
}
else if (strncmp (s, "float", sizeof "float" - 1) == 0)
{
s += sizeof "float" - 1;
type = 'f';
fieldlimit = 1;
}
else if (strncmp (s, "extend", sizeof "extend" - 1) == 0)
{
s += sizeof "extend" - 1;
type = 'x';
fieldlimit = 4;
}
else
return;
if (ISDIGIT (*s))
{
fieldnum = *s - '0';
++s;
}
if (fieldnum >= fieldlimit)
return;
SKIP_WHITESPACE ();
if (*s != '(')
return;
++s;
SKIP_WHITESPACE ();
s = atof_ieee (s, type, floatbuf);
if (s == NULL)
return;
s = s;
SKIP_WHITESPACE ();
if (*s != ')')
return;
++s;
SKIP_WHITESPACE ();
input_line_pointer = s;
expressionP->X_op = O_constant;
expressionP->X_unsigned = 1;
expressionP->X_add_number = ((floatbuf[fieldnum * 2]
<< LITTLENUM_NUMBER_OF_BITS)
+ floatbuf[fieldnum * 2 + 1]);
}
}
/* Round up a section size to the appropriate boundary. */
valueT
md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size ATTRIBUTE_UNUSED)
{
return size; /* Byte alignment is fine. */
}
/* Exactly what point is a PC-relative offset relative TO?
On the 29000, they're relative to the address of the instruction,
which we have set up as the address of the fixup too. */
long
md_pcrel_from (fixS *fixP)
{
return fixP->fx_where + fixP->fx_frag->fr_address;
}
/* Generate a reloc for a fixup. */
arelent *
tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
{
arelent *reloc;
reloc = xmalloc (sizeof (arelent));
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
/* reloc->address = fixp->fx_frag->fr_address + fixp->fx_where + fixp->fx_addnumber;*/
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
if (reloc->howto == (reloc_howto_type *) NULL)
{
as_bad_where (fixp->fx_file, fixp->fx_line,
_("reloc %d not supported by object file format"),
(int) fixp->fx_r_type);
return NULL;
}
if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
reloc->address = fixp->fx_offset;
reloc->addend = fixp->fx_addnumber;
return reloc;
}

56
gas/config/tc-or32.h
View File

@ -1,56 +0,0 @@
/* tc-or32.h -- Assemble for the OpenRISC 1000.
Copyright (C) 2002-2014 Free Software Foundation, Inc.
Contributed by Damjan Lampret <lampret@opencores.org>.
Based upon a29k port.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#define TC_OR32
#define TARGET_BYTES_BIG_ENDIAN 1
#define LEX_DOLLAR 1
#ifdef OBJ_ELF
#define TARGET_FORMAT "elf32-or32"
#define TARGET_ARCH bfd_arch_or32
#endif
#ifdef OBJ_COFF
#define TARGET_FORMAT "coff-or32-big"
#define reloc_type int
#endif
#define tc_unrecognized_line(c) or32_unrecognized_line (c)
extern int or32_unrecognized_line (int);
#define tc_coff_symbol_emit_hook(a) ; /* Not used. */
#define COFF_MAGIC SIPFBOMAGIC
/* No shared lib support, so we don't need to ensure externally
visible symbols can be overridden. */
#define EXTERN_FORCE_RELOC 0
#ifdef OBJ_ELF
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
#endif
#define ZERO_BASED_SEGMENTS

4
gas/configure vendored
View File

@ -12150,7 +12150,7 @@ _ACEOF
fi
;;
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | openrisc)
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
using_cgen=yes
;;
@ -12426,6 +12426,8 @@ esac
cgen_cpu_prefix=""
if test $using_cgen = yes ; then
case ${target_cpu} in
or1knd)
cgen_cpu_prefix=or1k ;;
*) cgen_cpu_prefix=${target_cpu} ;;
esac

4
gas/configure.in
View File

@ -321,7 +321,7 @@ changequote([,])dnl
fi
;;
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | openrisc)
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
using_cgen=yes
;;
@ -568,6 +568,8 @@ esac
cgen_cpu_prefix=""
if test $using_cgen = yes ; then
case ${target_cpu} in
or1knd)
cgen_cpu_prefix=or1k ;;
*) cgen_cpu_prefix=${target_cpu} ;;
esac
AC_SUBST(cgen_cpu_prefix)

10
gas/configure.tgt
View File

@ -81,7 +81,7 @@ case ${cpu} in
mt) cpu_type=mt endian=big ;;
nds32be) cpu_type=nds32 endian=big ;;
nds32le) cpu_type=nds32 endian=little ;;
or32*) cpu_type=or32 endian=big ;;
or1k* | or1knd*) cpu_type=or1k endian=big ;;
pjl*) cpu_type=pj endian=little ;;
pj*) cpu_type=pj endian=big ;;
powerpc*le*) cpu_type=ppc endian=little ;;
@ -357,10 +357,8 @@ case ${generic_target} in
ns32k-pc532-lites*) fmt=aout em=nbsd532 ;;
ns32k-*-*n*bsd*) fmt=aout em=nbsd532 ;;
openrisc-*-*) fmt=elf ;;
or32-*-rtems*) fmt=elf ;;
or32-*-elf) fmt=elf ;;
or1k-*-elf | or1knd-*-elf) fmt=elf endian=big ;;
or1k-*-linux* | or1knd-*-linux*) fmt=elf em=linux endian=big ;;
pj*) fmt=elf ;;
@ -474,7 +472,7 @@ case ${generic_target} in
esac
case ${cpu_type} in
aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k)
aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | or1k | or1knd | pdp11 | ppc | sparc | z80 | z8k)
bfd_gas=yes
;;
esac

2
gas/doc/as.texinfo
View File

@ -4350,7 +4350,7 @@ required alignment; this can be useful if you want the alignment to be filled
with no-op instructions when appropriate.
The way the required alignment is specified varies from system to system.
For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32,
For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or1k,
s390, sparc, tic4x, tic80 and xtensa, the first expression is the
alignment request in bytes. For example @samp{.align 8} advances
the location counter until it is a multiple of 8. If the location counter

20
gas/testsuite/ChangeLog
View File

@ -1,3 +1,23 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* Makefile.am: Remove openrisc and or32 support. Add support for or1k.
* gas/all/gas.exp: Likewise.
* gas/elf/warn-2.s: Likewise.
* gas/lns/lns.exp: Likewise.
* gas/lns/lns-common-1-or1k.s: New file.
* gas/or1k/allinsn.d: New file.
* gas/or1k/allinsn.exp: New file.
* gas/or1k/allinsn.s: New file.
* gas/openrisc/addi.d: Delete.
* gas/openrisc/addi.s: Delete.
* gas/openrisc/allinsn.d: Delete.
* gas/openrisc/allinsn.exp: Delete.
* gas/openrisc/allinsn.s: Delete.
* gas/openrisc/lohi.d: Delete.
* gas/openrisc/lohi.s: Delete.
* gas/openrisc/store.d: Delete.
* gas/openrisc/store.s: Delete.
2014-04-10 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
* gas/avr/diffreloc_withrelax.d: New testcase.

2
gas/testsuite/gas/all/gas.exp
View File

@ -163,7 +163,7 @@ case $target_triplet in {
# These targets fail redef3 because section contents for the
# word referencing the .comm sym is not zero and/or its reloc
# has a non-zero addend. Relaxing the test would hide real
# failures such as or32-elf.
# failures.
setup_xfail "bfin-*-*" "i\[3-7\]86-*-*coff" \
"i\[3-7\]86-*-*pe" "i\[3-7\]86-*-go32*" \
"i\[3-7\]86-*-cygwin*" "i\[3-7\]86-*-mingw*" "x86_64-*-mingw*"

4
gas/testsuite/gas/elf/warn-2.s
View File

@ -1,7 +1,7 @@
;# { dg-do assemble }
;# { dg-options "--gdwarf2 --defsym nop_type=0" }
;# { dg-options "--gdwarf2 --defsym nop_type=1" { target ia64-*-* } }
;# { dg-options "--gdwarf2 --defsym nop_type=2" { target or32-*-* openrisc-*-* } }
;# { dg-options "--gdwarf2 --defsym nop_type=2" { target or1k*-*-* } }
;# { dg-options "--gdwarf2 --defsym nop_type=3" { target i370-*-* } }
.offset 40
@ -20,4 +20,4 @@
.endif
.endif
;# { dg-warning "Warning: dwarf line number information for .* ignored" "" { xfail i370-*-* mcore-*-* mn10200-*-* moxie-*-* openrisc-*-* or32-*-* v850*-*-* } 0 }
;# { dg-warning "Warning: dwarf line number information for .* ignored" "" { xfail i370-*-* mcore-*-* mn10200-*-* moxie-*-* v850*-*-* } 0 }

25
gas/testsuite/gas/lns/lns-common-1-or1k.s Normal file
View File

@ -0,0 +1,25 @@
.file 1 "foo.c"
.loc 1 1
l.nop
l.nop
.loc 1 2 3
l.nop
l.nop
.loc 1 3 prologue_end
l.nop
l.nop
.loc 1 4 0 epilogue_begin
l.nop
l.nop
.loc 1 5 isa 1 basic_block
l.nop
l.nop
.loc 1 6 is_stmt 0
l.nop
l.nop
.loc 1 7 is_stmt 1
l.nop
l.nop
.loc 1 7 discriminator 1
l.nop
l.nop

3
gas/testsuite/gas/lns/lns.exp
View File

@ -28,7 +28,6 @@ if {
![istarget i370-*-*]
&& ![istarget i960-*-*]
&& ![istarget mcore-*-*]
&& ![istarget or32-*-*]
&& ![istarget rx-*-*]
&& ![istarget s390*-*-*]
} {
@ -44,6 +43,8 @@ if {
run_dump_test "lns-big-delta"
} elseif { [istarget ia64*-*-*] } {
run_dump_test "lns-common-1" { { source "lns-common-1-ia64.s" } }
} elseif { [istarget or1k*-*-*] } {
run_dump_test "lns-common-1" { { source "lns-common-1-or1k.s" } }
} else {
run_dump_test "lns-common-1"
}

10
gas/testsuite/gas/openrisc/addi.d
View File

@ -1,10 +0,0 @@
#as:
#objdump: -dr
#name: addi
.*: +file format .*
Disassembly of section .text:
00000000 <l_addi>:
0: 94 22 ff ff l.addi r1,r2,-1

4
gas/testsuite/gas/openrisc/addi.s
View File

@ -1,4 +0,0 @@
.text
.global l_addi
l_addi:
l.addi r1, r2, -1

201
gas/testsuite/gas/openrisc/allinsn.d
View File

@ -1,201 +0,0 @@
#as:
#objdump: -dr
#name: allinsn
.*: +file format .*
Disassembly of section .text:
00000000 <l_j>:
0: 00 00 00 00 l.j 0 <l_j>
0: R_OPENRISC_INSN_ABS_26 .text
00000004 <l_jal>:
4: 04 00 00 00 l.jal 0 <l_j>
4: R_OPENRISC_INSN_ABS_26 .text
00000008 <l_jr>:
8: 14 00 00 00 l.jr r0
0000000c <l_jalr>:
c: 14 20 00 00 l.jalr r0
00000010 <l_bal>:
10: 0b ff ff fc l.bal 0 <l_j>
00000014 <l_bnf>:
14: 0f ff ff fb l.bnf 0 <l_j>
00000018 <l_bf>:
18: 13 ff ff fa l.bf 0 <l_j>
0000001c <l_brk>:
1c: 17 00 00 00 l.brk 0x0
00000020 <l_rfe>:
20: 14 40 00 00 l.rfe r0
00000024 <l_sys>:
24: 16 00 00 00 l.sys 0x0
00000028 <l_nop>:
28: 15 00 00 00 l.nop
0000002c <l_movhi>:
2c: 18 00 00 00 l.movhi r0,0
00000030 <l_mfsr>:
30: 1c 00 00 00 l.mfsr r0,r0
00000034 <l_mtsr>:
34: 40 00 00 00 l.mtsr r0,r0
00000038 <l_lw>:
38: 80 00 00 00 l.lw r0,0\(r0\)
0000003c <l_lbz>:
3c: 84 00 00 00 l.lbz r0,0\(r0\)
00000040 <l_lbs>:
40: 88 00 00 00 l.lbs r0,0\(r0\)
00000044 <l_lhz>:
44: 8c 00 00 00 l.lhz r0,0\(r0\)
00000048 <l_lhs>:
48: 90 00 00 00 l.lhs r0,0\(r0\)
0000004c <l_sw>:
4c: d4 00 00 00 l.sw 0\(r0\),r0
00000050 <l_sb>:
50: d8 00 00 00 l.sb 0\(r0\),r0
00000054 <l_sh>:
54: dc 00 00 00 l.sh 0\(r0\),r0
00000058 <l_sll>:
58: e0 00 00 08 l.sll r0,r0,r0
0000005c <l_slli>:
5c: b4 00 00 00 l.slli r0,r0,0x0
00000060 <l_srl>:
60: e0 00 00 28 l.srl r0,r0,r0
00000064 <l_srli>:
64: b4 00 00 20 l.srli r0,r0,0x0
00000068 <l_sra>:
68: e0 00 00 48 l.sra r0,r0,r0
0000006c <l_srai>:
6c: b4 00 00 40 l.srai r0,r0,0x0
00000070 <l_ror>:
70: e0 00 00 88 l.ror r0,r0,r0
00000074 <l_rori>:
74: b4 00 00 80 l.rori r0,r0,0x0
00000078 <l_add>:
78: e0 00 00 00 l.add r0,r0,r0
0000007c <l_addi>:
7c: 94 00 00 00 l.addi r0,r0,0
00000080 <l_sub>:
80: e0 00 00 02 l.sub r0,r0,r0
00000084 <l_subi>:
84: 9c 00 00 00 l.subi r0,r0,0
00000088 <l_and>:
88: e0 00 00 03 l.and r0,r0,r0
0000008c <l_andi>:
8c: a0 00 00 00 l.andi r0,r0,0
00000090 <l_or>:
90: e0 00 00 04 l.or r0,r0,r0
00000094 <l_ori>:
94: a4 00 00 00 l.ori r0,r0,0
00000098 <l_xor>:
98: e0 00 00 05 l.xor r0,r0,r0
0000009c <l_xori>:
9c: a8 00 00 00 l.xori r0,r0,0
000000a0 <l_mul>:
a0: e0 00 00 06 l.mul r0,r0,r0
000000a4 <l_muli>:
a4: ac 00 00 00 l.muli r0,r0,0
000000a8 <l_div>:
a8: e0 00 00 09 l.div r0,r0,r0
000000ac <l_divu>:
ac: e0 00 00 0a l.divu r0,r0,r0
000000b0 <l_sfgts>:
b0: e4 c0 00 00 l.sfgts r0,r0
000000b4 <l_sfgtu>:
b4: e4 40 00 00 l.sfgtu r0,r0
000000b8 <l_sfges>:
b8: e4 e0 00 00 l.sfges r0,r0
000000bc <l_sfgeu>:
bc: e4 60 00 00 l.sfgeu r0,r0
000000c0 <l_sflts>:
c0: e5 00 00 00 l.sflts r0,r0
000000c4 <l_sfltu>:
c4: e4 80 00 00 l.sfltu r0,r0
000000c8 <l_sfles>:
c8: e5 20 00 00 l.sfles r0,r0
000000cc <l_sfleu>:
cc: e4 a0 00 00 l.sfleu r0,r0
000000d0 <l_sfgtsi>:
d0: b8 c0 00 00 l.sfgtsi r0,0
000000d4 <l_sfgtui>:
d4: b8 40 00 00 l.sfgtui r0,0x0
000000d8 <l_sfgesi>:
d8: b8 e0 00 00 l.sfgesi r0,0
000000dc <l_sfgeui>:
dc: b8 60 00 00 l.sfgeui r0,0x0
000000e0 <l_sfltsi>:
e0: b9 00 00 00 l.sfltsi r0,0
000000e4 <l_sfltui>:
e4: b8 80 00 00 l.sfltui r0,0x0
000000e8 <l_sflesi>:
e8: b9 20 00 00 l.sflesi r0,0
000000ec <l_sfleui>:
ec: b8 a0 00 00 l.sfleui r0,0x0
000000f0 <l_sfeq>:
f0: e4 00 00 00 l.sfeq r0,r0
000000f4 <l_sfeqi>:
f4: b8 00 00 00 l.sfeqi r0,0
000000f8 <l_sfne>:
f8: e4 20 00 00 l.sfne r0,r0
000000fc <l_sfnei>:
fc: b8 20 00 00 l.sfnei r0,0

24
gas/testsuite/gas/openrisc/allinsn.exp
View File

@ -1,24 +0,0 @@
# Copyright (C) 2012-2014 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
# OpenRISC assembler testsuite.
if [istarget openrisc*-*-*] {
run_dump_test "allinsn"
run_dump_test "addi"
run_dump_test "lohi"
run_dump_test "store"
}

260
gas/testsuite/gas/openrisc/allinsn.s
View File

@ -1,260 +0,0 @@
.data
foodata: .word 42
.text
footext:
.text
.global l_j
l_j:
l.j footext
.text
.global l_jal
l_jal:
l.jal footext
.text
.global l_jr
l_jr:
l.jr r0
.text
.global l_jalr
l_jalr:
l.jalr r0
.text
.global l_bal
l_bal:
l.bal footext
.text
.global l_bnf
l_bnf:
l.bnf footext
.text
.global l_bf
l_bf:
l.bf footext
.text
.global l_brk
l_brk:
l.brk 0
.text
.global l_rfe
l_rfe:
l.rfe r0
.text
.global l_sys
l_sys:
l.sys 0
.text
.global l_nop
l_nop:
l.nop
.text
.global l_movhi
l_movhi:
l.movhi r0,0
.text
.global l_mfsr
l_mfsr:
l.mfsr r0,r0
.text
.global l_mtsr
l_mtsr:
l.mtsr r0,r0
.text
.global l_lw
l_lw:
l.lw r0,0(r0)
.text
.global l_lbz
l_lbz:
l.lbz r0,0(r0)
.text
.global l_lbs
l_lbs:
l.lbs r0,0(r0)
.text
.global l_lhz
l_lhz:
l.lhz r0,0(r0)
.text
.global l_lhs
l_lhs:
l.lhs r0,0(r0)
.text
.global l_sw
l_sw:
l.sw 0(r0),r0
.text
.global l_sb
l_sb:
l.sb 0(r0),r0
.text
.global l_sh
l_sh:
l.sh 0(r0),r0
.text
.global l_sll
l_sll:
l.sll r0,r0,r0
.text
.global l_slli
l_slli:
l.slli r0,r0,0
.text
.global l_srl
l_srl:
l.srl r0,r0,r0
.text
.global l_srli
l_srli:
l.srli r0,r0,0
.text
.global l_sra
l_sra:
l.sra r0,r0,r0
.text
.global l_srai
l_srai:
l.srai r0,r0,0
.text
.global l_ror
l_ror:
l.ror r0,r0,r0
.text
.global l_rori
l_rori:
l.rori r0,r0,0
.text
.global l_add
l_add:
l.add r0,r0,r0
.text
.global l_addi
l_addi:
l.addi r0,r0,0
.text
.global l_sub
l_sub:
l.sub r0,r0,r0
.text
.global l_subi
l_subi:
l.subi r0,r0,0
.text
.global l_and
l_and:
l.and r0,r0,r0
.text
.global l_andi
l_andi:
l.andi r0,r0,0
.text
.global l_or
l_or:
l.or r0,r0,r0
.text
.global l_ori
l_ori:
l.ori r0,r0,0
.text
.global l_xor
l_xor:
l.xor r0,r0,r0
.text
.global l_xori
l_xori:
l.xori r0,r0,0
.text
.global l_mul
l_mul:
l.mul r0,r0,r0
.text
.global l_muli
l_muli:
l.muli r0,r0,0
.text
.global l_div
l_div:
l.div r0,r0,r0
.text
.global l_divu
l_divu:
l.divu r0,r0,r0
.text
.global l_sfgts
l_sfgts:
l.sfgts r0,r0
.text
.global l_sfgtu
l_sfgtu:
l.sfgtu r0,r0
.text
.global l_sfges
l_sfges:
l.sfges r0,r0
.text
.global l_sfgeu
l_sfgeu:
l.sfgeu r0,r0
.text
.global l_sflts
l_sflts:
l.sflts r0,r0
.text
.global l_sfltu
l_sfltu:
l.sfltu r0,r0
.text
.global l_sfles
l_sfles:
l.sfles r0,r0
.text
.global l_sfleu
l_sfleu:
l.sfleu r0,r0
.text
.global l_sfgtsi
l_sfgtsi:
l.sfgtsi r0,0
.text
.global l_sfgtui
l_sfgtui:
l.sfgtui r0,0
.text
.global l_sfgesi
l_sfgesi:
l.sfgesi r0,0
.text
.global l_sfgeui
l_sfgeui:
l.sfgeui r0,0
.text
.global l_sfltsi
l_sfltsi:
l.sfltsi r0,0
.text
.global l_sfltui
l_sfltui:
l.sfltui r0,0
.text
.global l_sflesi
l_sflesi:
l.sflesi r0,0
.text
.global l_sfleui
l_sfleui:
l.sfleui r0,0
.text
.global l_sfeq
l_sfeq:
l.sfeq r0,r0
.text
.global l_sfeqi
l_sfeqi:
l.sfeqi r0,0
.text
.global l_sfne
l_sfne:
l.sfne r0,r0
.text
.global l_sfnei
l_sfnei:
l.sfnei r0,0

13
gas/testsuite/gas/openrisc/lohi.d
View File

@ -1,13 +0,0 @@
#as:
#objdump: -dr
#name: lohi
.*: +file format .*
Disassembly of section .text:
00000000 <l_lo>:
0: 94 21 be ef l.addi r1,r1,-16657
00000004 <l_hi>:
4: 18 20 de ad l.movhi r1,-8531

7
gas/testsuite/gas/openrisc/lohi.s
View File

@ -1,7 +0,0 @@
.text
.global l_lo
l_lo:
l.addi r1, r1, lo(0xdeadbeef)
.global l_hi
l_hi:
l.movhi r1, hi(0xdeadbeef)

13
gas/testsuite/gas/openrisc/store.d
View File

@ -1,13 +0,0 @@
#as:
#objdump: -dr
#name: store
.*: +file format .*
Disassembly of section .text:
00000000 <l_sw>:
0: d7 e1 0f fc l.sw -4\(r1\),r1
00000004 <l_lw>:
4: 80 21 ff 9c l.lw r1,-100\(r1\)

7
gas/testsuite/gas/openrisc/store.s
View File

@ -1,7 +0,0 @@
.text
.global l_sw
l_sw:
l.sw -4(r1), r1
.global l_lw
l_lw:
l.lw r1, -100(r1)

689
gas/testsuite/gas/or1k/allinsn.d Normal file
View File

@ -0,0 +1,689 @@
#as:
#objdump: -dr
#name: allinsn
.*: +file format .*
Disassembly of section \.text:
00000000 <localtext>:
0: 15 00 00 00 l\.nop 0x0
00000004 <globaltext>:
4: 15 00 00 00 l\.nop 0x0
00000008 <l_j>:
8: 03 ff ff ff l\.j 4 <globaltext>
c: 00 00 00 01 l\.j 10 <l_j\+0x8>
10: 00 00 00 00 l\.j 10 <l_j\+0x8>
14: 03 ff ff fb l\.j 0 <localtext>
\.\.\.
18: R_OR1K_INSN_REL_26 \.data
1c: R_OR1K_INSN_REL_26 globaltext
20: R_OR1K_INSN_REL_26 globaldata
24: 03 ff ff f9 l\.j 8 <l_j>
28: 00 00 00 01 l\.j 2c <l_jal>
0000002c <l_jal>:
2c: 07 ff ff ff l\.jal 28 <l_j\+0x20>
30: 04 00 00 01 l\.jal 34 <l_jal\+0x8>
34: 04 00 00 00 l\.jal 34 <l_jal\+0x8>
38: 07 ff ff f2 l\.jal 0 <localtext>
3c: 04 00 00 00 l\.jal 3c <l_jal\+0x10>
3c: R_OR1K_INSN_REL_26 \.data
40: 04 00 00 00 l\.jal 40 <l_jal\+0x14>
40: R_OR1K_INSN_REL_26 globaltext
44: 04 00 00 00 l\.jal 44 <l_jal\+0x18>
44: R_OR1K_INSN_REL_26 globaldata
48: 07 ff ff f0 l\.jal 8 <l_j>
4c: 07 ff ff f8 l\.jal 2c <l_jal>
00000050 <l_jr>:
50: 44 00 00 00 l\.jr r0
54: 44 00 f8 00 l\.jr r31
58: 44 00 80 00 l\.jr r16
5c: 44 00 78 00 l\.jr r15
60: 44 00 08 00 l\.jr r1
64: 44 00 d8 00 l\.jr r27
68: 44 00 70 00 l\.jr r14
6c: 44 00 b0 00 l\.jr r22
00000070 <l_jalr>:
70: 48 00 00 00 l\.jalr r0
74: 48 00 f8 00 l\.jalr r31
78: 48 00 80 00 l\.jalr r16
7c: 48 00 78 00 l\.jalr r15
80: 48 00 08 00 l\.jalr r1
84: 48 00 d8 00 l\.jalr r27
88: 48 00 70 00 l\.jalr r14
8c: 48 00 b0 00 l\.jalr r22
00000090 <l_bnf>:
90: 0f ff ff ff l\.bnf 8c <l_jalr\+0x1c>
94: 0c 00 00 01 l\.bnf 98 <l_bnf\+0x8>
98: 0c 00 00 00 l\.bnf 98 <l_bnf\+0x8>
9c: 0f ff ff d9 l\.bnf 0 <localtext>
a0: 0c 00 00 00 l\.bnf a0 <l_bnf\+0x10>
a0: R_OR1K_INSN_REL_26 \.data
a4: 0c 00 00 00 l\.bnf a4 <l_bnf\+0x14>
a4: R_OR1K_INSN_REL_26 globaltext
a8: 0c 00 00 00 l\.bnf a8 <l_bnf\+0x18>
a8: R_OR1K_INSN_REL_26 globaldata
ac: 0f ff ff d7 l\.bnf 8 <l_j>
b0: 0f ff ff df l\.bnf 2c <l_jal>
000000b4 <l_bf>:
b4: 13 ff ff ff l\.bf b0 <l_bnf\+0x20>
b8: 10 00 00 01 l\.bf bc <l_bf\+0x8>
bc: 10 00 00 00 l\.bf bc <l_bf\+0x8>
c0: 13 ff ff d0 l\.bf 0 <localtext>
c4: 10 00 00 00 l\.bf c4 <l_bf\+0x10>
c4: R_OR1K_INSN_REL_26 \.data
c8: 10 00 00 00 l\.bf c8 <l_bf\+0x14>
c8: R_OR1K_INSN_REL_26 globaltext
cc: 10 00 00 00 l\.bf cc <l_bf\+0x18>
cc: R_OR1K_INSN_REL_26 globaldata
d0: 13 ff ff ce l\.bf 8 <l_j>
d4: 13 ff ff d6 l\.bf 2c <l_jal>
000000d8 <l_trap>:
d8: 21 00 00 00 l\.trap 0x0
dc: 21 00 ff ff l\.trap 0xffff
e0: 21 00 80 00 l\.trap 0x8000
e4: 21 00 7f ff l\.trap 0x7fff
e8: 21 00 00 01 l\.trap 0x1
ec: 21 00 d1 4f l\.trap 0xd14f
f0: 21 00 7f 7c l\.trap 0x7f7c
f4: 21 00 d2 4a l\.trap 0xd24a
000000f8 <l_sys>:
f8: 20 00 00 00 l\.sys 0x0
fc: 20 00 ff ff l\.sys 0xffff
100: 20 00 80 00 l\.sys 0x8000
104: 20 00 7f ff l\.sys 0x7fff
108: 20 00 00 01 l\.sys 0x1
10c: 20 00 d2 85 l\.sys 0xd285
110: 20 00 e3 15 l\.sys 0xe315
114: 20 00 80 fa l\.sys 0x80fa
00000118 <l_rfe>:
118: 24 00 00 00 l\.rfe
0000011c <l_nop>:
11c: 15 00 00 00 l\.nop 0x0
00000120 <l_movhi>:
120: 18 00 00 00 l\.movhi r0,0x0
124: 1b e0 ff ff l\.movhi r31,0xffff
128: 1a 00 80 00 l\.movhi r16,0x8000
12c: 19 e0 7f ff l\.movhi r15,0x7fff
130: 18 20 00 01 l\.movhi r1,0x1
134: 1b 80 81 ce l\.movhi r28,0x81ce
138: 1a e0 e8 ac l\.movhi r23,0xe8ac
13c: 1a 60 d8 c0 l\.movhi r19,0xd8c0
00000140 <l_mfspr>:
140: b4 00 00 00 l\.mfspr r0,r0,0x0
144: b7 ff ff ff l\.mfspr r31,r31,0xffff
148: b6 10 80 00 l\.mfspr r16,r16,0x8000
14c: b5 ef 7f ff l\.mfspr r15,r15,0x7fff
150: b4 21 00 01 l\.mfspr r1,r1,0x1
154: b6 fd d4 98 l\.mfspr r23,r29,0xd498
158: b6 74 11 81 l\.mfspr r19,r20,0x1181
15c: b7 42 f7 d6 l\.mfspr r26,r2,0xf7d6
00000160 <l_mtspr>:
160: c0 00 00 00 l\.mtspr r0,r0,0x0
164: c3 ff ff ff l\.mtspr r31,r31,0xffff
168: c2 10 80 00 l\.mtspr r16,r16,0x8000
16c: c1 ef 7f ff l\.mtspr r15,r15,0x7fff
170: c0 01 08 01 l\.mtspr r1,r1,0x1
174: c0 fe 33 77 l\.mtspr r30,r6,0x3b77
178: c2 a9 3c cc l\.mtspr r9,r7,0xaccc
17c: c3 f9 3d 7b l\.mtspr r25,r7,0xfd7b
00000180 <l_lwz>:
180: 84 00 00 00 l\.lwz r0,0\(r0\)
184: 87 ff ff ff l\.lwz r31,-1\(r31\)
188: 86 10 80 00 l\.lwz r16,-32768\(r16\)
18c: 85 ef 7f ff l\.lwz r15,32767\(r15\)
190: 84 21 00 01 l\.lwz r1,1\(r1\)
194: 85 f9 0b 75 l\.lwz r15,2933\(r25\)
198: 86 35 fc e1 l\.lwz r17,-799\(r21\)
19c: 84 12 bb 45 l\.lwz r0,-17595\(r18\)
000001a0 <l_lws>:
1a0: 88 00 00 00 l\.lws r0,0\(r0\)
1a4: 8b ff ff ff l\.lws r31,-1\(r31\)
1a8: 8a 10 80 00 l\.lws r16,-32768\(r16\)
1ac: 89 ef 7f ff l\.lws r15,32767\(r15\)
1b0: 88 21 00 01 l\.lws r1,1\(r1\)
1b4: 88 35 bb 3a l\.lws r1,-17606\(r21\)
1b8: 89 df 69 0b l\.lws r14,26891\(r31\)
1bc: 89 00 6b a0 l\.lws r8,27552\(r0\)
000001c0 <l_lbz>:
1c0: 8c 00 00 00 l\.lbz r0,0\(r0\)
1c4: 8f ff ff ff l\.lbz r31,-1\(r31\)
1c8: 8e 10 80 00 l\.lbz r16,-32768\(r16\)
1cc: 8d ef 7f ff l\.lbz r15,32767\(r15\)
1d0: 8c 21 00 01 l\.lbz r1,1\(r1\)
1d4: 8e 74 64 23 l\.lbz r19,25635\(r20\)
1d8: 8d e9 f2 a8 l\.lbz r15,-3416\(r9\)
1dc: 8c 61 45 54 l\.lbz r3,17748\(r1\)
000001e0 <l_lbs>:
1e0: 90 00 00 00 l\.lbs r0,0\(r0\)
1e4: 93 ff ff ff l\.lbs r31,-1\(r31\)
1e8: 92 10 80 00 l\.lbs r16,-32768\(r16\)
1ec: 91 ef 7f ff l\.lbs r15,32767\(r15\)
1f0: 90 21 00 01 l\.lbs r1,1\(r1\)
1f4: 93 48 44 c6 l\.lbs r26,17606\(r8\)
1f8: 92 d0 86 a0 l\.lbs r22,-31072\(r16\)
1fc: 90 c9 44 20 l\.lbs r6,17440\(r9\)
00000200 <l_lhz>:
200: 94 00 00 00 l\.lhz r0,0\(r0\)
204: 97 ff ff ff l\.lhz r31,-1\(r31\)
208: 96 10 80 00 l\.lhz r16,-32768\(r16\)
20c: 95 ef 7f ff l\.lhz r15,32767\(r15\)
210: 94 21 00 01 l\.lhz r1,1\(r1\)
214: 94 a4 e9 dd l\.lhz r5,-5667\(r4\)
218: 97 04 16 d8 l\.lhz r24,5848\(r4\)
21c: 95 47 7b bb l\.lhz r10,31675\(r7\)
00000220 <l_lhs>:
220: 98 00 00 00 l\.lhs r0,0\(r0\)
224: 9b ff ff ff l\.lhs r31,-1\(r31\)
228: 9a 10 80 00 l\.lhs r16,-32768\(r16\)
22c: 99 ef 7f ff l\.lhs r15,32767\(r15\)
230: 98 21 00 01 l\.lhs r1,1\(r1\)
234: 98 cb ff 72 l\.lhs r6,-142\(r11\)
238: 9a 9d eb 46 l\.lhs r20,-5306\(r29\)
23c: 99 f5 10 52 l\.lhs r15,4178\(r21\)
00000240 <l_sw>:
240: d4 00 00 00 l\.sw 0\(r0\),r0
244: d7 ff ff ff l\.sw -1\(r31\),r31
248: d6 10 80 00 l\.sw -32768\(r16\),r16
24c: d5 ef 7f ff l\.sw 32767\(r15\),r15
250: d4 01 08 01 l\.sw 1\(r1\),r1
254: d7 91 50 e1 l\.sw -7967\(r17\),r10
258: d4 1e 57 20 l\.sw 1824\(r30\),r10
25c: d5 ef 23 4e l\.sw 31566\(r15\),r4
00000260 <l_sb>:
260: d8 00 00 00 l\.sb 0\(r0\),r0
264: db ff ff ff l\.sb -1\(r31\),r31
268: da 10 80 00 l\.sb -32768\(r16\),r16
26c: d9 ef 7f ff l\.sb 32767\(r15\),r15
270: d8 01 08 01 l\.sb 1\(r1\),r1
274: d9 4a 06 b8 l\.sb 22200\(r10\),r0
278: d8 90 df 0b l\.sb 9995\(r16\),r27
27c: da 4e f9 9c l\.sb -28260\(r14\),r31
00000280 <l_sh>:
280: dc 00 00 00 l\.sh 0\(r0\),r0
284: df ff ff ff l\.sh -1\(r31\),r31
288: de 10 80 00 l\.sh -32768\(r16\),r16
28c: dd ef 7f ff l\.sh 32767\(r15\),r15
290: dc 01 08 01 l\.sh 1\(r1\),r1
294: dc b5 c9 bd l\.sh 10685\(r21\),r25
298: df 3c 2c f6 l\.sh -13066\(r28\),r5
29c: de 49 ef 50 l\.sh -26800\(r9\),r29
000002a0 <l_sll>:
2a0: e0 00 00 08 l\.sll r0,r0,r0
2a4: e3 ff f8 08 l\.sll r31,r31,r31
2a8: e2 10 80 08 l\.sll r16,r16,r16
2ac: e1 ef 78 08 l\.sll r15,r15,r15
2b0: e0 21 08 08 l\.sll r1,r1,r1
2b4: e3 f0 40 08 l\.sll r31,r16,r8
2b8: e3 f1 b0 08 l\.sll r31,r17,r22
2bc: e1 ee 28 08 l\.sll r15,r14,r5
000002c0 <l_slli>:
2c0: b8 00 00 00 l\.slli r0,r0,0x0
2c4: bb ff 00 3f l\.slli r31,r31,0x3f
2c8: ba 10 00 20 l\.slli r16,r16,0x20
2cc: b9 ef 00 1f l\.slli r15,r15,0x1f
2d0: b8 21 00 01 l\.slli r1,r1,0x1
2d4: b9 6e 00 31 l\.slli r11,r14,0x31
2d8: b8 fb 00 17 l\.slli r7,r27,0x17
2dc: bb d0 00 0b l\.slli r30,r16,0xb
000002e0 <l_srl>:
2e0: e0 00 00 48 l\.srl r0,r0,r0
2e4: e3 ff f8 48 l\.srl r31,r31,r31
2e8: e2 10 80 48 l\.srl r16,r16,r16
2ec: e1 ef 78 48 l\.srl r15,r15,r15
2f0: e0 21 08 48 l\.srl r1,r1,r1
2f4: e1 f9 68 48 l\.srl r15,r25,r13
2f8: e2 60 88 48 l\.srl r19,r0,r17
2fc: e1 a0 b8 48 l\.srl r13,r0,r23
00000300 <l_srli>:
300: b8 00 00 40 l\.srli r0,r0,0x0
304: bb ff 00 7f l\.srli r31,r31,0x3f
308: ba 10 00 60 l\.srli r16,r16,0x20
30c: b9 ef 00 5f l\.srli r15,r15,0x1f
310: b8 21 00 41 l\.srli r1,r1,0x1
314: b9 fe 00 4d l\.srli r15,r30,0xd
318: b9 a3 00 7f l\.srli r13,r3,0x3f
31c: b8 52 00 5e l\.srli r2,r18,0x1e
00000320 <l_sra>:
320: e0 00 00 88 l\.sra r0,r0,r0
324: e3 ff f8 88 l\.sra r31,r31,r31
328: e2 10 80 88 l\.sra r16,r16,r16
32c: e1 ef 78 88 l\.sra r15,r15,r15
330: e0 21 08 88 l\.sra r1,r1,r1
334: e0 7a 00 88 l\.sra r3,r26,r0
338: e3 b2 d8 88 l\.sra r29,r18,r27
33c: e3 7d 18 88 l\.sra r27,r29,r3
00000340 <l_srai>:
340: b8 00 00 80 l\.srai r0,r0,0x0
344: bb ff 00 bf l\.srai r31,r31,0x3f
348: ba 10 00 a0 l\.srai r16,r16,0x20
34c: b9 ef 00 9f l\.srai r15,r15,0x1f
350: b8 21 00 81 l\.srai r1,r1,0x1
354: b9 4b 00 9c l\.srai r10,r11,0x1c
358: ba ef 00 b0 l\.srai r23,r15,0x30
35c: ba 0f 00 a6 l\.srai r16,r15,0x26
00000360 <l_ror>:
360: e0 00 00 c8 l\.ror r0,r0,r0
364: e3 ff f8 c8 l\.ror r31,r31,r31
368: e2 10 80 c8 l\.ror r16,r16,r16
36c: e1 ef 78 c8 l\.ror r15,r15,r15
370: e0 21 08 c8 l\.ror r1,r1,r1
374: e3 ac 28 c8 l\.ror r29,r12,r5
378: e2 46 20 c8 l\.ror r18,r6,r4
37c: e0 50 88 c8 l\.ror r2,r16,r17
00000380 <l_rori>:
380: b8 00 00 c0 l\.rori r0,r0,0x0
384: bb ff 00 ff l\.rori r31,r31,0x3f
388: ba 10 00 e0 l\.rori r16,r16,0x20
38c: b9 ef 00 df l\.rori r15,r15,0x1f
390: b8 21 00 c1 l\.rori r1,r1,0x1
394: ba 20 00 d7 l\.rori r17,r0,0x17
398: ba 1f 00 ea l\.rori r16,r31,0x2a
39c: b9 b5 00 cc l\.rori r13,r21,0xc
000003a0 <l_add>:
3a0: e0 00 00 00 l\.add r0,r0,r0
3a4: e3 ff f8 00 l\.add r31,r31,r31
3a8: e2 10 80 00 l\.add r16,r16,r16
3ac: e1 ef 78 00 l\.add r15,r15,r15
3b0: e0 21 08 00 l\.add r1,r1,r1
3b4: e3 a7 20 00 l\.add r29,r7,r4
3b8: e3 aa 90 00 l\.add r29,r10,r18
3bc: e2 56 b8 00 l\.add r18,r22,r23
000003c0 <l_sub>:
3c0: e0 00 00 02 l\.sub r0,r0,r0
3c4: e3 ff f8 02 l\.sub r31,r31,r31
3c8: e2 10 80 02 l\.sub r16,r16,r16
3cc: e1 ef 78 02 l\.sub r15,r15,r15
3d0: e0 21 08 02 l\.sub r1,r1,r1
3d4: e2 fa 70 02 l\.sub r23,r26,r14
3d8: e1 58 78 02 l\.sub r10,r24,r15
3dc: e1 64 90 02 l\.sub r11,r4,r18
000003e0 <l_and>:
3e0: e0 00 00 03 l\.and r0,r0,r0
3e4: e3 ff f8 03 l\.and r31,r31,r31
3e8: e2 10 80 03 l\.and r16,r16,r16
3ec: e1 ef 78 03 l\.and r15,r15,r15
3f0: e0 21 08 03 l\.and r1,r1,r1
3f4: e0 1f c8 03 l\.and r0,r31,r25
3f8: e3 c7 98 03 l\.and r30,r7,r19
3fc: e2 62 d0 03 l\.and r19,r2,r26
00000400 <l_or>:
400: e0 00 00 04 l\.or r0,r0,r0
404: e3 ff f8 04 l\.or r31,r31,r31
408: e2 10 80 04 l\.or r16,r16,r16
40c: e1 ef 78 04 l\.or r15,r15,r15
410: e0 21 08 04 l\.or r1,r1,r1
414: e2 2a 10 04 l\.or r17,r10,r2
418: e0 f3 e8 04 l\.or r7,r19,r29
41c: e0 71 88 04 l\.or r3,r17,r17
00000420 <l_xor>:
420: e0 00 00 05 l\.xor r0,r0,r0
424: e3 ff f8 05 l\.xor r31,r31,r31
428: e2 10 80 05 l\.xor r16,r16,r16
42c: e1 ef 78 05 l\.xor r15,r15,r15
430: e0 21 08 05 l\.xor r1,r1,r1
434: e3 e5 88 05 l\.xor r31,r5,r17
438: e2 c4 28 05 l\.xor r22,r4,r5
43c: e3 d4 d0 05 l\.xor r30,r20,r26
00000440 <l_addc>:
440: e0 00 00 01 l\.addc r0,r0,r0
444: e3 ff f8 01 l\.addc r31,r31,r31
448: e2 10 80 01 l\.addc r16,r16,r16
44c: e1 ef 78 01 l\.addc r15,r15,r15
450: e0 21 08 01 l\.addc r1,r1,r1
454: e1 1a c0 01 l\.addc r8,r26,r24
458: e2 46 20 01 l\.addc r18,r6,r4
45c: e3 a0 90 01 l\.addc r29,r0,r18
00000460 <l_mul>:
460: e0 00 03 06 l\.mul r0,r0,r0
464: e3 ff fb 06 l\.mul r31,r31,r31
468: e2 10 83 06 l\.mul r16,r16,r16
46c: e1 ef 7b 06 l\.mul r15,r15,r15
470: e0 21 0b 06 l\.mul r1,r1,r1
474: e1 19 6b 06 l\.mul r8,r25,r13
478: e1 15 eb 06 l\.mul r8,r21,r29
47c: e3 63 8b 06 l\.mul r27,r3,r17
00000480 <l_mulu>:
480: e0 00 03 0b l\.mulu r0,r0,r0
484: e3 ff fb 0b l\.mulu r31,r31,r31
488: e2 10 83 0b l\.mulu r16,r16,r16
48c: e1 ef 7b 0b l\.mulu r15,r15,r15
490: e0 21 0b 0b l\.mulu r1,r1,r1
494: e3 4e 83 0b l\.mulu r26,r14,r16
498: e0 32 5b 0b l\.mulu r1,r18,r11
49c: e1 d2 8b 0b l\.mulu r14,r18,r17
000004a0 <l_div>:
4a0: e0 00 03 09 l\.div r0,r0,r0
4a4: e3 ff fb 09 l\.div r31,r31,r31
4a8: e2 10 83 09 l\.div r16,r16,r16
4ac: e1 ef 7b 09 l\.div r15,r15,r15
4b0: e0 21 0b 09 l\.div r1,r1,r1
4b4: e0 02 e3 09 l\.div r0,r2,r28
4b8: e3 47 fb 09 l\.div r26,r7,r31
4bc: e0 52 a3 09 l\.div r2,r18,r20
000004c0 <l_divu>:
4c0: e0 00 03 0a l\.divu r0,r0,r0
4c4: e3 ff fb 0a l\.divu r31,r31,r31
4c8: e2 10 83 0a l\.divu r16,r16,r16
4cc: e1 ef 7b 0a l\.divu r15,r15,r15
4d0: e0 21 0b 0a l\.divu r1,r1,r1
4d4: e0 a4 cb 0a l\.divu r5,r4,r25
4d8: e1 0b eb 0a l\.divu r8,r11,r29
4dc: e1 73 13 0a l\.divu r11,r19,r2
000004e0 <l_addi>:
4e0: 9c 00 00 00 l\.addi r0,r0,0
4e4: 9f ff ff ff l\.addi r31,r31,-1
4e8: 9e 10 80 00 l\.addi r16,r16,-32768
4ec: 9d ef 7f ff l\.addi r15,r15,32767
4f0: 9c 21 00 01 l\.addi r1,r1,1
4f4: 9d c0 1b 6c l\.addi r14,r0,7020
4f8: 9d ae 37 33 l\.addi r13,r14,14131
4fc: 9d d0 97 3b l\.addi r14,r16,-26821
00000500 <l_andi>:
500: a4 00 00 00 l\.andi r0,r0,0x0
504: a7 ff ff ff l\.andi r31,r31,0xffff
508: a6 10 80 00 l\.andi r16,r16,0x8000
50c: a5 ef 7f ff l\.andi r15,r15,0x7fff
510: a4 21 00 01 l\.andi r1,r1,0x1
514: a7 75 2e 97 l\.andi r27,r21,0x2e97
518: a6 b7 2f 1b l\.andi r21,r23,0x2f1b
51c: a7 de 83 c4 l\.andi r30,r30,0x83c4
00000520 <l_ori>:
520: a8 00 00 00 l\.ori r0,r0,0x0
524: ab ff ff ff l\.ori r31,r31,0xffff
528: aa 10 80 00 l\.ori r16,r16,0x8000
52c: a9 ef 7f ff l\.ori r15,r15,0x7fff
530: a8 21 00 01 l\.ori r1,r1,0x1
534: aa db d8 81 l\.ori r22,r27,0xd881
538: aa 3f 00 80 l\.ori r17,r31,0x80
53c: a9 b4 cf 6d l\.ori r13,r20,0xcf6d
00000540 <l_xori>:
540: ac 00 00 00 l\.xori r0,r0,0
544: af ff ff ff l\.xori r31,r31,-1
548: ae 10 80 00 l\.xori r16,r16,-32768
54c: ad ef 7f ff l\.xori r15,r15,32767
550: ac 21 00 01 l\.xori r1,r1,1
554: ae 50 ff ff l\.xori r18,r16,-1
558: af 2d c0 35 l\.xori r25,r13,-16331
55c: ad 9d 80 29 l\.xori r12,r29,-32727
00000560 <l_muli>:
560: b0 00 00 00 l\.muli r0,r0,0
564: b3 ff ff ff l\.muli r31,r31,-1
568: b2 10 80 00 l\.muli r16,r16,-32768
56c: b1 ef 7f ff l\.muli r15,r15,32767
570: b0 21 00 01 l\.muli r1,r1,1
574: b3 67 ed 85 l\.muli r27,r7,-4731
578: b0 f4 ff ff l\.muli r7,r20,-1
57c: b3 15 5a b3 l\.muli r24,r21,23219
00000580 <l_addic>:
580: a0 00 00 00 l\.addic r0,r0,0
584: a3 ff ff ff l\.addic r31,r31,-1
588: a2 10 80 00 l\.addic r16,r16,-32768
58c: a1 ef 7f ff l\.addic r15,r15,32767
590: a0 21 00 01 l\.addic r1,r1,1
594: a0 d6 80 44 l\.addic r6,r22,-32700
598: a2 69 ff ff l\.addic r19,r9,-1
59c: a3 7c 1a eb l\.addic r27,r28,6891
000005a0 <l_sfgtu>:
5a0: e4 40 00 00 l\.sfgtu r0,r0
5a4: e4 5f f8 00 l\.sfgtu r31,r31
5a8: e4 50 80 00 l\.sfgtu r16,r16
5ac: e4 4f 78 00 l\.sfgtu r15,r15
5b0: e4 41 08 00 l\.sfgtu r1,r1
5b4: e4 48 20 00 l\.sfgtu r8,r4
5b8: e4 51 a8 00 l\.sfgtu r17,r21
5bc: e4 46 28 00 l\.sfgtu r6,r5
000005c0 <l_sfgeu>:
5c0: e4 60 00 00 l\.sfgeu r0,r0
5c4: e4 7f f8 00 l\.sfgeu r31,r31
5c8: e4 70 80 00 l\.sfgeu r16,r16
5cc: e4 6f 78 00 l\.sfgeu r15,r15
5d0: e4 61 08 00 l\.sfgeu r1,r1
5d4: e4 6e 60 00 l\.sfgeu r14,r12
5d8: e4 76 38 00 l\.sfgeu r22,r7
5dc: e4 6d 08 00 l\.sfgeu r13,r1
000005e0 <l_sfltu>:
5e0: e4 80 00 00 l\.sfltu r0,r0
5e4: e4 9f f8 00 l\.sfltu r31,r31
5e8: e4 90 80 00 l\.sfltu r16,r16
5ec: e4 8f 78 00 l\.sfltu r15,r15
5f0: e4 81 08 00 l\.sfltu r1,r1
5f4: e4 81 68 00 l\.sfltu r1,r13
5f8: e4 96 f0 00 l\.sfltu r22,r30
5fc: e4 94 30 00 l\.sfltu r20,r6
00000600 <l_sfleu>:
600: e4 a0 00 00 l\.sfleu r0,r0
604: e4 bf f8 00 l\.sfleu r31,r31
608: e4 b0 80 00 l\.sfleu r16,r16
60c: e4 af 78 00 l\.sfleu r15,r15
610: e4 a1 08 00 l\.sfleu r1,r1
614: e4 b3 40 00 l\.sfleu r19,r8
618: e4 bb 78 00 l\.sfleu r27,r15
61c: e4 bb 18 00 l\.sfleu r27,r3
00000620 <l_sfgts>:
620: e5 40 00 00 l\.sfgts r0,r0
624: e5 5f f8 00 l\.sfgts r31,r31
628: e5 50 80 00 l\.sfgts r16,r16
62c: e5 4f 78 00 l\.sfgts r15,r15
630: e5 41 08 00 l\.sfgts r1,r1
634: e5 45 28 00 l\.sfgts r5,r5
638: e5 5f 28 00 l\.sfgts r31,r5
63c: e5 5e 90 00 l\.sfgts r30,r18
00000640 <l_sfges>:
640: e5 60 00 00 l\.sfges r0,r0
644: e5 7f f8 00 l\.sfges r31,r31
648: e5 70 80 00 l\.sfges r16,r16
64c: e5 6f 78 00 l\.sfges r15,r15
650: e5 61 08 00 l\.sfges r1,r1
654: e5 71 90 00 l\.sfges r17,r18
658: e5 60 48 00 l\.sfges r0,r9
65c: e5 76 c8 00 l\.sfges r22,r25
00000660 <l_sflts>:
660: e5 80 00 00 l\.sflts r0,r0
664: e5 9f f8 00 l\.sflts r31,r31
668: e5 90 80 00 l\.sflts r16,r16
66c: e5 8f 78 00 l\.sflts r15,r15
670: e5 81 08 00 l\.sflts r1,r1
674: e5 99 c0 00 l\.sflts r25,r24
678: e5 97 68 00 l\.sflts r23,r13
67c: e5 8f 40 00 l\.sflts r15,r8
00000680 <l_sfles>:
680: e5 a0 00 00 l\.sfles r0,r0
684: e5 bf f8 00 l\.sfles r31,r31
688: e5 b0 80 00 l\.sfles r16,r16
68c: e5 af 78 00 l\.sfles r15,r15
690: e5 a1 08 00 l\.sfles r1,r1
694: e5 b1 68 00 l\.sfles r17,r13
698: e5 be c8 00 l\.sfles r30,r25
69c: e5 a0 60 00 l\.sfles r0,r12
000006a0 <l_sfgtui>:
6a0: bc 40 00 00 l\.sfgtui r0,0
6a4: bc 5f ff ff l\.sfgtui r31,-1
6a8: bc 50 80 00 l\.sfgtui r16,-32768
6ac: bc 4f 7f ff l\.sfgtui r15,32767
6b0: bc 41 00 01 l\.sfgtui r1,1
6b4: bc 45 4b 21 l\.sfgtui r5,19233
6b8: bc 57 91 22 l\.sfgtui r23,-28382
6bc: bc 51 25 dd l\.sfgtui r17,9693
000006c0 <l_sfgeui>:
6c0: bc 60 00 00 l\.sfgeui r0,0
6c4: bc 7f ff ff l\.sfgeui r31,-1
6c8: bc 70 80 00 l\.sfgeui r16,-32768
6cc: bc 6f 7f ff l\.sfgeui r15,32767
6d0: bc 61 00 01 l\.sfgeui r1,1
6d4: bc 71 ec b6 l\.sfgeui r17,-4938
6d8: bc 6f 40 13 l\.sfgeui r15,16403
6dc: bc 66 f1 a4 l\.sfgeui r6,-3676
000006e0 <l_sfltui>:
6e0: bc 80 00 00 l\.sfltui r0,0
6e4: bc 9f ff ff l\.sfltui r31,-1
6e8: bc 90 80 00 l\.sfltui r16,-32768
6ec: bc 8f 7f ff l\.sfltui r15,32767
6f0: bc 81 00 01 l\.sfltui r1,1
6f4: bc 83 cc af l\.sfltui r3,-13137
6f8: bc 98 4c fd l\.sfltui r24,19709
6fc: bc 8a 03 3e l\.sfltui r10,830
00000700 <l_sfleui>:
700: bc a0 00 00 l\.sfleui r0,0
704: bc bf ff ff l\.sfleui r31,-1
708: bc b0 80 00 l\.sfleui r16,-32768
70c: bc af 7f ff l\.sfleui r15,32767
710: bc a1 00 01 l\.sfleui r1,1
714: bc b7 9b 66 l\.sfleui r23,-25754
718: bc b1 b6 d7 l\.sfleui r17,-18729
71c: bc a9 a8 81 l\.sfleui r9,-22399
00000720 <l_sfgtsi>:
720: bd 40 00 00 l\.sfgtsi r0,0
724: bd 5f ff ff l\.sfgtsi r31,-1
728: bd 50 80 00 l\.sfgtsi r16,-32768
72c: bd 4f 7f ff l\.sfgtsi r15,32767
730: bd 41 00 01 l\.sfgtsi r1,1
734: bd 4d b6 82 l\.sfgtsi r13,-18814
738: bd 4d d6 5f l\.sfgtsi r13,-10657
73c: bd 5c 97 d5 l\.sfgtsi r28,-26667
00000740 <l_sfgesi>:
740: bd 60 00 00 l\.sfgesi r0,0
744: bd 7f ff ff l\.sfgesi r31,-1
748: bd 70 80 00 l\.sfgesi r16,-32768
74c: bd 6f 7f ff l\.sfgesi r15,32767
750: bd 61 00 01 l\.sfgesi r1,1
754: bd 6c 09 48 l\.sfgesi r12,2376
758: bd 69 7d 3b l\.sfgesi r9,32059
75c: bd 6d 50 d8 l\.sfgesi r13,20696
00000760 <l_sfltsi>:
760: bd 80 00 00 l\.sfltsi r0,0
764: bd 9f ff ff l\.sfltsi r31,-1
768: bd 90 80 00 l\.sfltsi r16,-32768
76c: bd 8f 7f ff l\.sfltsi r15,32767
770: bd 81 00 01 l\.sfltsi r1,1
774: bd 9e 0b cd l\.sfltsi r30,3021
778: bd 85 93 5b l\.sfltsi r5,-27813
77c: bd 9c dd 90 l\.sfltsi r28,-8816
00000780 <l_sflesi>:
780: bd a0 00 00 l\.sflesi r0,0
784: bd bf ff ff l\.sflesi r31,-1
788: bd b0 80 00 l\.sflesi r16,-32768
78c: bd af 7f ff l\.sflesi r15,32767
790: bd a1 00 01 l\.sflesi r1,1
794: bd b2 2c 4a l\.sflesi r18,11338
798: bd bd 49 b9 l\.sflesi r29,18873
79c: bd bc 65 c2 l\.sflesi r28,26050
000007a0 <l_sfeq>:
7a0: e4 00 00 00 l\.sfeq r0,r0
7a4: e4 1f f8 00 l\.sfeq r31,r31
7a8: e4 10 80 00 l\.sfeq r16,r16
7ac: e4 0f 78 00 l\.sfeq r15,r15
7b0: e4 01 08 00 l\.sfeq r1,r1
7b4: e4 1c d0 00 l\.sfeq r28,r26
7b8: e4 0d 30 00 l\.sfeq r13,r6
7bc: e4 1a 48 00 l\.sfeq r26,r9
000007c0 <l_sfeqi>:
7c0: bc 00 00 00 l\.sfeqi r0,0
7c4: bc 1f ff ff l\.sfeqi r31,-1
7c8: bc 10 80 00 l\.sfeqi r16,-32768
7cc: bc 0f 7f ff l\.sfeqi r15,32767
7d0: bc 01 00 01 l\.sfeqi r1,1
7d4: bc 0a 65 1f l\.sfeqi r10,25887
7d8: bc 15 4d b6 l\.sfeqi r21,19894
7dc: bc 12 cb 95 l\.sfeqi r18,-13419
000007e0 <l_sfne>:
7e0: e4 20 00 00 l\.sfne r0,r0
7e4: e4 3f f8 00 l\.sfne r31,r31
7e8: e4 30 80 00 l\.sfne r16,r16
7ec: e4 2f 78 00 l\.sfne r15,r15
7f0: e4 21 08 00 l\.sfne r1,r1
7f4: e4 32 d8 00 l\.sfne r18,r27
7f8: e4 26 90 00 l\.sfne r6,r18
7fc: e4 20 f0 00 l\.sfne r0,r30
00000800 <l_sfnei>:
800: bc 20 00 00 l\.sfnei r0,0
804: bc 3f ff ff l\.sfnei r31,-1
808: bc 30 80 00 l\.sfnei r16,-32768
80c: bc 2f 7f ff l\.sfnei r15,32767
810: bc 21 00 01 l\.sfnei r1,1
814: bc 28 2c 92 l\.sfnei r8,11410
818: bc 26 b4 d9 l\.sfnei r6,-19239
81c: bc 34 a7 01 l\.sfnei r20,-22783
00000820 <l_lo>:
820: 9c 21 be ef l\.addi r1,r1,-16657
00000824 <l_hi>:
824: 18 20 de ad l\.movhi r1,0xdead
00000828 <l_mac>:
828: c4 01 10 01 l.mac r1,r2
0000082c <l_maci>:
82c: 4c 01 00 00 l\.maci r1,0
830: 4c 02 ff ff l\.maci r2,-1
834: 4c 02 7f ff l\.maci r2,32767
838: 4c 02 80 00 l\.maci r2,-32768

5
gas/testsuite/gas/or1k/allinsn.exp Normal file
View File

@ -0,0 +1,5 @@
# OR1K assembler testsuite. -*- Tcl -*-
if [istarget or1k*-*-*] {
run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
}

677
gas/testsuite/gas/or1k/allinsn.s Normal file
View File

@ -0,0 +1,677 @@
.data
localdata:
.word 42
.text
localtext:
l.nop
.data
.global globaldata
globaldata:
.word 43
.text
.global globaltext
globaltext:
l.nop
l_j:
l.j -4
l.j 4
l.j 0
l.j localtext
l.j localdata
l.j globaltext
l.j globaldata
l.j l_j
l.j l_jal
.text
l_jal:
l.jal -4
l.jal 4
l.jal 0
l.jal localtext
l.jal localdata
l.jal globaltext
l.jal globaldata
l.jal l_j
l.jal l_jal
.text
l_jr:
l.jr r0
l.jr r31
l.jr r16
l.jr r15
l.jr r1
l.jr r27
l.jr r14
l.jr r22
.text
l_jalr:
l.jalr r0
l.jalr r31
l.jalr r16
l.jalr r15
l.jalr r1
l.jalr r27
l.jalr r14
l.jalr r22
.text
l_bnf:
l.bnf -4
l.bnf 4
l.bnf 0
l.bnf localtext
l.bnf localdata
l.bnf globaltext
l.bnf globaldata
l.bnf l_j
l.bnf l_jal
.text
l_bf:
l.bf -4
l.bf 4
l.bf 0
l.bf localtext
l.bf localdata
l.bf globaltext
l.bf globaldata
l.bf l_j
l.bf l_jal
.text
l_trap:
l.trap 0
l.trap 65535
l.trap 32768
l.trap 32767
l.trap 1
l.trap 53583
l.trap 32636
l.trap 53834
.text
l_sys:
l.sys 0
l.sys 65535
l.sys 32768
l.sys 32767
l.sys 1
l.sys 53893
l.sys 58133
l.sys 33018
.text
l_rfe:
l.rfe
.text
l_nop:
l.nop
.text
l_movhi:
l.movhi r0,0
l.movhi r31,-1
l.movhi r16,-32768
l.movhi r15,32767
l.movhi r1,1
l.movhi r28,-32306
l.movhi r23,-5972
l.movhi r19,-10048
.text
l_mfspr:
l.mfspr r0,r0,0
l.mfspr r31,r31,65535
l.mfspr r16,r16,32768
l.mfspr r15,r15,32767
l.mfspr r1,r1,1
l.mfspr r23,r29,54424
l.mfspr r19,r20,4481
l.mfspr r26,r2,63446
.text
l_mtspr:
l.mtspr r0,r0,0
l.mtspr r31,r31,-1
l.mtspr r16,r16,-32768
l.mtspr r15,r15,32767
l.mtspr r1,r1,1
l.mtspr r30,r6,15223
l.mtspr r9,r7,-21300
l.mtspr r25,r7,-645
.text
l_lwz:
l.lwz r0,0(r0)
l.lwz r31,-1(r31)
l.lwz r16,-32768(r16)
l.lwz r15,32767(r15)
l.lwz r1,1(r1)
l.lwz r15,2933(r25)
l.lwz r17,-799(r21)
l.lwz r0,-17595(r18)
.text
l_lws:
l.lws r0,0(r0)
l.lws r31,-1(r31)
l.lws r16,-32768(r16)
l.lws r15,32767(r15)
l.lws r1,1(r1)
l.lws r1,-17606(r21)
l.lws r14,26891(r31)
l.lws r8,27552(r0)
.text
l_lbz:
l.lbz r0,0(r0)
l.lbz r31,-1(r31)
l.lbz r16,-32768(r16)
l.lbz r15,32767(r15)
l.lbz r1,1(r1)
l.lbz r19,25635(r20)
l.lbz r15,-3416(r9)
l.lbz r3,17748(r1)
.text
l_lbs:
l.lbs r0,0(r0)
l.lbs r31,-1(r31)
l.lbs r16,-32768(r16)
l.lbs r15,32767(r15)
l.lbs r1,1(r1)
l.lbs r26,17606(r8)
l.lbs r22,-31072(r16)
l.lbs r6,17440(r9)
.text
l_lhz:
l.lhz r0,0(r0)
l.lhz r31,-1(r31)
l.lhz r16,-32768(r16)
l.lhz r15,32767(r15)
l.lhz r1,1(r1)
l.lhz r5,-5667(r4)
l.lhz r24,5848(r4)
l.lhz r10,31675(r7)
.text
l_lhs:
l.lhs r0,0(r0)
l.lhs r31,-1(r31)
l.lhs r16,-32768(r16)
l.lhs r15,32767(r15)
l.lhs r1,1(r1)
l.lhs r6,-142(r11)
l.lhs r20,-5306(r29)
l.lhs r15,4178(r21)
.text
l_sw:
l.sw 0(r0),r0
l.sw -1(r31),r31
l.sw -32768(r16),r16
l.sw 32767(r15),r15
l.sw 1(r1),r1
l.sw -7967(r17),r10
l.sw 1824(r30),r10
l.sw 31566(r15),r4
.text
l_sb:
l.sb 0(r0),r0
l.sb -1(r31),r31
l.sb -32768(r16),r16
l.sb 32767(r15),r15
l.sb 1(r1),r1
l.sb 22200(r10),r0
l.sb 9995(r16),r27
l.sb -28260(r14),r31
.text
l_sh:
l.sh 0(r0),r0
l.sh -1(r31),r31
l.sh -32768(r16),r16
l.sh 32767(r15),r15
l.sh 1(r1),r1
l.sh 10685(r21),r25
l.sh -13066(r28),r5
l.sh -26800(r9),r29
.text
l_sll:
l.sll r0,r0,r0
l.sll r31,r31,r31
l.sll r16,r16,r16
l.sll r15,r15,r15
l.sll r1,r1,r1
l.sll r31,r16,r8
l.sll r31,r17,r22
l.sll r15,r14,r5
.text
l_slli:
l.slli r0,r0,0
l.slli r31,r31,63
l.slli r16,r16,32
l.slli r15,r15,31
l.slli r1,r1,1
l.slli r11,r14,49
l.slli r7,r27,23
l.slli r30,r16,11
.text
l_srl:
l.srl r0,r0,r0
l.srl r31,r31,r31
l.srl r16,r16,r16
l.srl r15,r15,r15
l.srl r1,r1,r1
l.srl r15,r25,r13
l.srl r19,r0,r17
l.srl r13,r0,r23
.text
l_srli:
l.srli r0,r0,0
l.srli r31,r31,63
l.srli r16,r16,32
l.srli r15,r15,31
l.srli r1,r1,1
l.srli r15,r30,13
l.srli r13,r3,63
l.srli r2,r18,30
.text
l_sra:
l.sra r0,r0,r0
l.sra r31,r31,r31
l.sra r16,r16,r16
l.sra r15,r15,r15
l.sra r1,r1,r1
l.sra r3,r26,r0
l.sra r29,r18,r27
l.sra r27,r29,r3
.text
l_srai:
l.srai r0,r0,0
l.srai r31,r31,63
l.srai r16,r16,32
l.srai r15,r15,31
l.srai r1,r1,1
l.srai r10,r11,28
l.srai r23,r15,48
l.srai r16,r15,38
.text
l_ror:
l.ror r0,r0,r0
l.ror r31,r31,r31
l.ror r16,r16,r16
l.ror r15,r15,r15
l.ror r1,r1,r1
l.ror r29,r12,r5
l.ror r18,r6,r4
l.ror r2,r16,r17
.text
l_rori:
l.rori r0,r0,0
l.rori r31,r31,63
l.rori r16,r16,32
l.rori r15,r15,31
l.rori r1,r1,1
l.rori r17,r0,23
l.rori r16,r31,42
l.rori r13,r21,12
.text
l_add:
l.add r0,r0,r0
l.add r31,r31,r31
l.add r16,r16,r16
l.add r15,r15,r15
l.add r1,r1,r1
l.add r29,r7,r4
l.add r29,r10,r18
l.add r18,r22,r23
.text
l_sub:
l.sub r0,r0,r0
l.sub r31,r31,r31
l.sub r16,r16,r16
l.sub r15,r15,r15
l.sub r1,r1,r1
l.sub r23,r26,r14
l.sub r10,r24,r15
l.sub r11,r4,r18
.text
l_and:
l.and r0,r0,r0
l.and r31,r31,r31
l.and r16,r16,r16
l.and r15,r15,r15
l.and r1,r1,r1
l.and r0,r31,r25
l.and r30,r7,r19
l.and r19,r2,r26
.text
l_or:
l.or r0,r0,r0
l.or r31,r31,r31
l.or r16,r16,r16
l.or r15,r15,r15
l.or r1,r1,r1
l.or r17,r10,r2
l.or r7,r19,r29
l.or r3,r17,r17
.text
l_xor:
l.xor r0,r0,r0
l.xor r31,r31,r31
l.xor r16,r16,r16
l.xor r15,r15,r15
l.xor r1,r1,r1
l.xor r31,r5,r17
l.xor r22,r4,r5
l.xor r30,r20,r26
.text
l_addc:
l.addc r0,r0,r0
l.addc r31,r31,r31
l.addc r16,r16,r16
l.addc r15,r15,r15
l.addc r1,r1,r1
l.addc r8,r26,r24
l.addc r18,r6,r4
l.addc r29,r0,r18
.text
l_mul:
l.mul r0,r0,r0
l.mul r31,r31,r31
l.mul r16,r16,r16
l.mul r15,r15,r15
l.mul r1,r1,r1
l.mul r8,r25,r13
l.mul r8,r21,r29
l.mul r27,r3,r17
.text
l_mulu:
l.mulu r0,r0,r0
l.mulu r31,r31,r31
l.mulu r16,r16,r16
l.mulu r15,r15,r15
l.mulu r1,r1,r1
l.mulu r26,r14,r16
l.mulu r1,r18,r11
l.mulu r14,r18,r17
.text
l_div:
l.div r0,r0,r0
l.div r31,r31,r31
l.div r16,r16,r16
l.div r15,r15,r15
l.div r1,r1,r1
l.div r0,r2,r28
l.div r26,r7,r31
l.div r2,r18,r20
.text
l_divu:
l.divu r0,r0,r0
l.divu r31,r31,r31
l.divu r16,r16,r16
l.divu r15,r15,r15
l.divu r1,r1,r1
l.divu r5,r4,r25
l.divu r8,r11,r29
l.divu r11,r19,r2
.text
l_addi:
l.addi r0,r0,0
l.addi r31,r31,-1
l.addi r16,r16,-32768
l.addi r15,r15,32767
l.addi r1,r1,1
l.addi r14,r0,7020
l.addi r13,r14,14131
l.addi r14,r16,-26821
.text
l_andi:
l.andi r0,r0,0
l.andi r31,r31,-1
l.andi r16,r16,-32768
l.andi r15,r15,32767
l.andi r1,r1,1
l.andi r27,r21,11927
l.andi r21,r23,12059
l.andi r30,r30,-31804
.text
l_ori:
l.ori r0,r0,0
l.ori r31,r31,-1
l.ori r16,r16,-32768
l.ori r15,r15,32767
l.ori r1,r1,1
l.ori r22,r27,-10111
l.ori r17,r31,128
l.ori r13,r20,-12435
.text
l_xori:
l.xori r0,r0,0
l.xori r31,r31,-1
l.xori r16,r16,-32768
l.xori r15,r15,32767
l.xori r1,r1,1
l.xori r18,r16,65535
l.xori r25,r13,-16331
l.xori r12,r29,-32727
.text
l_muli:
l.muli r0,r0,0
l.muli r31,r31,-1
l.muli r16,r16,-32768
l.muli r15,r15,32767
l.muli r1,r1,1
l.muli r27,r7,-4731
l.muli r7,r20,65535
l.muli r24,r21,23219
.text
l_addic:
l.addic r0,r0,0
l.addic r31,r31,-1
l.addic r16,r16,-32768
l.addic r15,r15,32767
l.addic r1,r1,1
l.addic r6,r22,-32700
l.addic r19,r9,65535
l.addic r27,r28,6891
.text
l_sfgtu:
l.sfgtu r0,r0
l.sfgtu r31,r31
l.sfgtu r16,r16
l.sfgtu r15,r15
l.sfgtu r1,r1
l.sfgtu r8,r4
l.sfgtu r17,r21
l.sfgtu r6,r5
.text
l_sfgeu:
l.sfgeu r0,r0
l.sfgeu r31,r31
l.sfgeu r16,r16
l.sfgeu r15,r15
l.sfgeu r1,r1
l.sfgeu r14,r12
l.sfgeu r22,r7
l.sfgeu r13,r1
.text
l_sfltu:
l.sfltu r0,r0
l.sfltu r31,r31
l.sfltu r16,r16
l.sfltu r15,r15
l.sfltu r1,r1
l.sfltu r1,r13
l.sfltu r22,r30
l.sfltu r20,r6
.text
l_sfleu:
l.sfleu r0,r0
l.sfleu r31,r31
l.sfleu r16,r16
l.sfleu r15,r15
l.sfleu r1,r1
l.sfleu r19,r8
l.sfleu r27,r15
l.sfleu r27,r3
.text
l_sfgts:
l.sfgts r0,r0
l.sfgts r31,r31
l.sfgts r16,r16
l.sfgts r15,r15
l.sfgts r1,r1
l.sfgts r5,r5
l.sfgts r31,r5
l.sfgts r30,r18
.text
l_sfges:
l.sfges r0,r0
l.sfges r31,r31
l.sfges r16,r16
l.sfges r15,r15
l.sfges r1,r1
l.sfges r17,r18
l.sfges r0,r9
l.sfges r22,r25
.text
l_sflts:
l.sflts r0,r0
l.sflts r31,r31
l.sflts r16,r16
l.sflts r15,r15
l.sflts r1,r1
l.sflts r25,r24
l.sflts r23,r13
l.sflts r15,r8
.text
l_sfles:
l.sfles r0,r0
l.sfles r31,r31
l.sfles r16,r16
l.sfles r15,r15
l.sfles r1,r1
l.sfles r17,r13
l.sfles r30,r25
l.sfles r0,r12
.text
l_sfgtui:
l.sfgtui r0,0
l.sfgtui r31,65535
l.sfgtui r16,32768
l.sfgtui r15,32767
l.sfgtui r1,1
l.sfgtui r5,19233
l.sfgtui r23,37154
l.sfgtui r17,9693
.text
l_sfgeui:
l.sfgeui r0,0
l.sfgeui r31,65535
l.sfgeui r16,32768
l.sfgeui r15,32767
l.sfgeui r1,1
l.sfgeui r17,60598
l.sfgeui r15,16403
l.sfgeui r6,61860
.text
l_sfltui:
l.sfltui r0,0
l.sfltui r31,65535
l.sfltui r16,32768
l.sfltui r15,32767
l.sfltui r1,1
l.sfltui r3,52399
l.sfltui r24,19709
l.sfltui r10,830
.text
l_sfleui:
l.sfleui r0,0
l.sfleui r31,65535
l.sfleui r16,32768
l.sfleui r15,32767
l.sfleui r1,1
l.sfleui r23,39782
l.sfleui r17,46807
l.sfleui r9,43137
.text
l_sfgtsi:
l.sfgtsi r0,0
l.sfgtsi r31,-1
l.sfgtsi r16,-32768
l.sfgtsi r15,32767
l.sfgtsi r1,1
l.sfgtsi r13,-18814
l.sfgtsi r13,-10657
l.sfgtsi r28,-26667
.text
l_sfgesi:
l.sfgesi r0,0
l.sfgesi r31,-1
l.sfgesi r16,-32768
l.sfgesi r15,32767
l.sfgesi r1,1
l.sfgesi r12,2376
l.sfgesi r9,32059
l.sfgesi r13,20696
.text
l_sfltsi:
l.sfltsi r0,0
l.sfltsi r31,-1
l.sfltsi r16,-32768
l.sfltsi r15,32767
l.sfltsi r1,1
l.sfltsi r30,3021
l.sfltsi r5,-27813
l.sfltsi r28,-8816
.text
l_sflesi:
l.sflesi r0,0
l.sflesi r31,-1
l.sflesi r16,-32768
l.sflesi r15,32767
l.sflesi r1,1
l.sflesi r18,11338
l.sflesi r29,18873
l.sflesi r28,26050
.text
l_sfeq:
l.sfeq r0,r0
l.sfeq r31,r31
l.sfeq r16,r16
l.sfeq r15,r15
l.sfeq r1,r1
l.sfeq r28,r26
l.sfeq r13,r6
l.sfeq r26,r9
.text
l_sfeqi:
l.sfeqi r0,0
l.sfeqi r31,-1
l.sfeqi r16,-32768
l.sfeqi r15,32767
l.sfeqi r1,1
l.sfeqi r10,25887
l.sfeqi r21,19894
l.sfeqi r18,-13419
.text
l_sfne:
l.sfne r0,r0
l.sfne r31,r31
l.sfne r16,r16
l.sfne r15,r15
l.sfne r1,r1
l.sfne r18,r27
l.sfne r6,r18
l.sfne r0,r30
.text
l_sfnei:
l.sfnei r0,0
l.sfnei r31,-1
l.sfnei r16,-32768
l.sfnei r15,32767
l.sfnei r1,1
l.sfnei r8,11410
l.sfnei r6,-19239
l.sfnei r20,-22783
l_lo:
l.addi r1, r1, lo(0xdeadbeef)
l_hi:
l.movhi r1, hi(0xdeadbeef)
l_mac:
l.mac r1,r2
l_maci:
l.maci r1,0
l.maci r2,-1
l.maci r2,32767
l.maci r2,-32768

4
include/ChangeLog
View File

@ -1,3 +1,7 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* dis-asm.h: Remove openrisc and or32 support. Add support for or1k.
2014-04-10 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
* elf/avr.h: Add new DIFF relocs.

4
include/coff/ChangeLog
View File

@ -1,3 +1,7 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* or32.h: Delete.
2014-04-08 Jon TURNEY <jon.turney@dronecode.org.uk>
* pe.h (external_IMAGE_DEBUG_DIRECTORY, _CV_INFO_PDB70)

288
include/coff/or32.h
View File

@ -1,288 +0,0 @@
/* COFF specification for OpenRISC 1000.
Copyright (C) 1993-2014 Free Software Foundation, Inc.
Contributed by David Wood @ New York University.
Modified by Johan Rydberg, <johan.rydberg@netinsight.se>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef OR32
# define OR32
#endif
/* File Header and related definitions. */
struct external_filehdr
{
char f_magic[2]; /* magic number */
char f_nscns[2]; /* number of sections */
char f_timdat[4]; /* time & date stamp */
char f_symptr[4]; /* file pointer to symtab */
char f_nsyms[4]; /* number of symtab entries */
char f_opthdr[2]; /* sizeof(optional hdr) */
char f_flags[2]; /* flags */
};
#define FILHDR struct external_filehdr
#define FILHSZ 20
/* Magic numbers for OpenRISC 1000. As it is know we use the
numbers for Am29000.
(AT&T will assign the "real" magic number). */
#define SIPFBOMAGIC 0572 /* Am29000 (Byte 0 is MSB). */
#define SIPRBOMAGIC 0573 /* Am29000 (Byte 0 is LSB). */
#define OR32_MAGIC_BIG SIPFBOMAGIC
#define OR32_MAGIC_LITTLE SIPRBOMAGIC
#define OR32BADMAG(x) (((x).f_magic!=OR32_MAGIC_BIG) && \
((x).f_magic!=OR32_MAGIC_LITTLE))
#define OMAGIC OR32_MAGIC_BIG
/* Optional (a.out) header. */
typedef struct external_aouthdr
{
char magic[2]; /* type of file */
char vstamp[2]; /* version stamp */
char tsize[4]; /* text size in bytes, padded to FW bdry */
char dsize[4]; /* initialized data " " */
char bsize[4]; /* uninitialized data " " */
char entry[4]; /* entry pt. */
char text_start[4]; /* base of text used for this file */
char data_start[4]; /* base of data used for this file */
} AOUTHDR;
#define AOUTSZ 28
#define AOUTHDRSZ 28
/* aouthdr magic numbers. */
#define NMAGIC 0410 /* separate i/d executable. */
#define SHMAGIC 0406 /* NYU/Ultra3 shared data executable
(writable text). */
#define _ETEXT "_etext"
/* Section header and related definitions. */
struct external_scnhdr
{
char s_name[8]; /* section name */
char s_paddr[4]; /* physical address, aliased s_nlib */
char s_vaddr[4]; /* virtual address */
char s_size[4]; /* section size */
char s_scnptr[4]; /* file ptr to raw data for section */
char s_relptr[4]; /* file ptr to relocation */
char s_lnnoptr[4]; /* file ptr to line numbers */
char s_nreloc[2]; /* number of relocation entries */
char s_nlnno[2]; /* number of line number entries */
char s_flags[4]; /* flags */
};
#define SCNHDR struct external_scnhdr
#define SCNHSZ 40
/* Names of "special" sections: */
#define _TEXT ".text"
#define _DATA ".data"
#define _BSS ".bss"
#define _LIT ".lit"
/* Section types - with additional section type for global
registers which will be relocatable for the OpenRISC 1000.
In instances where it is necessary for a linker to produce an
output file which contains text or data not based at virtual
address 0, e.g. for a ROM, then the linker should accept
address base information as command input and use PAD sections
to skip over unused addresses. */
#define STYP_BSSREG 0x1200 /* Global register area (like STYP_INFO) */
#define STYP_ENVIR 0x2200 /* Environment (like STYP_INFO) */
#define STYP_ABS 0x4000 /* Absolute (allocated, not reloc, loaded) */
/* Relocation information declaration and related definitions: */
struct external_reloc
{
char r_vaddr[4]; /* (virtual) address of reference */
char r_symndx[4]; /* index into symbol table */
char r_type[2]; /* relocation type */
};
#define RELOC struct external_reloc
#define RELSZ 10 /* sizeof (RELOC) */
/* Relocation types for the OpenRISC 1000: */
#define R_ABS 0 /* reference is absolute */
#define R_IREL 030 /* instruction relative (jmp/call) */
#define R_IABS 031 /* instruction absolute (jmp/call) */
#define R_ILOHALF 032 /* instruction low half (const) */
#define R_IHIHALF 033 /* instruction high half (consth) part 1 */
#define R_IHCONST 034 /* instruction high half (consth) part 2 */
/* constant offset of R_IHIHALF relocation */
#define R_BYTE 035 /* relocatable byte value */
#define R_HWORD 036 /* relocatable halfword value */
#define R_WORD 037 /* relocatable word value */
#define R_IGLBLRC 040 /* instruction global register RC */
#define R_IGLBLRA 041 /* instruction global register RA */
#define R_IGLBLRB 042 /* instruction global register RB */
/*
NOTE:
All the "I" forms refer to 29000 instruction formats. The linker is
expected to know how the numeric information is split and/or aligned
within the instruction word(s). R_BYTE works for instructions, too.
If the parameter to a CONSTH instruction is a relocatable type, two
relocation records are written. The first has an r_type of R_IHIHALF
(33 octal) and a normal r_vaddr and r_symndx. The second relocation
record has an r_type of R_IHCONST (34 octal), a normal r_vaddr (which
is redundant), and an r_symndx containing the 32-bit constant offset
to the relocation instead of the actual symbol table index. This
second record is always written, even if the constant offset is zero.
The constant fields of the instruction are set to zero. */
/* Line number entry declaration and related definitions: */
struct external_lineno
{
union
{
char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/
char l_paddr[4]; /* (physical) address of line number */
}
l_addr;
char l_lnno[2]; /* line number */
};
#define LINENO struct external_lineno
#define LINESZ 6 /* sizeof (LINENO) */
/* Symbol entry declaration and related definitions: */
#define E_SYMNMLEN 8 /* Number of characters in a symbol name */
struct external_syment
{
union
{
char e_name[E_SYMNMLEN];
struct
{
char e_zeroes[4];
char e_offset[4];
}
e;
}
e;
char e_value[4];
char e_scnum[2];
char e_type[2];
char e_sclass[1];
char e_numaux[1];
};
#define SYMENT struct external_syment
#define SYMESZ 18
/* Storage class definitions - new classes for global registers: */
#define C_GLBLREG 19 /* global register */
#define C_EXTREG 20 /* external global register */
#define C_DEFREG 21 /* ext. def. of global register */
/* Derived symbol mask/shifts: */
#define N_BTMASK (0xf)
#define N_BTSHFT (4)
#define N_TMASK (0x30)
#define N_TSHIFT (2)
/* Auxiliary symbol table entry declaration and related
definitions. */
#define E_FILNMLEN 14 /* # characters in a file name */
#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */
union external_auxent
{
struct
{
char x_tagndx[4]; /* str, un, or enum tag indx */
union
{
struct
{
char x_lnno[2]; /* declaration line number */
char x_size[2]; /* str/union/array size */
}
x_lnsz;
char x_fsize[4]; /* size of function */
}
x_misc;
union
{
struct /* if ISFCN, tag, or .bb */
{
char x_lnnoptr[4]; /* ptr to fcn line # */
char x_endndx[4]; /* entry ndx past block end */
}
x_fcn;
struct /* if ISARY, up to 4 dimen. */
{
char x_dimen[E_DIMNUM][2];
}
x_ary;
}
x_fcnary;
char x_tvndx[2]; /* tv index */
}
x_sym;
union
{
char x_fname[E_FILNMLEN];
struct
{
char x_zeroes[4];
char x_offset[4];
}
x_n;
}
x_file;
struct
{
char x_scnlen[4]; /* section length */
char x_nreloc[2]; /* # relocation entries */
char x_nlinno[2]; /* # line numbers */
}
x_scn;
struct
{
char x_tvfill[4]; /* tv fill value */
char x_tvlen[2]; /* length of .tv */
char x_tvran[2][2]; /* tv range */
}
x_tv; /* info about .tv section
(in auxent of symbol .tv)) */
};
#define AUXENT union external_auxent
#define AUXESZ 18

4
include/dis-asm.h
View File

@ -226,7 +226,6 @@ extern int print_insn_bfin (bfd_vma, disassemble_info *);
extern int print_insn_big_arm (bfd_vma, disassemble_info *);
extern int print_insn_big_mips (bfd_vma, disassemble_info *);
extern int print_insn_big_nios2 (bfd_vma, disassemble_info *);
extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
extern int print_insn_big_powerpc (bfd_vma, disassemble_info *);
extern int print_insn_big_score (bfd_vma, disassemble_info *);
extern int print_insn_cr16 (bfd_vma, disassemble_info *);
@ -254,7 +253,6 @@ extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
extern int print_insn_little_arm (bfd_vma, disassemble_info *);
extern int print_insn_little_mips (bfd_vma, disassemble_info *);
extern int print_insn_little_nios2 (bfd_vma, disassemble_info *);
extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
extern int print_insn_little_score (bfd_vma, disassemble_info *);
extern int print_insn_lm32 (bfd_vma, disassemble_info *);
@ -278,7 +276,7 @@ extern int print_insn_msp430 (bfd_vma, disassemble_info *);
extern int print_insn_mt (bfd_vma, disassemble_info *);
extern int print_insn_nds32 (bfd_vma, disassemble_info *);
extern int print_insn_ns32k (bfd_vma, disassemble_info *);
extern int print_insn_openrisc (bfd_vma, disassemble_info *);
extern int print_insn_or1k (bfd_vma, disassemble_info *);
extern int print_insn_pdp11 (bfd_vma, disassemble_info *);
extern int print_insn_pj (bfd_vma, disassemble_info *);
extern int print_insn_rs6000 (bfd_vma, disassemble_info *);

7
include/elf/ChangeLog
View File

@ -1,3 +1,10 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* common.h: Remove openrisc and or32 support. Add support for or1k.
* or1k.h: New file.
* openrisc.h: Delete.
* or32.h: Delete.
2014-03-05 Alan Modra <amodra@gmail.com>
Update copyright years.

11
include/elf/common.h
View File

@ -192,7 +192,7 @@
#define EM_MN10300 89 /* Matsushita MN10300 */
#define EM_MN10200 90 /* Matsushita MN10200 */
#define EM_PJ 91 /* picoJava */
#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
#define EM_OR1K 92 /* OpenRISC 1000 32-bit embedded processor */
#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */
#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */
#define EM_VIDEOCORE 95 /* Alphamosaic VideoCore processor */
@ -339,9 +339,6 @@
/* FR30 magic number - no EABI available. */
#define EM_CYGNUS_FR30 0x3330
/* OpenRISC magic number. Written in the absense of an ABI. */
#define EM_OPENRISC_OLD 0x3426
/* DLX magic number. Written in the absense of an ABI. */
#define EM_DLX 0x5aa5
@ -360,9 +357,6 @@
/* Ubicom IP2xxx; Written in the absense of an ABI. */
#define EM_IP2K_OLD 0x8217
/* (Deprecated) Temporary number for the OpenRISC processor. */
#define EM_OR32 0x8472
/* Cygnus PowerPC ELF backend. Written in the absence of an ABI. */
#define EM_CYGNUS_POWERPC 0x9025
@ -408,6 +402,9 @@
#define EM_ADAPTEVA_EPIPHANY 0x1223 /* Adapteva's Epiphany architecture. */
/* Old constant that might be in use by some software. */
#define EM_OPENRISC EM_OR1K
/* See the above comment before you add a new EM_* value here. */
/* Values for e_version. */

39
include/elf/openrisc.h
View File

@ -1,39 +0,0 @@
/* OpenRISC ELF support for BFD.
Copyright (C) 2001-2014 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef _ELF_OPENRISC_H
#define _ELF_OPENRISC_H
#include "elf/reloc-macros.h"
/* Relocations. */
START_RELOC_NUMBERS (elf_openrisc_reloc_type)
RELOC_NUMBER (R_OPENRISC_NONE, 0)
RELOC_NUMBER (R_OPENRISC_INSN_REL_26, 1)
RELOC_NUMBER (R_OPENRISC_INSN_ABS_26, 2)
RELOC_NUMBER (R_OPENRISC_LO_16_IN_INSN, 3)
RELOC_NUMBER (R_OPENRISC_HI_16_IN_INSN, 4)
RELOC_NUMBER (R_OPENRISC_8, 5)
RELOC_NUMBER (R_OPENRISC_16, 6)
RELOC_NUMBER (R_OPENRISC_32, 7)
RELOC_NUMBER (R_OPENRISC_GNU_VTINHERIT, 8)
RELOC_NUMBER (R_OPENRISC_GNU_VTENTRY, 9)
END_RELOC_NUMBERS (R_OPENRISC_max)
#endif /* _ELF_OPENRISC_H */

65
include/elf/or1k.h Normal file
View File

@ -0,0 +1,65 @@
/* Or1k ELF support for BFD.
Copyright 2001-2014 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/> */
#ifndef _ELF_OR1K_H
#define _ELF_OR1K_H
#include "elf/reloc-macros.h"
/* Relocations. */
START_RELOC_NUMBERS (elf_or1k_reloc_type)
RELOC_NUMBER (R_OR1K_NONE, 0)
RELOC_NUMBER (R_OR1K_32, 1)
RELOC_NUMBER (R_OR1K_16, 2)
RELOC_NUMBER (R_OR1K_8, 3)
RELOC_NUMBER (R_OR1K_LO_16_IN_INSN, 4)
RELOC_NUMBER (R_OR1K_HI_16_IN_INSN, 5)
RELOC_NUMBER (R_OR1K_INSN_REL_26, 6)
RELOC_NUMBER (R_OR1K_GNU_VTENTRY, 7)
RELOC_NUMBER (R_OR1K_GNU_VTINHERIT, 8)
RELOC_NUMBER (R_OR1K_32_PCREL, 9)
RELOC_NUMBER (R_OR1K_16_PCREL, 10)
RELOC_NUMBER (R_OR1K_8_PCREL, 11)
RELOC_NUMBER (R_OR1K_GOTPC_HI16, 12)
RELOC_NUMBER (R_OR1K_GOTPC_LO16, 13)
RELOC_NUMBER (R_OR1K_GOT16, 14)
RELOC_NUMBER (R_OR1K_PLT26, 15)
RELOC_NUMBER (R_OR1K_GOTOFF_HI16, 16)
RELOC_NUMBER (R_OR1K_GOTOFF_LO16, 17)
RELOC_NUMBER (R_OR1K_COPY, 18)
RELOC_NUMBER (R_OR1K_GLOB_DAT, 19)
RELOC_NUMBER (R_OR1K_JMP_SLOT, 20)
RELOC_NUMBER (R_OR1K_RELATIVE, 21)
RELOC_NUMBER (R_OR1K_TLS_GD_HI16, 22)
RELOC_NUMBER (R_OR1K_TLS_GD_LO16, 23)
RELOC_NUMBER (R_OR1K_TLS_LDM_HI16, 24)
RELOC_NUMBER (R_OR1K_TLS_LDM_LO16, 25)
RELOC_NUMBER (R_OR1K_TLS_LDO_HI16, 26)
RELOC_NUMBER (R_OR1K_TLS_LDO_LO16, 27)
RELOC_NUMBER (R_OR1K_TLS_IE_HI16, 28)
RELOC_NUMBER (R_OR1K_TLS_IE_LO16, 29)
RELOC_NUMBER (R_OR1K_TLS_LE_HI16, 30)
RELOC_NUMBER (R_OR1K_TLS_LE_LO16, 31)
RELOC_NUMBER (R_OR1K_TLS_TPOFF, 32)
RELOC_NUMBER (R_OR1K_TLS_DTPOFF, 33)
RELOC_NUMBER (R_OR1K_TLS_DTPMOD, 34)
END_RELOC_NUMBERS (R_OR1K_max)
#define EF_OR1K_NODELAY (1UL << 0)
#endif /* _ELF_OR1K_H */

56
include/elf/or32.h
View File

@ -1,56 +0,0 @@
/* OR1K ELF support for BFD. Derived from ppc.h.
Copyright (C) 2002-2014 Free Software Foundation, Inc.
Contributed by Ivan Guzvinec <ivang@opencores.org>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef _ELF_OR1K_H
#define _ELF_OR1K_H
#include "elf/reloc-macros.h"
/* Relocations. */
START_RELOC_NUMBERS (elf_or32_reloc_type)
RELOC_NUMBER (R_OR32_NONE, 0)
RELOC_NUMBER (R_OR32_32, 1)
RELOC_NUMBER (R_OR32_16, 2)
RELOC_NUMBER (R_OR32_8, 3)
RELOC_NUMBER (R_OR32_CONST, 4)
RELOC_NUMBER (R_OR32_CONSTH, 5)
RELOC_NUMBER (R_OR32_JUMPTARG, 6)
RELOC_NUMBER (R_OR32_GNU_VTENTRY, 7)
RELOC_NUMBER (R_OR32_GNU_VTINHERIT, 8)
END_RELOC_NUMBERS (R_OR32_max)
/* Four bit OR32 machine type field. */
#define EF_OR32_MACH 0x0000000f
/* Various CPU types. */
#define E_OR32_MACH_BASE 0x00000000
#define E_OR32_MACH_UNUSED1 0x00000001
#define E_OR32_MACH_UNUSED2 0x00000002
#define E_OR32_MACH_UNUSED4 0x00000003
/* Processor specific section headers, sh_type field */
#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \
entries in this section \
based on the address \
specified in the associated \
symbol table entry. */
#endif /* _ELF_OR1K_H */

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* or32.h: Delete.
2014-03-05 Alan Modra <amodra@gmail.com>
Update copyright years.

181
include/opcode/or32.h
View File

@ -1,181 +0,0 @@
/* Table of opcodes for the OpenRISC 1000 ISA.
Copyright (C) 2002-2014 Free Software Foundation, Inc.
Contributed by Damjan Lampret (lampret@opencores.org).
This file is part of or1k_gen_isa, or1ksim, GDB and GAS.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* We treat all letters the same in encode/decode routines so
we need to assign some characteristics to them like signess etc. */
#ifndef OR32_H_ISA
#define OR32_H_ISA
#define NUM_UNSIGNED (0)
#define NUM_SIGNED (1)
#define MAX_GPRS 32
#define PAGE_SIZE 4096
#undef __HALF_WORD_INSN__
#define OPERAND_DELIM (',')
#define OR32_IF_DELAY (1)
#define OR32_W_FLAG (2)
#define OR32_R_FLAG (4)
struct or32_letter
{
char letter;
int sign;
/* int reloc; relocation per letter ?? */
};
/* Main instruction specification array. */
struct or32_opcode
{
/* Name of the instruction. */
char *name;
/* A string of characters which describe the operands.
Valid characters are:
,() Itself. Characters appears in the assembly code.
rA Register operand.
rB Register operand.
rD Register operand.
I An immediate operand, range -32768 to 32767.
J An immediate operand, range . (unused)
K An immediate operand, range 0 to 65535.
L An immediate operand, range 0 to 63.
M An immediate operand, range . (unused)
N An immediate operand, range -33554432 to 33554431.
O An immediate operand, range . (unused). */
char *args;
/* Opcode and operand encoding. */
char *encoding;
void (*exec) (void);
unsigned int flags;
};
#define OPTYPE_LAST (0x80000000)
#define OPTYPE_OP (0x40000000)
#define OPTYPE_REG (0x20000000)
#define OPTYPE_SIG (0x10000000)
#define OPTYPE_DIS (0x08000000)
#define OPTYPE_DST (0x04000000)
#define OPTYPE_SBIT (0x00001F00)
#define OPTYPE_SHR (0x0000001F)
#define OPTYPE_SBIT_SHR (8)
/* MM: Data how to decode operands. */
extern struct insn_op_struct
{
unsigned long type;
unsigned long data;
} **op_start;
#ifdef HAS_EXECUTION
extern void l_invalid (void);
extern void l_sfne (void);
extern void l_bf (void);
extern void l_add (void);
extern void l_sw (void);
extern void l_sb (void);
extern void l_sh (void);
extern void l_lwz (void);
extern void l_lbs (void);
extern void l_lbz (void);
extern void l_lhs (void);
extern void l_lhz (void);
extern void l_movhi (void);
extern void l_and (void);
extern void l_or (void);
extern void l_xor (void);
extern void l_sub (void);
extern void l_mul (void);
extern void l_div (void);
extern void l_divu (void);
extern void l_sll (void);
extern void l_sra (void);
extern void l_srl (void);
extern void l_j (void);
extern void l_jal (void);
extern void l_jalr (void);
extern void l_jr (void);
extern void l_rfe (void);
extern void l_nop (void);
extern void l_bnf (void);
extern void l_sfeq (void);
extern void l_sfgts (void);
extern void l_sfges (void);
extern void l_sflts (void);
extern void l_sfles (void);
extern void l_sfgtu (void);
extern void l_sfgeu (void);
extern void l_sfltu (void);
extern void l_sfleu (void);
extern void l_mtspr (void);
extern void l_mfspr (void);
extern void l_sys (void);
extern void l_trap (void); /* CZ 21/06/01. */
extern void l_macrc (void);
extern void l_mac (void);
extern void l_msb (void);
extern void l_invalid (void);
extern void l_cust1 (void);
extern void l_cust2 (void);
extern void l_cust3 (void);
extern void l_cust4 (void);
#endif
extern void l_none (void);
extern const struct or32_letter or32_letters[];
extern const struct or32_opcode or32_opcodes[];
extern const unsigned int or32_num_opcodes;
/* Calculates instruction length in bytes. Always 4 for OR32. */
extern int insn_len (int);
/* Is individual insn's operand signed or unsigned? */
extern int letter_signed (char);
/* Number of letters in the individual lettered operand. */
extern int letter_range (char);
/* MM: Returns index of given instruction name. */
extern int insn_index (char *);
/* MM: Returns instruction name from index. */
extern const char *insn_name (int);
/* MM: Constructs new FSM, based on or32_opcodes. */
extern void build_automata (void);
/* MM: Destructs FSM. */
extern void destruct_automata (void);
/* MM: Decodes instruction using FSM. Call build_automata first. */
extern int insn_decode (unsigned int);
/* Disassemble one instruction from insn to disassemble.
Return the size of the instruction. */
int disassemble_insn (unsigned long);
#endif

12
ld/ChangeLog
View File

@ -1,3 +1,15 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* Makefile.am: Remove openrisc and or32 support. Add support for or1k.
* configure.tgt: Likewise.
* emulparams/elf32or1k.sh: New file.
* emulparams/elf32or1k_linux.sh: New file.
* emulparams/elf32openrisc.sh: Delete.
* emulparams/or32.sh: Delete.
* emulparams/or32elf.sh: Delete.
* scripttempl/or32.sc: Delete.
* Makefile.in: Regenerate.
2014-04-21 Richard Henderson <rth@redhat.com>
* emultempl/alphaelf.em (alpha_after_parse): Enable 2 relax passes.

20
ld/Makefile.am
View File

@ -245,7 +245,8 @@ ALL_EMULATION_SOURCES = \
eelf32microblaze.c \
eelf32moxie.c \
eelf32mt.c \
eelf32openrisc.c \
eelf32or1k.c \
eelf32or1k_linux.c \
eelf32ppc.c \
eelf32ppc_fbsd.c \
eelf32ppclinux.c \
@ -348,8 +349,6 @@ ALL_EMULATION_SOURCES = \
ends32belf_linux.c \
enews.c \
ens32knbsd.c \
eor32.c \
eor32elf.c \
epc532macha.c \
epdp11.c \
epjelf.c \
@ -1134,9 +1133,12 @@ eelf32moxie.c: $(srcdir)/emulparams/elf32moxie.sh \
eelf32mt.c: $(srcdir)/emulparams/elf32mt.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32mt "$(tdir_mt)"
eelf32openrisc.c: $(srcdir)/emulparams/elf32openrisc.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32openrisc "$(tdir_openrisc)"
eelf32or1k.c: $(srcdir)/emulparams/elf32or1k.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32or1k "$(tdir_elf32or1k)"
eelf32or1k_linux.c: $(srcdir)/emulparams/elf32or1k_linux.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32or1k_linux "$(tdir_elf32or1k_linux)"
eelf32ppc.c: $(srcdir)/emulparams/elf32ppc.sh \
$(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emultempl/ppc32elf.em \
ldemul-list.h \
@ -1542,12 +1544,6 @@ eaarch64linux32b.c: $(srcdir)/emulparams/aarch64linux32b.sh $(srcdir)/emulparams
$(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} aarch64linux32b "$(tdir_aarch64linux32b)"
eor32.c: $(srcdir)/emulparams/or32.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/or32.sc ${GEN_DEPENDS}
${GENSCRIPTS} or32 "$(tdir_or32)"
eor32elf.c: $(srcdir)/emulparams/or32elf.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} or32elf "$(tdir_or32elf)"
epc532macha.c: $(srcdir)/emulparams/pc532macha.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} pc532macha "$(tdir_pc532macha)"

25
ld/Makefile.in
View File

@ -552,7 +552,8 @@ ALL_EMULATION_SOURCES = \
eelf32microblaze.c \
eelf32moxie.c \
eelf32mt.c \
eelf32openrisc.c \
eelf32or1k.c \
eelf32or1k_linux.c \
eelf32ppc.c \
eelf32ppc_fbsd.c \
eelf32ppclinux.c \
@ -655,8 +656,6 @@ ALL_EMULATION_SOURCES = \
ends32belf_linux.c \
enews.c \
ens32knbsd.c \
eor32.c \
eor32elf.c \
epc532macha.c \
epdp11.c \
epjelf.c \
@ -1164,7 +1163,8 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mipswindiss.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32moxie.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mt.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32openrisc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32or1k.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32or1k_linux.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppc_fbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppclinux.Po@am__quote@
@ -1301,8 +1301,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32elf_linux.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/enews.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ens32knbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eor32.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eor32elf.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epc532macha.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epdp11.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epjelf.Po@am__quote@
@ -2569,9 +2567,12 @@ eelf32moxie.c: $(srcdir)/emulparams/elf32moxie.sh \
eelf32mt.c: $(srcdir)/emulparams/elf32mt.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32mt "$(tdir_mt)"
eelf32openrisc.c: $(srcdir)/emulparams/elf32openrisc.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32openrisc "$(tdir_openrisc)"
eelf32or1k.c: $(srcdir)/emulparams/elf32or1k.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32or1k "$(tdir_elf32or1k)"
eelf32or1k_linux.c: $(srcdir)/emulparams/elf32or1k_linux.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32or1k_linux "$(tdir_elf32or1k_linux)"
eelf32ppc.c: $(srcdir)/emulparams/elf32ppc.sh \
$(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emultempl/ppc32elf.em \
ldemul-list.h \
@ -2977,12 +2978,6 @@ eaarch64linux32b.c: $(srcdir)/emulparams/aarch64linux32b.sh $(srcdir)/emulparams
$(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} aarch64linux32b "$(tdir_aarch64linux32b)"
eor32.c: $(srcdir)/emulparams/or32.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/or32.sc ${GEN_DEPENDS}
${GENSCRIPTS} or32 "$(tdir_or32)"
eor32elf.c: $(srcdir)/emulparams/or32elf.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} or32elf "$(tdir_or32elf)"
epc532macha.c: $(srcdir)/emulparams/pc532macha.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} pc532macha "$(tdir_pc532macha)"

2
ld/NEWS
View File

@ -1,5 +1,7 @@
-*- text -*-
* Replace support for openrisc and or32 with support for or1k.
* Add support for the --build-id command line option to COFF based targets.
* x86/x86_64 pe-coff now supports the --build-id option.

7
ld/configure.tgt
View File

@ -527,10 +527,9 @@ nios2*-*-*) targ_emul=nios2elf ;;
ns32k-pc532-mach* | ns32k-pc532-ux*) targ_emul=pc532macha ;;
ns32k-*-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd
;;
openrisc-*-*) targ_emul=elf32openrisc ;;
or32-*-coff) targ_emul=or32 ;;
or32-*-elf) targ_emul=or32elf ;;
or32-*-rtems*) targ_emul=or32elf
or1k-*-elf | or1knd-*-elf) targ_emul=elf32or1k ;;
or1k-*-linux* | or1knd-*-linux*) targ_emul=elf32or1k_linux ;;
or1k-*-rtems* | or1knd-*-rtems*) targ_emul=elf32or1k
;;
pdp11-*-*) targ_emul=pdp11
;;

11
ld/emulparams/elf32openrisc.sh
View File

@ -1,11 +0,0 @@
MACHINE=
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf32-openrisc"
NO_RELA_RELOCS=yes
TEXT_START_ADDR=0x10000
ARCH=openrisc
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
ENTRY=_start
EMBEDDED=yes
NOP=0x15000000

14
ld/emulparams/elf32or1k.sh Normal file
View File

@ -0,0 +1,14 @@
SCRIPT_NAME=elf
MACHINE=
TEMPLATE_NAME=elf32
OUTPUT_FORMAT="elf32-or1k"
NOP=0x15000000
TEXT_START_ADDR=0x0000
TARGET_PAGE_SIZE=0x2000
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
EMBEDDED=yes
ARCH=or1k
ELFSIZE=32
INITIAL_READONLY_SECTIONS=".vectors ${RELOCATING-0} : { KEEP (*(.vectors)) }"
NO_REL_RELOCS=yes
COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"

5
ld/emulparams/elf32or1k_linux.sh Normal file
View File

@ -0,0 +1,5 @@
. ${srcdir}/emulparams/elf32or1k.sh
unset EMBEDDED
GENERATE_SHLIB_SCRIPT=yes
GENERATE_PIE_SCRIPT=yes
GENERATE_COMBRELOC_SCRIPT=yes

5
ld/emulparams/or32.sh
View File

@ -1,5 +0,0 @@
SCRIPT_NAME=or32
OUTPUT_FORMAT="coff-or32-big"
TEXT_START_ADDR=0x1000000
TARGET_PAGE_SIZE=0x1000000
ARCH=or32

9
ld/emulparams/or32elf.sh
View File

@ -1,9 +0,0 @@
SCRIPT_NAME=elf
TEMPLATE_NAME=generic
EXTRA_EM_FILE=genelf
OUTPUT_FORMAT="elf32-or32"
NO_RELA_RELOCS=yes
TEXT_START_ADDR=0x1000000
TARGET_PAGE_SIZE=0x1000000
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
ARCH=or32

37
ld/scripttempl/or32.sc
View File

@ -1,37 +0,0 @@
cat <<EOF
OUTPUT_FORMAT("${OUTPUT_FORMAT}")
${LIB_SEARCH_DIRS}
SECTIONS
{
.text : {
*(.text)
${RELOCATING+ __etext = .};
${CONSTRUCTING+ __CTOR_LIST__ = .;}
${CONSTRUCTING+ LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)}
${CONSTRUCTING+ *(.ctors)}
${CONSTRUCTING+ LONG(0)}
${CONSTRUCTING+ __CTOR_END__ = .;}
${CONSTRUCTING+ __DTOR_LIST__ = .;}
${CONSTRUCTING+ LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)}
${CONSTRUCTING+ *(.dtors)}
${CONSTRUCTING+ LONG(0)}
${CONSTRUCTING+ __DTOR_END__ = .;}
*(.lit)
*(.shdata)
}
.shbss SIZEOF(.text) + ADDR(.text) : {
*(.shbss)
}
.data : {
*(.data)
${RELOCATING+ __edata = .};
}
.bss SIZEOF(.data) + ADDR(.data) :
{
*(.bss)
*(COMMON)
${RELOCATING+ __end = ALIGN(0x8)};
}
}
EOF

30
ld/testsuite/ChangeLog
View File

@ -1,3 +1,33 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* ld-discard/extern.d: Remove openrisc and or32 support. Add
support for or1k.
* ld-discard/start.d: Likewise.
* ld-discard/static.d: Likewise.
* ld-elf/group1.d: Likewise.
* ld-elf/group3b.d: Likewise.
* ld-elf/group8a.d: Likewise.
* ld-elf/group8b.d: Likewise.
* ld-elf/group9a.d: Likewise.
* ld-elf/group9b.d: Likewise.
* ld-elf/linkonce2.d: Likewise.
* ld-elf/merge.d: Likewise.
* ld-elf/merge2.d: Likewise.
* ld-elf/orphan-region.d: Likewise.
* ld-elf/orphan.d: Likewise.
* ld-elf/orphan3.d: Likewise.
* ld-elf/pr12851.d: Likewise.
* ld-elf/pr12975.d: Likewise.
* ld-elf/pr13177.d: Likewise.
* ld-elf/pr13195.d: Likewise.
* ld-elf/pr349.d: Likewise.
* ld-elf/sec64k.exp: Likewise.
* ld-elf/warn1.d: Likewise.
* ld-elf/warn2.d: Likewise.
* ld-elf/warn3.d: Likewise.
* ld-scripts/weak.exp: Likewise.
* lib/ld-lib.exp: Likewise.
2014-04-17 Kwok Cheung Yeung <kcy@codesourcery.com>
* ld-mips-elf/elf-rel-xgot-n32.d: Update for new GOT layout.

2
ld/testsuite/ld-discard/extern.d
View File

@ -2,7 +2,7 @@
#ld: -T discard.ld
#error: .*data.* referenced in section `\.text' of tmpdir/dump0.o: defined in discarded section `\.data\.exit' of tmpdir/dump0.o
#objdump: -p
#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-*
#xfail: m68hc12-*-* m6812-*-*
#pass
# The expected warning used to start with "`data' referenced..." but

2
ld/testsuite/ld-discard/start.d
View File

@ -3,6 +3,6 @@
#ld: -T discard.ld
#error: `data' referenced in section `\.text' of tmpdir/dump0.o: defined in discarded section `\.data\.exit' of tmpdir/dump1.o
#objdump: -p
#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-*
#xfail: m68hc12-*-* m6812-*-*
#pass

2
ld/testsuite/ld-discard/static.d
View File

@ -2,6 +2,6 @@
#ld: -T discard.ld
#error: `(\.data\.exit|data)' referenced in section `\.text' of tmpdir/dump0.o: defined in discarded section `\.data\.exit' of tmpdir/dump0.o
#objdump: -p
#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-*
#xfail: m68hc12-*-* m6812-*-*
#pass

2
ld/testsuite/ld-elf/eh-frame-hdr.d
View File

@ -2,7 +2,7 @@
#ld: -e _start --eh-frame-hdr
#objdump: -hw
#target: cfi
#xfail: avr*-*-*
#xfail: avr*-*-* or1k-*-*
# avr doesn't support shared libraries.
#...
[0-9] .eh_frame_hdr 0*[12][048c] .*

2
ld/testsuite/ld-elf/group1.d
View File

@ -2,7 +2,7 @@
#source: group1b.s
#ld: -T group.ld
#readelf: -s
#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-*
# generic linker targets don't comply with all symbol merging rules
Symbol table '.symtab' contains .* entries:

2
ld/testsuite/ld-elf/group3b.d
View File

@ -2,7 +2,7 @@
#source: group3a.s
#ld: -T group.ld
#readelf: -s
#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-*
# generic linker targets don't comply with all symbol merging rules
Symbol table '.symtab' contains .* entries:

2
ld/testsuite/ld-elf/group8a.d
View File

@ -1,7 +1,7 @@
#source: group8.s
#ld: -r --gc-sections --entry foo
#readelf: -g --wide
#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others

2
ld/testsuite/ld-elf/group8b.d
View File

@ -1,7 +1,7 @@
#source: group8.s
#ld: -r --gc-sections --entry bar
#readelf: -g --wide
#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-*
#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others

2
ld/testsuite/ld-elf/group9a.d
View File

@ -1,7 +1,7 @@
#source: group9.s
#ld: -r --gc-sections --entry foo
#readelf: -g --wide
#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-*
#notarget: alpha-*-* hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others

2
ld/testsuite/ld-elf/group9b.d
View File

@ -1,7 +1,7 @@
#source: group9.s
#ld: -r --gc-sections --entry bar
#readelf: -g --wide
#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-*
#notarget: alpha-*-* hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others

2
ld/testsuite/ld-elf/linkonce2.d
View File

@ -2,7 +2,7 @@
#source: linkonce1b.s
#ld: -emit-relocs
#objdump: -r
#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-*
#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-*
# generic elf targets don't emit relocs
.*: file format .*

Some files were not shown because too many files have changed in this diff Show More