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AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension.

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This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV
instructions. These instructions needed special infrastructure to support
[base]! style for addressing mode. That is also removed now.

Committed on behalf of Sudakshina Das.

*** gas/ChangeLog ***

	* config/tc-aarch64.c (parse_address_main): Remove support for
	[base]! address expression.
	(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
	(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
	and stgv.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** include/ChangeLog ***

	* opcode/aarch64.h (enum aarch64_opnd): Remove
	AARCH64_OPND_ADDR_SIMPLE_2.
	(enum aarch64_insn_class): Remove ldstgv_indexed.

*** opcodes/ChangeLog ***

	* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
	* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
	* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
	* aarch64-dis.h (ext_addr_simple_2): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Remove
	case for ldstgv_indexed.
	(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
	* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
	(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
This commit is contained in:
Sudi Das 2019-01-25 13:57:14 +00:00 committed by Tamar Christina
parent 183445093e
commit 550fd7bf68
18 changed files with 1675 additions and 1764 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
gas/ChangeLog
View File

@ -1,3 +1,16 @@
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/tc-aarch64.c (parse_address_main): Remove support for
[base]! address expression.
(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
2019-01-25 Wu Heng <wu.heng@zte.com.cn> 2019-01-25 Wu Heng <wu.heng@zte.com.cn>
PR gas/23940 PR gas/23940

19
gas/config/tc-aarch64.c
View File

@ -3381,7 +3381,6 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
[base,Wm,(S|U)XTW {#imm}] [base,Wm,(S|U)XTW {#imm}]
Pre-indexed Pre-indexed
[base,#imm]! [base,#imm]!
[base]! // in ld/stgv
Post-indexed Post-indexed
[base],#imm [base],#imm
[base],Xm // in SIMD ld/st structure [base],Xm // in SIMD ld/st structure
@ -3690,11 +3689,10 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
} }
/* If at this point neither .preind nor .postind is set, we have a /* If at this point neither .preind nor .postind is set, we have a
bare [Rn]{!}; reject [Rn]! except for ld/stgv but accept [Rn] bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0]. */
as a shorthand for [Rn,#0]. */
if (operand->addr.preind == 0 && operand->addr.postind == 0) if (operand->addr.preind == 0 && operand->addr.postind == 0)
{ {
if (operand->type != AARCH64_OPND_ADDR_SIMPLE_2 && operand->addr.writeback) if (operand->addr.writeback)
{ {
/* Reject [Rn]! */ /* Reject [Rn]! */
set_syntax_error (_("missing offset in the pre-indexed address")); set_syntax_error (_("missing offset in the pre-indexed address"));
@ -6148,7 +6146,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break; break;
case AARCH64_OPND_ADDR_SIMPLE: case AARCH64_OPND_ADDR_SIMPLE:
case AARCH64_OPND_ADDR_SIMPLE_2:
case AARCH64_OPND_SIMD_ADDR_SIMPLE: case AARCH64_OPND_SIMD_ADDR_SIMPLE:
{ {
/* [<Xn|SP>{, #<simm>}] */ /* [<Xn|SP>{, #<simm>}] */
@ -6158,8 +6155,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
po_misc_or_fail (parse_address (&str, info)); po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg if (info->addr.pcrel || info->addr.offset.is_reg
|| !info->addr.preind || info->addr.postind || !info->addr.preind || info->addr.postind
|| (info->addr.writeback || info->addr.writeback)
&& operands[i] != AARCH64_OPND_ADDR_SIMPLE_2))
{ {
set_syntax_error (_("invalid addressing mode")); set_syntax_error (_("invalid addressing mode"));
goto failure; goto failure;
@ -6182,8 +6178,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
} }
} }
po_char_or_fail (']'); po_char_or_fail (']');
if (operands[i] == AARCH64_OPND_ADDR_SIMPLE_2)
po_char_or_fail ('!');
break; break;
} }
@ -6782,13 +6776,6 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
as_warn (_("unpredictable transfer with writeback -- `%s'"), str); as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
break; break;
case ldstgv_indexed:
/* Load operations must load different registers. */
if ((opcode->opcode & (1 << 22))
&& opnds[0].reg.regno == opnds[1].addr.base_regno)
as_warn (_("unpredictable load of register -- `%s'"), str);
break;
case ldstpair_off: case ldstpair_off:
case ldstnapair_offs: case ldstnapair_offs:
case ldstpair_indexed: case ldstpair_indexed:

11
gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
View File

@ -121,14 +121,3 @@ Disassembly of section \.text:
.*: d960001f ldg xzr, \[x0\] .*: d960001f ldg xzr, \[x0\]
.*: d96ff000 ldg x0, \[x0, #4080\] .*: d96ff000 ldg x0, \[x0, #4080\]
.*: d9700000 ldg x0, \[x0, #-4096\] .*: d9700000 ldg x0, \[x0, #-4096\]
.*: d9e0001b ldgv x27, \[x0\]!
.*: d9e00360 ldgv x0, \[x27\]!
.*: d9e00379 ldgv x25, \[x27\]!
.*: d9e003e0 ldgv x0, \[sp\]!
.*: d9e0001f ldgv xzr, \[x0\]!
.*: d9a00000 stgv x0, \[x0\]!
.*: d9a0001b stgv x27, \[x0\]!
.*: d9a00360 stgv x0, \[x27\]!
.*: d9a00379 stgv x25, \[x27\]!
.*: d9a003e0 stgv x0, \[sp\]!
.*: d9a0001f stgv xzr, \[x0\]!

13
gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
View File

@ -30,14 +30,6 @@ func:
\op [sp], #-4096 \op [sp], #-4096
.endm .endm
.macro expand_ldg_bulk op
\op x27, [x0]!
\op x0, [x27]!
\op x25, [x27]!
\op x0, [sp]!
\op xzr, [x0]!
.endm
# IRG # IRG
expand_3_reg irg expand_3_reg irg
irg sp, x0 irg sp, x0
@ -106,8 +98,3 @@ func:
ldg xzr, [x0, #0] ldg xzr, [x0, #0]
ldg x0, [x0, #4080] ldg x0, [x0, #4080]
ldg x0, [x0, #-4096] ldg x0, [x0, #-4096]
expand_ldg_bulk ldgv
stgv x0, [x0]!
expand_ldg_bulk stgv

7
gas/testsuite/gas/aarch64/illegal-memtag.l
View File

@ -12,9 +12,6 @@
[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]' [^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]' [^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]' [^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
[^:]*:[0-9]+: Warning: unpredictable load of register -- `ldgv x1,\[x1\]!'
[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `ldgv x1,\[x2\]'
[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `stgv x1,\[x2\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3' [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3' [^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp' [^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
@ -40,7 +37,3 @@
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]' [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]' [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]' [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgv sp,\[x1\]!'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgv x0,\[xzr\]!'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgv sp,\[x1\]!'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgv x0,\[xzr\]!'

12
gas/testsuite/gas/aarch64/illegal-memtag.s
View File

@ -20,14 +20,6 @@ func:
stgp x1, x2, [x3, #33] stgp x1, x2, [x3, #33]
stgp x1, x2, [x3, #-1025] stgp x1, x2, [x3, #-1025]
# LDGV : Warn for Xt == Xn
# STGV : Sould not warn for above
ldgv x1, [x1]!
stgv x1, [x1]!
# Error for no writeback
ldgv x1, [x2]
stgv x1, [x2]
# Illegal SP/XZR registers # Illegal SP/XZR registers
irg xzr, x2, x3 irg xzr, x2, x3
irg x1, xzr, x3 irg x1, xzr, x3
@ -54,7 +46,3 @@ func:
stgp x0, x0, [xzr] stgp x0, x0, [xzr]
ldg sp, [x0, #16] ldg sp, [x0, #16]
ldg x0, [xzr, #16] ldg x0, [xzr, #16]
ldgv sp, [x1]!
ldgv x0, [xzr]!
stgv sp, [x1]!
stgv x0, [xzr]!

7
include/ChangeLog
View File

@ -1,3 +1,10 @@
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Remove
AARCH64_OPND_ADDR_SIMPLE_2.
(enum aarch64_insn_class): Remove ldstgv_indexed.
2019-01-22 Tom Tromey <tom@tromey.com> 2019-01-22 Tom Tromey <tom@tromey.com>
* coff/ecoff.h: Include coff/sym.h. * coff/ecoff.h: Include coff/sym.h.

2
include/opcode/aarch64.h
View File

@ -275,7 +275,6 @@ enum aarch64_opnd
AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
AARCH64_OPND_ADDR_SIMPLE_2, /* Address of ld/stgv. */
AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
@ -562,7 +561,6 @@ enum aarch64_insn_class
ldstnapair_offs, ldstnapair_offs,
ldstpair_off, ldstpair_off,
ldstpair_indexed, ldstpair_indexed,
ldstgv_indexed,
loadlit, loadlit,
log_imm, log_imm,
log_shift, log_shift,

16
opcodes/ChangeLog
View File

@ -1,3 +1,19 @@
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
* aarch64-dis.h (ext_addr_simple_2): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Remove
case for ldstgv_indexed.
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
2019-01-23 Nick Clifton <nickc@redhat.com> 2019-01-23 Nick Clifton <nickc@redhat.com>
* po/pt_BR.po: Updated Brazilian Portuguese translation. * po/pt_BR.po: Updated Brazilian Portuguese translation.

678
opcodes/aarch64-asm-2.c
View File

@ -201,390 +201,390 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 757: /* extr */ case 757: /* extr */
value = 757; /* --> extr. */ value = 757; /* --> extr. */
break; break;
case 990: /* bic */ case 988: /* bic */
case 989: /* and */ case 987: /* and */
value = 989; /* --> and. */ value = 987; /* --> and. */
break; break;
case 992: /* mov */ case 990: /* mov */
case 991: /* orr */ case 989: /* orr */
value = 991; /* --> orr. */ value = 989; /* --> orr. */
break; break;
case 995: /* tst */ case 993: /* tst */
case 994: /* ands */ case 992: /* ands */
value = 994; /* --> ands. */ value = 992; /* --> ands. */
break; break;
case 1000: /* uxtw */ case 998: /* uxtw */
case 999: /* mov */ case 997: /* mov */
case 998: /* orr */ case 996: /* orr */
value = 998; /* --> orr. */ value = 996; /* --> orr. */
break; break;
case 1002: /* mvn */ case 1000: /* mvn */
case 1001: /* orn */ case 999: /* orn */
value = 1001; /* --> orn. */ value = 999; /* --> orn. */
break; break;
case 1006: /* tst */ case 1004: /* tst */
case 1005: /* ands */ case 1003: /* ands */
value = 1005; /* --> ands. */ value = 1003; /* --> ands. */
break; break;
case 1132: /* staddb */ case 1130: /* staddb */
case 1036: /* ldaddb */ case 1034: /* ldaddb */
value = 1036; /* --> ldaddb. */ value = 1034; /* --> ldaddb. */
break; break;
case 1133: /* staddh */ case 1131: /* staddh */
case 1037: /* ldaddh */ case 1035: /* ldaddh */
value = 1037; /* --> ldaddh. */ value = 1035; /* --> ldaddh. */
break; break;
case 1134: /* stadd */ case 1132: /* stadd */
case 1038: /* ldadd */ case 1036: /* ldadd */
value = 1038; /* --> ldadd. */ value = 1036; /* --> ldadd. */
break; break;
case 1135: /* staddlb */ case 1133: /* staddlb */
case 1040: /* ldaddlb */ case 1038: /* ldaddlb */
value = 1040; /* --> ldaddlb. */ value = 1038; /* --> ldaddlb. */
break; break;
case 1136: /* staddlh */ case 1134: /* staddlh */
case 1043: /* ldaddlh */ case 1041: /* ldaddlh */
value = 1043; /* --> ldaddlh. */ value = 1041; /* --> ldaddlh. */
break; break;
case 1137: /* staddl */ case 1135: /* staddl */
case 1046: /* ldaddl */ case 1044: /* ldaddl */
value = 1046; /* --> ldaddl. */ value = 1044; /* --> ldaddl. */
break; break;
case 1138: /* stclrb */ case 1136: /* stclrb */
case 1048: /* ldclrb */ case 1046: /* ldclrb */
value = 1048; /* --> ldclrb. */ value = 1046; /* --> ldclrb. */
break; break;
case 1139: /* stclrh */ case 1137: /* stclrh */
case 1049: /* ldclrh */ case 1047: /* ldclrh */
value = 1049; /* --> ldclrh. */ value = 1047; /* --> ldclrh. */
break; break;
case 1140: /* stclr */ case 1138: /* stclr */
case 1050: /* ldclr */ case 1048: /* ldclr */
value = 1050; /* --> ldclr. */ value = 1048; /* --> ldclr. */
break; break;
case 1141: /* stclrlb */ case 1139: /* stclrlb */
case 1052: /* ldclrlb */ case 1050: /* ldclrlb */
value = 1052; /* --> ldclrlb. */ value = 1050; /* --> ldclrlb. */
break; break;
case 1142: /* stclrlh */ case 1140: /* stclrlh */
case 1055: /* ldclrlh */ case 1053: /* ldclrlh */
value = 1055; /* --> ldclrlh. */ value = 1053; /* --> ldclrlh. */
break; break;
case 1143: /* stclrl */ case 1141: /* stclrl */
case 1058: /* ldclrl */ case 1056: /* ldclrl */
value = 1058; /* --> ldclrl. */ value = 1056; /* --> ldclrl. */
break; break;
case 1144: /* steorb */ case 1142: /* steorb */
case 1060: /* ldeorb */ case 1058: /* ldeorb */
value = 1060; /* --> ldeorb. */ value = 1058; /* --> ldeorb. */
break; break;
case 1145: /* steorh */ case 1143: /* steorh */
case 1061: /* ldeorh */ case 1059: /* ldeorh */
value = 1061; /* --> ldeorh. */ value = 1059; /* --> ldeorh. */
break; break;
case 1146: /* steor */ case 1144: /* steor */
case 1062: /* ldeor */ case 1060: /* ldeor */
value = 1062; /* --> ldeor. */ value = 1060; /* --> ldeor. */
break; break;
case 1147: /* steorlb */ case 1145: /* steorlb */
case 1064: /* ldeorlb */ case 1062: /* ldeorlb */
value = 1064; /* --> ldeorlb. */ value = 1062; /* --> ldeorlb. */
break; break;
case 1148: /* steorlh */ case 1146: /* steorlh */
case 1067: /* ldeorlh */ case 1065: /* ldeorlh */
value = 1067; /* --> ldeorlh. */ value = 1065; /* --> ldeorlh. */
break; break;
case 1149: /* steorl */ case 1147: /* steorl */
case 1070: /* ldeorl */ case 1068: /* ldeorl */
value = 1070; /* --> ldeorl. */ value = 1068; /* --> ldeorl. */
break; break;
case 1150: /* stsetb */ case 1148: /* stsetb */
case 1072: /* ldsetb */ case 1070: /* ldsetb */
value = 1072; /* --> ldsetb. */ value = 1070; /* --> ldsetb. */
break; break;
case 1151: /* stseth */ case 1149: /* stseth */
case 1073: /* ldseth */ case 1071: /* ldseth */
value = 1073; /* --> ldseth. */ value = 1071; /* --> ldseth. */
break; break;
case 1152: /* stset */ case 1150: /* stset */
case 1074: /* ldset */ case 1072: /* ldset */
value = 1074; /* --> ldset. */ value = 1072; /* --> ldset. */
break; break;
case 1153: /* stsetlb */ case 1151: /* stsetlb */
case 1076: /* ldsetlb */ case 1074: /* ldsetlb */
value = 1076; /* --> ldsetlb. */ value = 1074; /* --> ldsetlb. */
break; break;
case 1154: /* stsetlh */ case 1152: /* stsetlh */
case 1079: /* ldsetlh */ case 1077: /* ldsetlh */
value = 1079; /* --> ldsetlh. */ value = 1077; /* --> ldsetlh. */
break; break;
case 1155: /* stsetl */ case 1153: /* stsetl */
case 1082: /* ldsetl */ case 1080: /* ldsetl */
value = 1082; /* --> ldsetl. */ value = 1080; /* --> ldsetl. */
break; break;
case 1156: /* stsmaxb */ case 1154: /* stsmaxb */
case 1084: /* ldsmaxb */ case 1082: /* ldsmaxb */
value = 1084; /* --> ldsmaxb. */ value = 1082; /* --> ldsmaxb. */
break; break;
case 1157: /* stsmaxh */ case 1155: /* stsmaxh */
case 1085: /* ldsmaxh */ case 1083: /* ldsmaxh */
value = 1085; /* --> ldsmaxh. */ value = 1083; /* --> ldsmaxh. */
break; break;
case 1158: /* stsmax */ case 1156: /* stsmax */
case 1086: /* ldsmax */ case 1084: /* ldsmax */
value = 1086; /* --> ldsmax. */ value = 1084; /* --> ldsmax. */
break; break;
case 1159: /* stsmaxlb */ case 1157: /* stsmaxlb */
case 1088: /* ldsmaxlb */ case 1086: /* ldsmaxlb */
value = 1088; /* --> ldsmaxlb. */ value = 1086; /* --> ldsmaxlb. */
break; break;
case 1160: /* stsmaxlh */ case 1158: /* stsmaxlh */
case 1091: /* ldsmaxlh */ case 1089: /* ldsmaxlh */
value = 1091; /* --> ldsmaxlh. */ value = 1089; /* --> ldsmaxlh. */
break; break;
case 1161: /* stsmaxl */ case 1159: /* stsmaxl */
case 1094: /* ldsmaxl */ case 1092: /* ldsmaxl */
value = 1094; /* --> ldsmaxl. */ value = 1092; /* --> ldsmaxl. */
break; break;
case 1162: /* stsminb */ case 1160: /* stsminb */
case 1096: /* ldsminb */ case 1094: /* ldsminb */
value = 1096; /* --> ldsminb. */ value = 1094; /* --> ldsminb. */
break; break;
case 1163: /* stsminh */ case 1161: /* stsminh */
case 1097: /* ldsminh */ case 1095: /* ldsminh */
value = 1097; /* --> ldsminh. */ value = 1095; /* --> ldsminh. */
break; break;
case 1164: /* stsmin */ case 1162: /* stsmin */
case 1098: /* ldsmin */ case 1096: /* ldsmin */
value = 1098; /* --> ldsmin. */ value = 1096; /* --> ldsmin. */
break; break;
case 1165: /* stsminlb */ case 1163: /* stsminlb */
case 1100: /* ldsminlb */ case 1098: /* ldsminlb */
value = 1100; /* --> ldsminlb. */ value = 1098; /* --> ldsminlb. */
break; break;
case 1166: /* stsminlh */ case 1164: /* stsminlh */
case 1103: /* ldsminlh */ case 1101: /* ldsminlh */
value = 1103; /* --> ldsminlh. */ value = 1101; /* --> ldsminlh. */
break; break;
case 1167: /* stsminl */ case 1165: /* stsminl */
case 1106: /* ldsminl */ case 1104: /* ldsminl */
value = 1106; /* --> ldsminl. */ value = 1104; /* --> ldsminl. */
break; break;
case 1168: /* stumaxb */ case 1166: /* stumaxb */
case 1108: /* ldumaxb */ case 1106: /* ldumaxb */
value = 1108; /* --> ldumaxb. */ value = 1106; /* --> ldumaxb. */
break; break;
case 1169: /* stumaxh */ case 1167: /* stumaxh */
case 1109: /* ldumaxh */ case 1107: /* ldumaxh */
value = 1109; /* --> ldumaxh. */ value = 1107; /* --> ldumaxh. */
break; break;
case 1170: /* stumax */ case 1168: /* stumax */
case 1110: /* ldumax */ case 1108: /* ldumax */
value = 1110; /* --> ldumax. */ value = 1108; /* --> ldumax. */
break; break;
case 1171: /* stumaxlb */ case 1169: /* stumaxlb */
case 1112: /* ldumaxlb */ case 1110: /* ldumaxlb */
value = 1112; /* --> ldumaxlb. */ value = 1110; /* --> ldumaxlb. */
break; break;
case 1172: /* stumaxlh */ case 1170: /* stumaxlh */
case 1115: /* ldumaxlh */ case 1113: /* ldumaxlh */
value = 1115; /* --> ldumaxlh. */ value = 1113; /* --> ldumaxlh. */
break; break;
case 1173: /* stumaxl */ case 1171: /* stumaxl */
case 1118: /* ldumaxl */ case 1116: /* ldumaxl */
value = 1118; /* --> ldumaxl. */ value = 1116; /* --> ldumaxl. */
break; break;
case 1174: /* stuminb */ case 1172: /* stuminb */
case 1120: /* lduminb */ case 1118: /* lduminb */
value = 1120; /* --> lduminb. */ value = 1118; /* --> lduminb. */
break; break;
case 1175: /* stuminh */ case 1173: /* stuminh */
case 1121: /* lduminh */ case 1119: /* lduminh */
value = 1121; /* --> lduminh. */ value = 1119; /* --> lduminh. */
break; break;
case 1176: /* stumin */ case 1174: /* stumin */
case 1122: /* ldumin */ case 1120: /* ldumin */
value = 1122; /* --> ldumin. */ value = 1120; /* --> ldumin. */
break; break;
case 1177: /* stuminlb */ case 1175: /* stuminlb */
case 1124: /* lduminlb */ case 1122: /* lduminlb */
value = 1124; /* --> lduminlb. */ value = 1122; /* --> lduminlb. */
break; break;
case 1178: /* stuminlh */ case 1176: /* stuminlh */
case 1127: /* lduminlh */ case 1125: /* lduminlh */
value = 1127; /* --> lduminlh. */ value = 1125; /* --> lduminlh. */
break; break;
case 1179: /* stuminl */ case 1177: /* stuminl */
case 1130: /* lduminl */ case 1128: /* lduminl */
value = 1130; /* --> lduminl. */ value = 1128; /* --> lduminl. */
break;
case 1179: /* mov */
case 1178: /* movn */
value = 1178; /* --> movn. */
break; break;
case 1181: /* mov */ case 1181: /* mov */
case 1180: /* movn */ case 1180: /* movz */
value = 1180; /* --> movn. */ value = 1180; /* --> movz. */
break; break;
case 1183: /* mov */ case 1227: /* autibsp */
case 1182: /* movz */ case 1226: /* autibz */
value = 1182; /* --> movz. */ case 1225: /* autiasp */
case 1224: /* autiaz */
case 1223: /* pacibsp */
case 1222: /* pacibz */
case 1221: /* paciasp */
case 1220: /* paciaz */
case 1201: /* psb */
case 1200: /* esb */
case 1199: /* autib1716 */
case 1198: /* autia1716 */
case 1197: /* pacib1716 */
case 1196: /* pacia1716 */
case 1195: /* xpaclri */
case 1194: /* sevl */
case 1193: /* sev */
case 1192: /* wfi */
case 1191: /* wfe */
case 1190: /* yield */
case 1189: /* bti */
case 1188: /* csdb */
case 1187: /* nop */
case 1186: /* hint */
value = 1186; /* --> hint. */
break; break;
case 1229: /* autibsp */ case 1205: /* pssbb */
case 1228: /* autibz */ case 1204: /* ssbb */
case 1227: /* autiasp */ case 1203: /* dsb */
case 1226: /* autiaz */ value = 1203; /* --> dsb. */
case 1225: /* pacibsp */
case 1224: /* pacibz */
case 1223: /* paciasp */
case 1222: /* paciaz */
case 1203: /* psb */
case 1202: /* esb */
case 1201: /* autib1716 */
case 1200: /* autia1716 */
case 1199: /* pacib1716 */
case 1198: /* pacia1716 */
case 1197: /* xpaclri */
case 1196: /* sevl */
case 1195: /* sev */
case 1194: /* wfi */
case 1193: /* wfe */
case 1192: /* yield */
case 1191: /* bti */
case 1190: /* csdb */
case 1189: /* nop */
case 1188: /* hint */
value = 1188; /* --> hint. */
break; break;
case 1207: /* pssbb */ case 1216: /* cpp */
case 1206: /* ssbb */ case 1215: /* dvp */
case 1205: /* dsb */ case 1214: /* cfp */
value = 1205; /* --> dsb. */ case 1213: /* tlbi */
case 1212: /* ic */
case 1211: /* dc */
case 1210: /* at */
case 1209: /* sys */
value = 1209; /* --> sys. */
break; break;
case 1218: /* cpp */ case 2025: /* bic */
case 1217: /* dvp */ case 1275: /* and */
case 1216: /* cfp */ value = 1275; /* --> and. */
case 1215: /* tlbi */
case 1214: /* ic */
case 1213: /* dc */
case 1212: /* at */
case 1211: /* sys */
value = 1211; /* --> sys. */
break; break;
case 2027: /* bic */ case 1258: /* mov */
case 1277: /* and */ case 1277: /* and */
value = 1277; /* --> and. */ value = 1277; /* --> and. */
break; break;
case 1260: /* mov */ case 1262: /* movs */
case 1279: /* and */ case 1278: /* ands */
value = 1279; /* --> and. */ value = 1278; /* --> ands. */
break; break;
case 1264: /* movs */ case 2026: /* cmple */
case 1280: /* ands */ case 1313: /* cmpge */
value = 1280; /* --> ands. */ value = 1313; /* --> cmpge. */
break; break;
case 2028: /* cmple */ case 2029: /* cmplt */
case 1315: /* cmpge */ case 1316: /* cmpgt */
value = 1315; /* --> cmpge. */ value = 1316; /* --> cmpgt. */
break; break;
case 2031: /* cmplt */ case 2027: /* cmplo */
case 1318: /* cmpgt */ case 1318: /* cmphi */
value = 1318; /* --> cmpgt. */ value = 1318; /* --> cmphi. */
break; break;
case 2029: /* cmplo */ case 2028: /* cmpls */
case 1320: /* cmphi */ case 1321: /* cmphs */
value = 1320; /* --> cmphi. */ value = 1321; /* --> cmphs. */
break; break;
case 2030: /* cmpls */ case 1255: /* mov */
case 1323: /* cmphs */ case 1343: /* cpy */
value = 1323; /* --> cmphs. */ value = 1343; /* --> cpy. */
break; break;
case 1257: /* mov */ case 1257: /* mov */
case 1344: /* cpy */
value = 1344; /* --> cpy. */
break;
case 2036: /* fmov */
case 1260: /* mov */
case 1345: /* cpy */ case 1345: /* cpy */
value = 1345; /* --> cpy. */ value = 1345; /* --> cpy. */
break; break;
case 1259: /* mov */ case 1250: /* mov */
case 1346: /* cpy */ case 1357: /* dup */
value = 1346; /* --> cpy. */ value = 1357; /* --> dup. */
break;
case 2038: /* fmov */
case 1262: /* mov */
case 1347: /* cpy */
value = 1347; /* --> cpy. */
break; break;
case 1252: /* mov */ case 1252: /* mov */
case 1249: /* mov */
case 1358: /* dup */
value = 1358; /* --> dup. */
break;
case 2035: /* fmov */
case 1254: /* mov */
case 1359: /* dup */ case 1359: /* dup */
value = 1359; /* --> dup. */ value = 1359; /* --> dup. */
break; break;
case 1254: /* mov */ case 1253: /* mov */
case 1251: /* mov */ case 1360: /* dupm */
case 1360: /* dup */ value = 1360; /* --> dupm. */
value = 1360; /* --> dup. */
break; break;
case 2037: /* fmov */ case 2030: /* eon */
case 1256: /* mov */ case 1362: /* eor */
case 1361: /* dup */ value = 1362; /* --> eor. */
value = 1361; /* --> dup. */
break; break;
case 1255: /* mov */ case 1263: /* not */
case 1362: /* dupm */
value = 1362; /* --> dupm. */
break;
case 2032: /* eon */
case 1364: /* eor */ case 1364: /* eor */
value = 1364; /* --> eor. */ value = 1364; /* --> eor. */
break; break;
case 1265: /* not */ case 1264: /* nots */
case 1366: /* eor */ case 1365: /* eors */
value = 1366; /* --> eor. */ value = 1365; /* --> eors. */
break; break;
case 1266: /* nots */ case 2031: /* facle */
case 1367: /* eors */ case 1370: /* facge */
value = 1367; /* --> eors. */ value = 1370; /* --> facge. */
break; break;
case 2033: /* facle */ case 2032: /* faclt */
case 1372: /* facge */ case 1371: /* facgt */
value = 1372; /* --> facge. */ value = 1371; /* --> facgt. */
break; break;
case 2034: /* faclt */ case 2033: /* fcmle */
case 1373: /* facgt */ case 1384: /* fcmge */
value = 1373; /* --> facgt. */ value = 1384; /* --> fcmge. */
break; break;
case 2035: /* fcmle */ case 2034: /* fcmlt */
case 1386: /* fcmge */ case 1386: /* fcmgt */
value = 1386; /* --> fcmge. */ value = 1386; /* --> fcmgt. */
break; break;
case 2036: /* fcmlt */ case 1247: /* fmov */
case 1388: /* fcmgt */ case 1392: /* fcpy */
value = 1388; /* --> fcmgt. */ value = 1392; /* --> fcpy. */
break; break;
case 1249: /* fmov */ case 1246: /* fmov */
case 1394: /* fcpy */ case 1415: /* fdup */
value = 1394; /* --> fcpy. */ value = 1415; /* --> fdup. */
break; break;
case 1248: /* fmov */ case 1248: /* mov */
case 1417: /* fdup */ case 1746: /* orr */
value = 1417; /* --> fdup. */ value = 1746; /* --> orr. */
break; break;
case 1250: /* mov */ case 2037: /* orn */
case 1748: /* orr */ case 1747: /* orr */
value = 1748; /* --> orr. */ value = 1747; /* --> orr. */
break; break;
case 2039: /* orn */ case 1251: /* mov */
case 1749: /* orr */ case 1749: /* orr */
value = 1749; /* --> orr. */ value = 1749; /* --> orr. */
break; break;
case 1253: /* mov */ case 1261: /* movs */
case 1751: /* orr */ case 1750: /* orrs */
value = 1751; /* --> orr. */ value = 1750; /* --> orrs. */
break; break;
case 1263: /* movs */ case 1256: /* mov */
case 1752: /* orrs */ case 1812: /* sel */
value = 1752; /* --> orrs. */ value = 1812; /* --> sel. */
break; break;
case 1258: /* mov */ case 1259: /* mov */
case 1814: /* sel */ case 1813: /* sel */
value = 1814; /* --> sel. */ value = 1813; /* --> sel. */
break;
case 1261: /* mov */
case 1815: /* sel */
value = 1815; /* --> sel. */
break; break;
default: return NULL; default: return NULL;
} }
@ -627,6 +627,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 27: case 27:
case 28: case 28:
case 29: case 29:
case 159:
case 160: case 160:
case 161: case 161:
case 162: case 162:
@ -636,7 +637,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 166: case 166:
case 167: case 167:
case 168: case 168:
case 169: case 181:
case 182: case 182:
case 183: case 183:
case 184: case 184:
@ -645,9 +646,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 187: case 187:
case 188: case 188:
case 189: case 189:
case 190: case 193:
case 194: case 196:
case 197:
return aarch64_ins_regno (self, info, code, inst, errors); return aarch64_ins_regno (self, info, code, inst, errors);
case 13: case 13:
return aarch64_ins_reg_extended (self, info, code, inst, errors); return aarch64_ins_reg_extended (self, info, code, inst, errors);
@ -659,7 +659,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 31: case 31:
case 32: case 32:
case 33: case 33:
case 199: case 198:
return aarch64_ins_reglane (self, info, code, inst, errors); return aarch64_ins_reglane (self, info, code, inst, errors);
case 34: case 34:
return aarch64_ins_reglist (self, info, code, inst, errors); return aarch64_ins_reglist (self, info, code, inst, errors);
@ -693,8 +693,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 79: case 79:
case 80: case 80:
case 81: case 81:
case 157: case 156:
case 159: case 158:
case 173:
case 174: case 174:
case 175: case 175:
case 176: case 176:
@ -702,7 +703,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 178: case 178:
case 179: case 179:
case 180: case 180:
case 181:
return aarch64_ins_imm (self, info, code, inst, errors); return aarch64_ins_imm (self, info, code, inst, errors);
case 42: case 42:
case 43: case 43:
@ -712,10 +712,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 46: case 46:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 50: case 50:
case 148: case 147:
return aarch64_ins_fpimm (self, info, code, inst, errors); return aarch64_ins_fpimm (self, info, code, inst, errors);
case 67: case 67:
case 155: case 154:
return aarch64_ins_limm (self, info, code, inst, errors); return aarch64_ins_limm (self, info, code, inst, errors);
case 68: case 68:
return aarch64_ins_aimm (self, info, code, inst, errors); return aarch64_ins_aimm (self, info, code, inst, errors);
@ -725,69 +725,68 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors); return aarch64_ins_fbits (self, info, code, inst, errors);
case 72: case 72:
case 73: case 73:
case 153: case 152:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 74: case 74:
case 152: case 151:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 75: case 75:
case 76: case 76:
return aarch64_ins_cond (self, info, code, inst, errors); return aarch64_ins_cond (self, info, code, inst, errors);
case 82: case 82:
case 92: case 91:
return aarch64_ins_addr_simple (self, info, code, inst, errors); return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 83: case 83:
return aarch64_ins_addr_simple_2 (self, info, code, inst, errors);
case 84:
return aarch64_ins_addr_regoff (self, info, code, inst, errors); return aarch64_ins_addr_regoff (self, info, code, inst, errors);
case 84:
case 85: case 85:
case 86: case 86:
case 87:
case 89:
case 91:
return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 88: case 88:
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
case 90: case 90:
return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 87:
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
case 89:
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
case 93: case 92:
return aarch64_ins_addr_offset (self, info, code, inst, errors); return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 94: case 93:
return aarch64_ins_simd_addr_post (self, info, code, inst, errors); return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
case 95: case 94:
return aarch64_ins_sysreg (self, info, code, inst, errors); return aarch64_ins_sysreg (self, info, code, inst, errors);
case 96: case 95:
return aarch64_ins_pstatefield (self, info, code, inst, errors); return aarch64_ins_pstatefield (self, info, code, inst, errors);
case 96:
case 97: case 97:
case 98: case 98:
case 99: case 99:
case 100: case 100:
case 101:
return aarch64_ins_sysins_op (self, info, code, inst, errors); return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 101:
case 102: case 102:
case 103:
return aarch64_ins_barrier (self, info, code, inst, errors); return aarch64_ins_barrier (self, info, code, inst, errors);
case 104: case 103:
return aarch64_ins_prfop (self, info, code, inst, errors); return aarch64_ins_prfop (self, info, code, inst, errors);
case 104:
case 105: case 105:
case 106:
return aarch64_ins_hint (self, info, code, inst, errors); return aarch64_ins_hint (self, info, code, inst, errors);
case 107: case 106:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 107:
case 108: case 108:
case 109: case 109:
case 110: case 110:
case 111:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 112: case 111:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 113: case 112:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 113:
case 114: case 114:
case 115: case 115:
case 116: case 116:
case 117:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 117:
case 118: case 118:
case 119: case 119:
case 120: case 120:
@ -800,8 +799,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 127: case 127:
case 128: case 128:
case 129: case 129:
case 130:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 130:
case 131: case 131:
case 132: case 132:
case 133: case 133:
@ -809,49 +808,48 @@ aarch64_insert_operand (const aarch64_operand *self,
case 135: case 135:
case 136: case 136:
case 137: case 137:
case 138:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 138:
case 139: case 139:
case 140: case 140:
case 141: case 141:
case 142:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 143: case 142:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 144: case 143:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 145: case 144:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 146: case 145:
return aarch64_ins_sve_aimm (self, info, code, inst, errors); return aarch64_ins_sve_aimm (self, info, code, inst, errors);
case 147: case 146:
return aarch64_ins_sve_asimm (self, info, code, inst, errors); return aarch64_ins_sve_asimm (self, info, code, inst, errors);
case 149: case 148:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 150: case 149:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 151: case 150:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
case 154: case 153:
return aarch64_ins_inv_limm (self, info, code, inst, errors); return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 156: case 155:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
case 158: case 157:
return aarch64_ins_sve_scale (self, info, code, inst, errors); return aarch64_ins_sve_scale (self, info, code, inst, errors);
case 169:
case 170: case 170:
case 171:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors); return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 171:
case 172: case 172:
case 173:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors); return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 190:
case 191: case 191:
case 192: case 192:
case 193:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors); return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 195: case 194:
return aarch64_ins_sve_index (self, info, code, inst, errors); return aarch64_ins_sve_index (self, info, code, inst, errors);
case 196: case 195:
case 198: case 197:
return aarch64_ins_sve_reglist (self, info, code, inst, errors); return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort (); default: assert (0); abort ();
} }

11
opcodes/aarch64-asm.c
View File

@ -618,17 +618,6 @@ aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE; return TRUE;
} }
/* Encode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
bfd_boolean
aarch64_ins_addr_simple_2 (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst,
aarch64_operand_error *errors)
{
return aarch64_ins_addr_simple (self, info, code, inst, errors);
}
/* Encode the address operand for e.g. /* Encode the address operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
bfd_boolean bfd_boolean

1
opcodes/aarch64-asm.h
View File

@ -59,7 +59,6 @@ AARCH64_DECL_OPD_INSERTER (ins_limm);
AARCH64_DECL_OPD_INSERTER (ins_inv_limm); AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
AARCH64_DECL_OPD_INSERTER (ins_ft); AARCH64_DECL_OPD_INSERTER (ins_ft);
AARCH64_DECL_OPD_INSERTER (ins_addr_simple); AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
AARCH64_DECL_OPD_INSERTER (ins_addr_simple_2);
AARCH64_DECL_OPD_INSERTER (ins_addr_offset); AARCH64_DECL_OPD_INSERTER (ins_addr_offset);
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff); AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
AARCH64_DECL_OPD_INSERTER (ins_addr_simm); AARCH64_DECL_OPD_INSERTER (ins_addr_simm);

2590
opcodes/aarch64-dis-2.c
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File diff suppressed because it is too large Load Diff

17
opcodes/aarch64-dis.c
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@ -985,23 +985,6 @@ aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE; return TRUE;
} }
/* Decode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
bfd_boolean
aarch64_ext_addr_simple_2 (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
/* Rn */
info->addr.base_regno = extract_field (FLD_Rn, code, 0);
info->addr.writeback = 1;
info->addr.preind = 1;
return TRUE;
}
/* Decode the address operand for e.g. /* Decode the address operand for e.g.
stlur <Xt>, [<Xn|SP>{, <amount>}]. */ stlur <Xt>, [<Xn|SP>{, <amount>}]. */
bfd_boolean bfd_boolean

1
opcodes/aarch64-dis.h
View File

@ -82,7 +82,6 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm); AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm);
AARCH64_DECL_OPD_EXTRACTOR (ext_ft); AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple); AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple_2);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_offset); AARCH64_DECL_OPD_EXTRACTOR (ext_addr_offset);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff); AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm); AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);

31
opcodes/aarch64-opc-2.c
View File

@ -107,7 +107,6 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a writeback address with base register (no offset)"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
@ -257,24 +256,24 @@ static const unsigned op_enum_table [] =
925, 925,
931, 931,
932, 932,
983,
984,
985, 985,
986, 986,
987,
988,
12, 12,
636, 636,
637, 637,
1178,
1180, 1180,
1182, 1182,
1184, 990,
992,
1183,
1181, 1181,
1179,
318, 318,
624, 624,
635, 635,
634, 634,
990, 988,
631, 631,
628, 628,
620, 620,
@ -284,7 +283,7 @@ static const unsigned op_enum_table [] =
630, 630,
632, 632,
633, 633,
1000, 998,
664, 664,
667, 667,
670, 670,
@ -301,17 +300,17 @@ static const unsigned op_enum_table [] =
391, 391,
413, 413,
415, 415,
1253,
1258,
1251, 1251,
1250, 1256,
1254, 1249,
1248,
1252,
1259,
1261, 1261,
1263, 1262,
1258,
1264, 1264,
1260, 1263,
1266,
1265,
131, 131,
}; };

6
opcodes/aarch64-opc.c
View File

@ -1602,7 +1602,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
break; break;
case ldst_imm9: case ldst_imm9:
case ldstpair_indexed: case ldstpair_indexed:
case ldstgv_indexed:
case asisdlsep: case asisdlsep:
case asisdlsop: case asisdlsop:
if (opnd->addr.writeback == 0) if (opnd->addr.writeback == 0)
@ -3557,11 +3556,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "[%s]", name); snprintf (buf, size, "[%s]", name);
break; break;
case AARCH64_OPND_ADDR_SIMPLE_2:
name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
snprintf (buf, size, "[%s]!", name);
break;
case AARCH64_OPND_ADDR_REGOFF: case AARCH64_OPND_ADDR_REGOFF:
case AARCH64_OPND_SVE_ADDR_R: case AARCH64_OPND_SVE_ADDR_R:
case AARCH64_OPND_SVE_ADDR_RR: case AARCH64_OPND_SVE_ADDR_RR:

4
opcodes/aarch64-tbl.h
View File

@ -3324,8 +3324,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
MEMTAG_INSN ("ldgv", 0xd9e00000, 0xfffffc00, ldstgv_indexed, OP2 (Rt, ADDR_SIMPLE_2), QL_STLX, 0),
MEMTAG_INSN ("stgv", 0xd9a00000, 0xfffffc00, ldstgv_indexed, OP2 (Rt, ADDR_SIMPLE_2), QL_STLX, 0),
/* Limited Ordering Regions load/store instructions. */ /* Limited Ordering Regions load/store instructions. */
_LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), _LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
_LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
@ -4650,8 +4648,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_imm26), "26-bit PC-relative address") \ F(FLD_imm26), "26-bit PC-relative address") \
Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \ Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \
"an address with base register (no offset)") \ "an address with base register (no offset)") \
Y(ADDRESS, addr_simple_2, "ADDR_SIMPLE_2", 0, F(), \
"a writeback address with base register (no offset)") \
Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \ Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \
"an address with register offset") \ "an address with register offset") \
Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \ Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \