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* tc-i386.h (i386_target_format): Define even for ELFs.

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(QWORD_MNEM_SUFFIX): New macro.
	(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
	New macros
	(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
	(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
	ImmExt): Renumber.
	(Size64, No_qSuf, NoRex64, Rex64): New macros.
	(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
	(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
	InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
	SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
	(Reg, WordReg): Add Reg64.
	(Imm): Add Imm32S and Imm64.
	(EncImm): New.
	(Disp): Add Disp64 and Disp32S.
	(AnyMem): Add Disp32S.
	(RegRex, RegRex64): New macros.
	(rex_byte): New type.
	* tc-i386.c (set_16bit_code_flag): Kill.
	(fits_in_unsigned_long, fits_in_signed_long): New functions.
	(reloc): New parameter "signed"; support x86_64.
	(set_code_flag): New.
	(DEFAULT_ARCH): New macro; default to "i386".
	(default_arch): New static variable.
	(struct _i386_insn): New fields Operand_PCrel; rex.
	(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
	(flag_code): New enum and static variable.
	(use_rela_relocations): New static variable.
	(flag_code_names): New static variable.
	(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
	(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
	K6 and Athlon.
	(i386_align_code): Return plain "nop" for x86_64.
	(mode_from_disp_size): Support Disp32S.
	(smallest_imm_type): Support Imm32S and Imm64.
	(offset_in_range): Support size of 8.
	(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
	(md_pseudo_table): Add "code64"; use set_code_flat.
	(md_begin): Emit sane error message on hash failure.
	(tc_i386_fix_adjustable): Support x86_64 relocations.
	(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
	instructions supported on particular arch just partially,
	output of 64bit immediates, handling of Imm32S and Disp32S type.
	(i386_immedaite): Support x86_64 relocations; support 64bit constants.
	(i386_displacement): Likewise.
	(i386_index_check): Cleanup; support 64bit addresses.
	(md_apply_fix3): Support x86_64 relocation and rela.
	(md_longopts): Add "32" and "64".
	(md_parse_option): Add OPTION_32 and OPTION_64.
	(i386_target_format): Call even for ELFs; choose between
	elf64-x86-64 and elf32-i386.
	(i386_validate_fix): Refuse GOTOFF in 64bit mode.
	(tc_gen_reloc): Support rela relocations and x86_64.
	(intel_e09_1): Support QWORD.

	* i386.h (i386_optab): Replace "Imm" with "EncImm".
	(i386_regtab): Add flags field.
This commit is contained in:
Jan Hubicka 2000-12-20 13:24:13 +00:00
parent 7b82c249fa
commit 3e73aa7c95
6 changed files with 1047 additions and 370 deletions
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59
gas/ChangeLog
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@ -1,3 +1,62 @@
Wed Dec 20 14:21:22 MET 2000 Jan Hubicka <jh@suse.cz>
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem):
Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT"
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
2000-12-15 Diego Novillo <dnovillo@redhat.com> 2000-12-15 Diego Novillo <dnovillo@redhat.com>
* config/tc-i386.c (intel_e09_1): Only flag as a memory operand if * config/tc-i386.c (intel_e09_1): Only flag as a memory operand if

1003
gas/config/tc-i386.c
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135
gas/config/tc-i386.h
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@ -101,9 +101,8 @@ extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
#define AOUT_TARGET_FORMAT "a.out-i386" #define AOUT_TARGET_FORMAT "a.out-i386"
#endif #endif
#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \ #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
|| (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \ || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
|| (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
extern const char *i386_target_format PARAMS ((void)); extern const char *i386_target_format PARAMS ((void));
#define TARGET_FORMAT i386_target_format () #define TARGET_FORMAT i386_target_format ()
#else #else
@ -202,7 +201,8 @@ extern const char extra_symbol_chars[];
#define ADDR_PREFIX 2 #define ADDR_PREFIX 2
#define DATA_PREFIX 3 #define DATA_PREFIX 3
#define SEG_PREFIX 4 #define SEG_PREFIX 4
#define MAX_PREFIXES 5 /* max prefixes per opcode */ #define REX_PREFIX 5 /* must come last. */
#define MAX_PREFIXES 6 /* max prefixes per opcode */
/* we define the syntax here (modulo base,index,scale syntax) */ /* we define the syntax here (modulo base,index,scale syntax) */
#define REGISTER_PREFIX '%' #define REGISTER_PREFIX '%'
@ -229,6 +229,7 @@ extern const char extra_symbol_chars[];
#define BYTE_MNEM_SUFFIX 'b' #define BYTE_MNEM_SUFFIX 'b'
#define SHORT_MNEM_SUFFIX 's' #define SHORT_MNEM_SUFFIX 's'
#define LONG_MNEM_SUFFIX 'l' #define LONG_MNEM_SUFFIX 'l'
#define QWORD_MNEM_SUFFIX 'q'
/* Intel Syntax */ /* Intel Syntax */
#define LONG_DOUBLE_MNEM_SUFFIX 'x' #define LONG_DOUBLE_MNEM_SUFFIX 'x'
@ -278,9 +279,20 @@ typedef struct
#define Cpu486 0x10 /* i486 or better required */ #define Cpu486 0x10 /* i486 or better required */
#define Cpu586 0x20 /* i585 or better required */ #define Cpu586 0x20 /* i585 or better required */
#define Cpu686 0x40 /* i686 or better required */ #define Cpu686 0x40 /* i686 or better required */
#define CpuMMX 0x80 /* MMX support required */ #define CpuK6 0x80 /* AMD K6 or better required*/
#define CpuSSE 0x100 /* Streaming SIMD extensions required */ #define CpuAthlon 0x100 /* AMD Athlon or better required*/
#define Cpu3dnow 0x200 /* 3dnow! support required */ #define CpuSledgehammer 0x200 /* Sledgehammer or better required */
#define CpuMMX 0x400 /* MMX support required */
#define CpuSSE 0x800 /* Streaming SIMD extensions required */
#define Cpu3dnow 0x1000 /* 3dnow! support required */
#define CpuUnknown 0x2000 /* The CPU is unknown, be on the safe side. */
/* These flags are set by gas depending on the flag_code. */
#define Cpu64 0x4000000 /* 64bit support required */
#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
/* The default value for unknown CPUs - enable all features to avoid problems. */
#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSledgehammer|CpuMMX|CpuSSE|Cpu3dnow|CpuK6|CpuAthlon)
/* the bits in opcode_modifier are used to generate the final opcode from /* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of the base_opcode. These bits also are used to detect alternate forms of
@ -305,19 +317,23 @@ typedef struct
#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ #define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
#define Size16 0x2000 /* needs size prefix if in 32-bit mode */ #define Size16 0x2000 /* needs size prefix if in 32-bit mode */
#define Size32 0x4000 /* needs size prefix if in 16-bit mode */ #define Size32 0x4000 /* needs size prefix if in 16-bit mode */
#define IgnoreSize 0x8000 /* instruction ignores operand size prefix */ #define Size64 0x8000 /* needs size prefix if in 16-bit mode */
#define DefaultSize 0x10000 /* default insn size depends on mode */ #define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
#define No_bSuf 0x20000 /* b suffix on instruction illegal */ #define DefaultSize 0x20000 /* default insn size depends on mode */
#define No_wSuf 0x40000 /* w suffix on instruction illegal */ #define No_bSuf 0x40000 /* b suffix on instruction illegal */
#define No_lSuf 0x80000 /* l suffix on instruction illegal */ #define No_wSuf 0x80000 /* w suffix on instruction illegal */
#define No_sSuf 0x100000 /* s suffix on instruction illegal */ #define No_lSuf 0x100000 /* l suffix on instruction illegal */
#define No_xSuf 0x200000 /* x suffix on instruction illegal */ #define No_sSuf 0x200000 /* s suffix on instruction illegal */
#define FWait 0x400000 /* instruction needs FWAIT */ #define No_qSuf 0x400000 /* q suffix on instruction illegal */
#define IsString 0x800000 /* quick test for string instructions */ #define No_xSuf 0x800000 /* x suffix on instruction illegal */
#define regKludge 0x1000000 /* fake an extra reg operand for clr, imul */ #define FWait 0x1000000 /* instruction needs FWAIT */
#define IsPrefix 0x2000000 /* opcode is a prefix */ #define IsString 0x2000000 /* quick test for string instructions */
#define ImmExt 0x4000000 /* instruction has extension in 8 bit imm */ #define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
#define Ugh 0x8000000 /* deprecated fp insn, gets a warning */ #define IsPrefix 0x8000000 /* opcode is a prefix */
#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
/* operand_types[i] describes the type of operand i. This is made /* operand_types[i] describes the type of operand i. This is made
by OR'ing together all of the possible type masks. (e.g. by OR'ing together all of the possible type masks. (e.g.
@ -330,51 +346,58 @@ typedef struct
#define Reg8 0x1 /* 8 bit reg */ #define Reg8 0x1 /* 8 bit reg */
#define Reg16 0x2 /* 16 bit reg */ #define Reg16 0x2 /* 16 bit reg */
#define Reg32 0x4 /* 32 bit reg */ #define Reg32 0x4 /* 32 bit reg */
#define Reg64 0x8 /* 64 bit reg */
/* immediate */ /* immediate */
#define Imm8 0x8 /* 8 bit immediate */ #define Imm8 0x10 /* 8 bit immediate */
#define Imm8S 0x10 /* 8 bit immediate sign extended */ #define Imm8S 0x20 /* 8 bit immediate sign extended */
#define Imm16 0x20 /* 16 bit immediate */ #define Imm16 0x40 /* 16 bit immediate */
#define Imm32 0x40 /* 32 bit immediate */ #define Imm32 0x80 /* 32 bit immediate */
#define Imm1 0x80 /* 1 bit immediate */ #define Imm32S 0x100 /* 32 bit immediate sign extended */
#define Imm64 0x200 /* 64 bit immediate */
#define Imm1 0x400 /* 1 bit immediate */
/* memory */ /* memory */
#define BaseIndex 0x100 #define BaseIndex 0x800
/* Disp8,16,32 are used in different ways, depending on the /* Disp8,16,32 are used in different ways, depending on the
instruction. For jumps, they specify the size of the PC relative instruction. For jumps, they specify the size of the PC relative
displacement, for baseindex type instructions, they specify the displacement, for baseindex type instructions, they specify the
size of the offset relative to the base register, and for memory size of the offset relative to the base register, and for memory
offset instructions such as `mov 1234,%al' they specify the size of offset instructions such as `mov 1234,%al' they specify the size of
the offset relative to the segment base. */ the offset relative to the segment base. */
#define Disp8 0x200 /* 8 bit displacement */ #define Disp8 0x1000 /* 8 bit displacement */
#define Disp16 0x400 /* 16 bit displacement */ #define Disp16 0x2000 /* 16 bit displacement */
#define Disp32 0x800 /* 32 bit displacement */ #define Disp32 0x4000 /* 32 bit displacement */
#define Disp32S 0x8000 /* 32 bit signed displacement */
#define Disp64 0x10000 /* 64 bit displacement */
/* specials */ /* specials */
#define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */ #define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
#define ShiftCount 0x2000 /* register to hold shift cound = cl */ #define ShiftCount 0x40000 /* register to hold shift cound = cl */
#define Control 0x4000 /* Control register */ #define Control 0x80000 /* Control register */
#define Debug 0x8000 /* Debug register */ #define Debug 0x100000 /* Debug register */
#define Test 0x10000 /* Test register */ #define Test 0x200000 /* Test register */
#define FloatReg 0x20000 /* Float register */ #define FloatReg 0x400000 /* Float register */
#define FloatAcc 0x40000 /* Float stack top %st(0) */ #define FloatAcc 0x800000 /* Float stack top %st(0) */
#define SReg2 0x80000 /* 2 bit segment register */ #define SReg2 0x1000000 /* 2 bit segment register */
#define SReg3 0x100000 /* 3 bit segment register */ #define SReg3 0x2000000 /* 3 bit segment register */
#define Acc 0x200000 /* Accumulator %al or %ax or %eax */ #define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
#define JumpAbsolute 0x400000 #define JumpAbsolute 0x8000000
#define RegMMX 0x800000 /* MMX register */ #define RegMMX 0x10000000 /* MMX register */
#define RegXMM 0x1000000 /* XMM registers in PIII */ #define RegXMM 0x20000000 /* XMM registers in PIII */
#define EsSeg 0x2000000 /* String insn operand with fixed es segment */ #define EsSeg 0x40000000 /* String insn operand with fixed es segment */
/* InvMem is for instructions with a modrm byte that only allow a /* InvMem is for instructions with a modrm byte that only allow a
general register encoding in the i.tm.mode and i.tm.regmem fields, general register encoding in the i.tm.mode and i.tm.regmem fields,
eg. control reg moves. They really ought to support a memory form, eg. control reg moves. They really ought to support a memory form,
but don't, so we add an InvMem flag to the register operand to but don't, so we add an InvMem flag to the register operand to
indicate that it should be encoded in the i.tm.regmem field. */ indicate that it should be encoded in the i.tm.regmem field. */
#define InvMem 0x4000000 #define InvMem 0x80000000
#define Reg (Reg8|Reg16|Reg32) /* gen'l register */ #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
#define WordReg (Reg16|Reg32) #define WordReg (Reg16|Reg32|Reg64)
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
#define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */ #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
#define Disp (Disp8|Disp16|Disp32) /* General displacement */ #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
#define AnyMem (Disp|BaseIndex|InvMem) /* General memory */ #define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
/* The following aliases are defined because the opcode table /* The following aliases are defined because the opcode table
carefully specifies the allowed memory types for each instruction. carefully specifies the allowed memory types for each instruction.
At the moment we can only tell a memory reference size by the At the moment we can only tell a memory reference size by the
@ -408,6 +431,9 @@ typedef struct
{ {
char *reg_name; char *reg_name;
unsigned int reg_type; unsigned int reg_type;
unsigned int reg_flags;
#define RegRex 0x1 /* Extended register. */
#define RegRex64 0x2 /* Extended 8 bit register. */
unsigned int reg_num; unsigned int reg_num;
} }
reg_entry; reg_entry;
@ -428,6 +454,17 @@ typedef struct
} }
modrm_byte; modrm_byte;
/* x86-64 extension prefix. */
typedef struct
{
unsigned int mode64;
unsigned int extX; /* Used to extend modrm reg field. */
unsigned int extY; /* Used to extend SIB index field. */
unsigned int extZ; /* Used to extend modrm reg/mem, SIB base, modrm base fields. */
unsigned int empty; /* Used to old-style byte registers to new style. */
}
rex_byte;
/* 386 opcode byte to code indirect addressing. */ /* 386 opcode byte to code indirect addressing. */
typedef struct typedef struct
{ {

1
gas/configure.in
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@ -117,7 +117,6 @@ changequote([,])dnl
armb*) cpu_type=arm endian=little ;; armb*) cpu_type=arm endian=little ;;
armv*l) cpu_type=arm endian=little ;; armv*l) cpu_type=arm endian=little ;;
armv*b) cpu_type=arm endian=big ;; armv*b) cpu_type=arm endian=big ;;
xscale*) cpu_type=arm endian=little ;;
strongarm*) cpu_type=arm endian=little ;; strongarm*) cpu_type=arm endian=little ;;
thumb*) cpu_type=arm endian=little ;; thumb*) cpu_type=arm endian=little ;;
hppa*) cpu_type=hppa ;; hppa*) cpu_type=hppa ;;

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include/opcode/ChangeLog
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@ -1,3 +1,8 @@
Wed Dec 20 14:22:03 MET 2000 Jan Hubicka <jh@suse.cz>
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-12 Nick Clifton <nickc@redhat.com> 2000-12-12 Nick Clifton <nickc@redhat.com>
* mips.h: Fix formatting. * mips.h: Fix formatting.

214
include/opcode/i386.h
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@ -77,8 +77,8 @@ static const template i386_optab[] = {
#define MOV_AX_DISP32 0xa0 #define MOV_AX_DISP32 0xa0
{ "mov", 2, 0xa0, X, 0, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, { "mov", 2, 0xa0, X, 0, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
{ "mov", 2, 0x88, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } }, { "mov", 2, 0x88, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } },
{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } }, { "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg, 0 } },
{ "mov", 2, 0xc6, X, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } }, { "mov", 2, 0xc6, X, 0, bwl_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } },
/* The segment register moves accept WordReg so that a segment register /* The segment register moves accept WordReg so that a segment register
can be copied to a 32 bit register, and vice versa, without using a can be copied to a 32 bit register, and vice versa, without using a
size prefix. When moving to a 32 bit register, the upper 16 bits size prefix. When moving to a 32 bit register, the upper 16 bits
@ -171,57 +171,57 @@ static const template i386_optab[] = {
/* Arithmetic. */ /* Arithmetic. */
{"add", 2, 0x00, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"add", 2, 0x00, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
{"add", 2, 0x83, 0, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, {"add", 2, 0x83, 0, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
{"add", 2, 0x04, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, {"add", 2, 0x04, X, 0, bwl_Suf|W, { EncImm, Acc, 0} },
{"add", 2, 0x80, 0, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, {"add", 2, 0x80, 0, 0, bwl_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
{"inc", 1, 0x40, X, 0, wl_Suf|ShortForm, { WordReg, 0, 0} }, {"inc", 1, 0x40, X, 0, wl_Suf|ShortForm, { WordReg, 0, 0} },
{"inc", 1, 0xfe, 0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, {"inc", 1, 0xfe, 0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
{"sub", 2, 0x28, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"sub", 2, 0x28, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
{"sub", 2, 0x83, 5, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, {"sub", 2, 0x83, 5, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
{"sub", 2, 0x2c, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, {"sub", 2, 0x2c, X, 0, bwl_Suf|W, { EncImm, Acc, 0} },
{"sub", 2, 0x80, 5, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, {"sub", 2, 0x80, 5, 0, bwl_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
{"dec", 1, 0x48, X, 0, wl_Suf|ShortForm, { WordReg, 0, 0} }, {"dec", 1, 0x48, X, 0, wl_Suf|ShortForm, { WordReg, 0, 0} },
{"dec", 1, 0xfe, 1, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, {"dec", 1, 0xfe, 1, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
{"sbb", 2, 0x18, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"sbb", 2, 0x18, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
{"sbb", 2, 0x83, 3, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, {"sbb", 2, 0x83, 3, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
{"sbb", 2, 0x1c, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, {"sbb", 2, 0x1c, X, 0, bwl_Suf|W, { EncImm, Acc, 0} },
{"sbb", 2, 0x80, 3, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, {"sbb", 2, 0x80, 3, 0, bwl_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
{"cmp", 2, 0x38, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"cmp", 2, 0x38, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
{"cmp", 2, 0x83, 7, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, {"cmp", 2, 0x83, 7, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
{"cmp", 2, 0x3c, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, {"cmp", 2, 0x3c, X, 0, bwl_Suf|W, { EncImm, Acc, 0} },
{"cmp", 2, 0x80, 7, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, {"cmp", 2, 0x80, 7, 0, bwl_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
{"test", 2, 0x84, X, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, {"test", 2, 0x84, X, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
{"test", 2, 0x84, X, 0, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"test", 2, 0x84, X, 0, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
{"test", 2, 0xa8, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, {"test", 2, 0xa8, X, 0, bwl_Suf|W, { EncImm, Acc, 0} },
{"test", 2, 0xf6, 0, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, {"test", 2, 0xf6, 0, 0, bwl_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
{"and", 2, 0x20, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"and", 2, 0x20, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
{"and", 2, 0x83, 4, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, {"and", 2, 0x83, 4, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
{"and", 2, 0x24, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, {"and", 2, 0x24, X, 0, bwl_Suf|W, { EncImm, Acc, 0} },
{"and", 2, 0x80, 4, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, {"and", 2, 0x80, 4, 0, bwl_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
{"or", 2, 0x08, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"or", 2, 0x08, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
{"or", 2, 0x83, 1, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, {"or", 2, 0x83, 1, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
{"or", 2, 0x0c, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, {"or", 2, 0x0c, X, 0, bwl_Suf|W, { EncImm, Acc, 0} },
{"or", 2, 0x80, 1, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, {"or", 2, 0x80, 1, 0, bwl_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
{"xor", 2, 0x30, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"xor", 2, 0x30, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
{"xor", 2, 0x83, 6, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, {"xor", 2, 0x83, 6, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
{"xor", 2, 0x34, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, {"xor", 2, 0x34, X, 0, bwl_Suf|W, { EncImm, Acc, 0} },
{"xor", 2, 0x80, 6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, {"xor", 2, 0x80, 6, 0, bwl_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
/* clr with 1 operand is really xor with 2 operands. */ /* clr with 1 operand is really xor with 2 operands. */
{"clr", 1, 0x30, X, 0, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, {"clr", 1, 0x30, X, 0, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
{"adc", 2, 0x10, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"adc", 2, 0x10, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
{"adc", 2, 0x83, 2, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, {"adc", 2, 0x83, 2, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
{"adc", 2, 0x14, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, {"adc", 2, 0x14, X, 0, bwl_Suf|W, { EncImm, Acc, 0} },
{"adc", 2, 0x80, 2, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, {"adc", 2, 0x80, 2, 0, bwl_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
{"neg", 1, 0xf6, 3, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, {"neg", 1, 0xf6, 3, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
{"not", 1, 0xf6, 2, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, {"not", 1, 0xf6, 2, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
@ -1085,104 +1085,104 @@ static const template i386_optab[] = {
static const reg_entry i386_regtab[] = { static const reg_entry i386_regtab[] = {
/* make %st first as we test for it */ /* make %st first as we test for it */
{"st", FloatReg|FloatAcc, 0}, {"st", FloatReg|FloatAcc, 0, 0},
/* 8 bit regs */ /* 8 bit regs */
{"al", Reg8|Acc, 0}, {"al", Reg8|Acc, 0, 0},
{"cl", Reg8|ShiftCount, 1}, {"cl", Reg8|ShiftCount, 0, 1},
{"dl", Reg8, 2}, {"dl", Reg8, 0, 2},
{"bl", Reg8, 3}, {"bl", Reg8, 0, 3},
{"ah", Reg8, 4}, {"ah", Reg8, 0, 4},
{"ch", Reg8, 5}, {"ch", Reg8, 0, 5},
{"dh", Reg8, 6}, {"dh", Reg8, 0, 6},
{"bh", Reg8, 7}, {"bh", Reg8, 0, 7},
/* 16 bit regs */ /* 16 bit regs */
{"ax", Reg16|Acc, 0}, {"ax", Reg16|Acc, 0, 0},
{"cx", Reg16, 1}, {"cx", Reg16, 0, 1},
{"dx", Reg16|InOutPortReg, 2}, {"dx", Reg16|InOutPortReg, 0, 2},
{"bx", Reg16|BaseIndex, 3}, {"bx", Reg16|BaseIndex, 0, 3},
{"sp", Reg16, 4}, {"sp", Reg16, 0, 4},
{"bp", Reg16|BaseIndex, 5}, {"bp", Reg16|BaseIndex, 0, 5},
{"si", Reg16|BaseIndex, 6}, {"si", Reg16|BaseIndex, 0, 6},
{"di", Reg16|BaseIndex, 7}, {"di", Reg16|BaseIndex, 0, 7},
/* 32 bit regs */ /* 32 bit regs */
{"eax", Reg32|BaseIndex|Acc, 0}, {"eax", Reg32|BaseIndex|Acc, 0, 0},
{"ecx", Reg32|BaseIndex, 1}, {"ecx", Reg32|BaseIndex, 0, 1},
{"edx", Reg32|BaseIndex, 2}, {"edx", Reg32|BaseIndex, 0, 2},
{"ebx", Reg32|BaseIndex, 3}, {"ebx", Reg32|BaseIndex, 0, 3},
{"esp", Reg32, 4}, {"esp", Reg32, 0, 4},
{"ebp", Reg32|BaseIndex, 5}, {"ebp", Reg32|BaseIndex, 0, 5},
{"esi", Reg32|BaseIndex, 6}, {"esi", Reg32|BaseIndex, 0, 6},
{"edi", Reg32|BaseIndex, 7}, {"edi", Reg32|BaseIndex, 0, 7},
/* segment registers */ /* segment registers */
{"es", SReg2, 0}, {"es", SReg2, 0, 0},
{"cs", SReg2, 1}, {"cs", SReg2, 0, 1},
{"ss", SReg2, 2}, {"ss", SReg2, 0, 2},
{"ds", SReg2, 3}, {"ds", SReg2, 0, 3},
{"fs", SReg3, 4}, {"fs", SReg3, 0, 4},
{"gs", SReg3, 5}, {"gs", SReg3, 0, 5},
/* control registers */ /* control registers */
{"cr0", Control, 0}, {"cr0", Control, 0, 0},
{"cr1", Control, 1}, {"cr1", Control, 0, 1},
{"cr2", Control, 2}, {"cr2", Control, 0, 2},
{"cr3", Control, 3}, {"cr3", Control, 0, 3},
{"cr4", Control, 4}, {"cr4", Control, 0, 4},
{"cr5", Control, 5}, {"cr5", Control, 0, 5},
{"cr6", Control, 6}, {"cr6", Control, 0, 6},
{"cr7", Control, 7}, {"cr7", Control, 0, 7},
/* debug registers */ /* debug registers */
{"db0", Debug, 0}, {"db0", Debug, 0, 0},
{"db1", Debug, 1}, {"db1", Debug, 0, 1},
{"db2", Debug, 2}, {"db2", Debug, 0, 2},
{"db3", Debug, 3}, {"db3", Debug, 0, 3},
{"db4", Debug, 4}, {"db4", Debug, 0, 4},
{"db5", Debug, 5}, {"db5", Debug, 0, 5},
{"db6", Debug, 6}, {"db6", Debug, 0, 6},
{"db7", Debug, 7}, {"db7", Debug, 0, 7},
{"dr0", Debug, 0}, {"dr0", Debug, 0, 0},
{"dr1", Debug, 1}, {"dr1", Debug, 0, 1},
{"dr2", Debug, 2}, {"dr2", Debug, 0, 2},
{"dr3", Debug, 3}, {"dr3", Debug, 0, 3},
{"dr4", Debug, 4}, {"dr4", Debug, 0, 4},
{"dr5", Debug, 5}, {"dr5", Debug, 0, 5},
{"dr6", Debug, 6}, {"dr6", Debug, 0, 6},
{"dr7", Debug, 7}, {"dr7", Debug, 0, 7},
/* test registers */ /* test registers */
{"tr0", Test, 0}, {"tr0", Test, 0, 0},
{"tr1", Test, 1}, {"tr1", Test, 0, 1},
{"tr2", Test, 2}, {"tr2", Test, 0, 2},
{"tr3", Test, 3}, {"tr3", Test, 0, 3},
{"tr4", Test, 4}, {"tr4", Test, 0, 4},
{"tr5", Test, 5}, {"tr5", Test, 0, 5},
{"tr6", Test, 6}, {"tr6", Test, 0, 6},
{"tr7", Test, 7}, {"tr7", Test, 0, 7},
/* mmx and simd registers */ /* mmx and simd registers */
{"mm0", RegMMX, 0}, {"mm0", RegMMX, 0, 0},
{"mm1", RegMMX, 1}, {"mm1", RegMMX, 0, 1},
{"mm2", RegMMX, 2}, {"mm2", RegMMX, 0, 2},
{"mm3", RegMMX, 3}, {"mm3", RegMMX, 0, 3},
{"mm4", RegMMX, 4}, {"mm4", RegMMX, 0, 4},
{"mm5", RegMMX, 5}, {"mm5", RegMMX, 0, 5},
{"mm6", RegMMX, 6}, {"mm6", RegMMX, 0, 6},
{"mm7", RegMMX, 7}, {"mm7", RegMMX, 0, 7},
{"xmm0", RegXMM, 0}, {"xmm0", RegXMM, 0, 0},
{"xmm1", RegXMM, 1}, {"xmm1", RegXMM, 0, 1},
{"xmm2", RegXMM, 2}, {"xmm2", RegXMM, 0, 2},
{"xmm3", RegXMM, 3}, {"xmm3", RegXMM, 0, 3},
{"xmm4", RegXMM, 4}, {"xmm4", RegXMM, 0, 4},
{"xmm5", RegXMM, 5}, {"xmm5", RegXMM, 0, 5},
{"xmm6", RegXMM, 6}, {"xmm6", RegXMM, 0, 6},
{"xmm7", RegXMM, 7} {"xmm7", RegXMM, 0, 7}
}; };
static const reg_entry i386_float_regtab[] = { static const reg_entry i386_float_regtab[] = {
{"st(0)", FloatReg|FloatAcc, 0}, {"st(0)", FloatReg|FloatAcc, 0, 0},
{"st(1)", FloatReg, 1}, {"st(1)", FloatReg, 0, 1},
{"st(2)", FloatReg, 2}, {"st(2)", FloatReg, 0, 2},
{"st(3)", FloatReg, 3}, {"st(3)", FloatReg, 0, 3},
{"st(4)", FloatReg, 4}, {"st(4)", FloatReg, 0, 4},
{"st(5)", FloatReg, 5}, {"st(5)", FloatReg, 0, 5},
{"st(6)", FloatReg, 6}, {"st(6)", FloatReg, 0, 6},
{"st(7)", FloatReg, 7} {"st(7)", FloatReg, 0, 7}
}; };
#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */