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x86: use template for XOP integer comparison, shift, and rotate insns

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These all follow common patterns.
This commit is contained in:
Jan Beulich 2020-03-09 10:14:17 +01:00
parent 3fabc17903
commit 2f13234bc5
3 changed files with 1079 additions and 1160 deletions
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6
opcodes/ChangeLog
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@ -1,3 +1,9 @@
2020-03-09 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
vprot*, vpsha*, and vpshl*.
* i386-tbl.h: Re-generate.
2020-03-09 Jan Beulich <jbeulich@suse.com> 2020-03-09 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps, * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,

113
opcodes/i386-opc.tbl
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@ -2370,88 +2370,22 @@ vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexS
// XOP instructions // XOP instructions
<xop_elem:opc, b:0, w:1, d:2, q:3>
<xop_irel:imm, lt:0, le:1, gt:2, ge:3, eq:4, neq:5, false:6, true:7>
<xop_sign:opc, :00, u:20>
vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vfrczsd, 2, 0x83, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Qword|RegXMM|Unspecified|BaseIndex, RegXMM } vfrczsd, 2, 0x83, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Qword|RegXMM|Unspecified|BaseIndex, RegXMM }
vfrczss, 2, 0x82, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Dword|RegXMM|Unspecified|BaseIndex, RegXMM } vfrczss, 2, 0x82, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Dword|RegXMM|Unspecified|BaseIndex, RegXMM }
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcomb, 4, 0xcc, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vpcom<xop_sign><xop_elem>, 4, 0xcc | 0x<xop_sign:opc> | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|VexOpcode=3|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomd, 4, 0xce, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vpcom<xop_irel><xop_sign><xop_elem>, 3, 0xcc | 0x<xop_sign:opc> | <xop_elem:opc>, <xop_irel:imm>, 1, CpuXOP, Modrm|Vex128|VexOpcode=3|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomq, 4, 0xcf, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomub, 4, 0xec, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomud, 4, 0xee, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomuq, 4, 0xef, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomuw, 4, 0xed, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomw, 4, 0xcd, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcomltb, 3, 0xcc, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomltd, 3, 0xce, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomltq, 3, 0xcf, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomltub, 3, 0xec, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomltud, 3, 0xee, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomltuq, 3, 0xef, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomltuw, 3, 0xed, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomltw, 3, 0xcd, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomleb, 3, 0xcc, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomled, 3, 0xce, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomleq, 3, 0xcf, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomleub, 3, 0xec, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomleud, 3, 0xee, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomleuq, 3, 0xef, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomleuw, 3, 0xed, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomlew, 3, 0xcd, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgtb, 3, 0xcc, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgtd, 3, 0xce, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgtq, 3, 0xcf, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgtub, 3, 0xec, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgtud, 3, 0xee, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgtuq, 3, 0xef, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgtuw, 3, 0xed, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgtw, 3, 0xcd, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgeb, 3, 0xcc, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomged, 3, 0xce, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgeq, 3, 0xcf, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgeub, 3, 0xec, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgeud, 3, 0xee, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgeuq, 3, 0xef, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgeuw, 3, 0xed, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomgew, 3, 0xcd, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomeqb, 3, 0xcc, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomeqd, 3, 0xce, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomeqq, 3, 0xcf, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomequb, 3, 0xec, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomequd, 3, 0xee, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomequq, 3, 0xef, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomequw, 3, 0xed, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomeqw, 3, 0xcd, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomneqb, 3, 0xcc, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomneqd, 3, 0xce, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomneqq, 3, 0xcf, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomnequb, 3, 0xec, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomnequd, 3, 0xee, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomnequq, 3, 0xef, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomnequw, 3, 0xed, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomneqw, 3, 0xcd, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomfalseb, 3, 0xcc, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomfalsed, 3, 0xce, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomfalseq, 3, 0xcf, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomfalseub, 3, 0xec, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomfalseud, 3, 0xee, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomfalseuq, 3, 0xef, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomfalseuw, 3, 0xed, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomfalsew, 3, 0xcd, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomtrueb, 3, 0xcc, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomtrued, 3, 0xce, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomtrueq, 3, 0xcf, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomtrueub, 3, 0xec, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomtrueud, 3, 0xee, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomtrueuq, 3, 0xef, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomtrueuw, 3, 0xed, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomtruew, 3, 0xcd, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vphaddbd, 2, 0xc2, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphaddbd, 2, 0xc2, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
vphaddbq, 2, 0xc3, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphaddbq, 2, 0xc3, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
vphaddbw, 2, 0xc1, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphaddbw, 2, 0xc1, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
@ -2481,34 +2415,13 @@ vpmadcsswd, 4, 0xa6, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|V
vpmadcswd, 4, 0xb6, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vpmadcswd, 4, 0xb6, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpperm, 4, 0xa3, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vpperm, 4, 0xa3, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpperm, 4, 0xa3, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM, RegXMM } vpperm, 4, 0xa3, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM, RegXMM }
vprotb, 3, 0x90, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } vprot<xop_elem>, 3, 0x90 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|VexOpcode=4|VexW0|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vprotb, 3, 0x90, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vprot<xop_elem>, 3, 0x90 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|VexOpcode=4|VexW1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vprotb, 3, 0xc0, None, 1, CpuXOP, Modrm|VexOpcode=3|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } vprot<xop_elem>, 3, 0xc0 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|VexOpcode=3|VexW0|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
vprotd, 3, 0x92, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } vpsha<xop_elem>, 3, 0x98 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|VexOpcode=4|VexW0|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vprotd, 3, 0x92, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vpsha<xop_elem>, 3, 0x98 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|VexOpcode=4|VexW1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vprotd, 3, 0xc2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } vpshl<xop_elem>, 3, 0x94 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|VexOpcode=4|VexW0|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vprotq, 3, 0x93, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } vpshl<xop_elem>, 3, 0x94 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|VexOpcode=4|VexW1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vprotq, 3, 0x93, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vprotq, 3, 0xc3, None, 1, CpuXOP, Modrm|VexOpcode=3|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
vprotw, 3, 0x91, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vprotw, 3, 0x91, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vprotw, 3, 0xc1, None, 1, CpuXOP, Modrm|VexOpcode=3|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
vpshab, 3, 0x98, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vpshab, 3, 0x98, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpshad, 3, 0x9a, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vpshad, 3, 0x9a, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpshaq, 3, 0x9b, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vpshaq, 3, 0x9b, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpshaw, 3, 0x99, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vpshaw, 3, 0x99, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpshlb, 3, 0x94, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vpshlb, 3, 0x94, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpshld, 3, 0x96, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vpshld, 3, 0x96, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpshlq, 3, 0x97, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vpshlq, 3, 0x97, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpshlw, 3, 0x95, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vpshlw, 3, 0x95, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
// LWP instructions // LWP instructions

2120
opcodes/i386-tbl.h
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